1 @c Copyright (C) 1991, 92, 93, 94, 95, 1997 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter MIPS Dependent Features
10 @node Machine Dependencies
11 @chapter MIPS Dependent Features
14 @cindex MIPS processor
15 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
16 different @sc{mips} processors, and MIPS ISA levels I through IV. For
17 information about the @sc{mips} instruction set, see @cite{MIPS RISC
18 Architecture}, by Kane and Heindrich (Prentice-Hall). For an overview
19 of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
20 Programming'' in the same work.
23 * MIPS Opts:: Assembler options
24 * MIPS Object:: ECOFF object code
25 * MIPS Stabs:: Directives for debugging information
26 * MIPS ISA:: Directives to override the ISA level
27 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
28 * MIPS insn:: Directive to mark data as an instruction
29 * MIPS option stack:: Directives to save and restore options
33 @section Assembler options
35 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
39 @cindex @code{-G} option (MIPS)
41 This option sets the largest size of an object that can be referenced
42 implicitly with the @code{gp} register. It is only accepted for targets
43 that use @sc{ecoff} format. The default value is 8.
45 @cindex @code{-EB} option (MIPS)
46 @cindex @code{-EL} option (MIPS)
47 @cindex MIPS big-endian output
48 @cindex MIPS little-endian output
49 @cindex big-endian output, MIPS
50 @cindex little-endian output, MIPS
53 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
54 little-endian output at run time (unlike the other @sc{gnu} development
55 tools, which must be configured for one or the other). Use @samp{-EB}
56 to select big-endian output, and @samp{-EL} for little-endian.
58 @cindex MIPS architecture options
63 Generate code for a particular MIPS Instruction Set Architecture level.
64 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
65 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
66 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
67 @sc{r10000} processors. You can also switch instruction sets during the
68 assembly; see @ref{MIPS ISA,, Directives to override the ISA level}.
71 Assume that 32-bit general purpose registers are available. This
72 affects synthetic instructions such as @code{move}, which will assemble
73 to a 32-bit or a 64-bit instruction depending on this flag. On some
74 MIPS variants there is a 32-bit mode flag; when this flag is set,
75 64-bit instructions generate a trap. Also, some 32-bit OSes only save
76 the 32-bit registers on a context switch, so it is essential never to
77 use the 64-bit registers.
80 Assume that 64-bit general purpose registers are available. This is
81 provided in the interests of symmetry with -gp32.
85 Generate code for the MIPS 16 processor. This is equivalent to putting
86 @samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
87 turns off this option.
91 Cause nops to be inserted if the read of the destination register
92 of an mfhi or mflo instruction occurs in the following two instructions.
96 Generate code for the LSI @sc{r4010} chip. This tells the assembler to
97 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
98 etc.), and to not schedule @samp{nop} instructions around accesses to
99 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
104 Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
105 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
106 instructions around accesses to the @samp{HI} and @samp{LO} registers.
107 @samp{-no-m4650} turns off this option.
113 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
114 @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
115 specific to that chip, and to schedule for that chip's hazards.
117 @item -mcpu=@var{cpu}
118 Generate code for a particular MIPS cpu. It is exactly equivalent to
119 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
120 understood. Valid @var{cpu} value are:
147 @cindex @code{-nocpp} ignored (MIPS)
149 This option is ignored. It is accepted for command-line compatibility with
150 other assemblers, which use it to turn off C style preprocessing. With
151 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
152 @sc{gnu} assembler itself never runs the C preprocessor.
154 @item --construct-floats
155 @itemx --no-construct-floats
156 @cindex --construct-floats
157 @cindex --no-construct-floats
158 The @code{--no-construct-floats} option disables the construction of
159 double width floating point constants by loading the two halves of the
160 value into the two single width floating point registers that make up
161 the double width register. This feature is useful if the processor
162 support the FR bit in its status register, and this bit is known (by
163 the programmer) to be set. This bit prevents the aliasing of the double
164 width register by the single width registers.
166 By default @code{--construct-floats} is selected, allowing construction
167 of these floating point constants.
171 @c FIXME! (1) reflect these options (next item too) in option summaries;
172 @c (2) stop teasing, say _which_ instructions expanded _how_.
173 @code{@value{AS}} automatically macro expands certain division and
174 multiplication instructions to check for overflow and division by zero. This
175 option causes @code{@value{AS}} to generate code to take a trap exception
176 rather than a break exception when an error is detected. The trap instructions
177 are only supported at Instruction Set Architecture level 2 and higher.
181 Generate code to take a break exception rather than a trap exception when an
182 error is detected. This is the default.
186 @section MIPS ECOFF object code
188 @cindex ECOFF sections
189 @cindex MIPS ECOFF sections
190 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
191 besides the usual @code{.text}, @code{.data} and @code{.bss}. The
192 additional sections are @code{.rdata}, used for read-only data,
193 @code{.sdata}, used for small data, and @code{.sbss}, used for small
196 @cindex small objects, MIPS ECOFF
197 @cindex @code{gp} register, MIPS
198 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
199 register to form the address of a ``small object''. Any object in the
200 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
201 For external objects, or for objects in the @code{.bss} section, you can use
202 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
203 @code{$gp}; the default value is 8, meaning that a reference to any object
204 eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
205 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
206 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
207 or @code{sbss} in any case). The size of an object in the @code{.bss} section
208 is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
209 size of an external object may be set with the @code{.extern} directive. For
210 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
211 in length, whie leaving @code{sym} otherwise undefined.
213 Using small @sc{ecoff} objects requires linker support, and assumes that the
214 @code{$gp} register is correctly initialized (normally done automatically by
215 the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
219 @section Directives for debugging information
221 @cindex MIPS debugging directives
222 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
223 generating debugging information which are not support by traditional @sc{mips}
224 assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
225 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
226 @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
227 generated by the three @code{.stab} directives can only be read by @sc{gdb},
228 not by traditional @sc{mips} debuggers (this enhancement is required to fully
229 support C++ debugging). These directives are primarily used by compilers, not
230 assembly language programmers!
233 @section Directives to override the ISA level
235 @cindex MIPS ISA override
236 @kindex @code{.set mips@var{n}}
237 @sc{gnu} @code{@value{AS}} supports an additional directive to change
238 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
239 mips@var{n}}. @var{n} should be a number from 0 to 4. A value from 1
240 to 4 makes the assembler accept instructions for the corresponding
241 @sc{isa} level, from that point on in the assembly. @code{.set
242 mips@var{n}} affects not only which instructions are permitted, but also
243 how certain macros are expanded. @code{.set mips0} restores the
244 @sc{isa} level to its original level: either the level you selected with
245 command line options, or the default for your configuration. You can
246 use this feature to permit specific @sc{r4000} instructions while
247 assembling in 32 bit mode. Use this directive with care!
249 The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
250 in which it will assemble instructions for the MIPS 16 processor. Use
251 @samp{.set nomips16} to return to normal 32 bit mode.
253 Traditional @sc{mips} assemblers do not support this directive.
255 @node MIPS autoextend
256 @section Directives for extending MIPS 16 bit instructions
258 @kindex @code{.set autoextend}
259 @kindex @code{.set noautoextend}
260 By default, MIPS 16 instructions are automatically extended to 32 bits
261 when necessary. The directive @samp{.set noautoextend} will turn this
262 off. When @samp{.set noautoextend} is in effect, any 32 bit instruction
263 must be explicitly extended with the @samp{.e} modifier (e.g.,
264 @samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used
265 to once again automatically extend instructions when necessary.
267 This directive is only meaningful when in MIPS 16 mode. Traditional
268 @sc{mips} assemblers do not support this directive.
271 @section Directive to mark data as an instruction
274 The @code{.insn} directive tells @code{@value{AS}} that the following
275 data is actually instructions. This makes a difference in MIPS 16 mode:
276 when loading the address of a label which precedes instructions,
277 @code{@value{AS}} automatically adds 1 to the value, so that jumping to
278 the loaded address will do the right thing.
280 @node MIPS option stack
281 @section Directives to save and restore options
283 @cindex MIPS option stack
284 @kindex @code{.set push}
285 @kindex @code{.set pop}
286 The directives @code{.set push} and @code{.set pop} may be used to save
287 and restore the current settings for all the options which are
288 controlled by @code{.set}. The @code{.set push} directive saves the
289 current settings on a stack. The @code{.set pop} directive pops the
290 stack and restores the settings.
292 These directives can be useful inside an macro which must change an
293 option such as the ISA level or instruction reordering but does not want
294 to change the state of the code which invoked the macro.
296 Traditional @sc{mips} assemblers do not support these directives.