1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
9 @chapter MIPS Dependent Features
12 @node Machine Dependencies
13 @chapter MIPS Dependent Features
16 @cindex MIPS processor
17 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
18 different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
19 and MIPS64. For information about the @sc{mips} instruction set, see
20 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
21 For an overview of @sc{mips} assembly conventions, see ``Appendix D:
22 Assembly Language Programming'' in the same work.
25 * MIPS Opts:: Assembler options
26 * MIPS Object:: ECOFF object code
27 * MIPS Stabs:: Directives for debugging information
28 * MIPS ISA:: Directives to override the ISA level
29 * MIPS symbol sizes:: Directives to override the size of symbols
30 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
31 * MIPS insn:: Directive to mark data as an instruction
32 * MIPS option stack:: Directives to save and restore options
33 * MIPS ASE instruction generation overrides:: Directives to control
34 generation of MIPS ASE instructions
35 * MIPS floating-point:: Directives to override floating-point options
36 * MIPS Syntax:: MIPS specific syntactical considerations
40 @section Assembler options
42 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
46 @cindex @code{-G} option (MIPS)
48 This option sets the largest size of an object that can be referenced
49 implicitly with the @code{gp} register. It is only accepted for targets
50 that use @sc{ecoff} format. The default value is 8.
52 @cindex @code{-EB} option (MIPS)
53 @cindex @code{-EL} option (MIPS)
54 @cindex MIPS big-endian output
55 @cindex MIPS little-endian output
56 @cindex big-endian output, MIPS
57 @cindex little-endian output, MIPS
60 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
61 little-endian output at run time (unlike the other @sc{gnu} development
62 tools, which must be configured for one or the other). Use @samp{-EB}
63 to select big-endian output, and @samp{-EL} for little-endian.
66 @cindex PIC selection, MIPS
67 @cindex @option{-KPIC} option, MIPS
68 Generate SVR4-style PIC. This option tells the assembler to generate
69 SVR4-style position-independent macro expansions. It also tells the
70 assembler to mark the output file as PIC.
73 @cindex @option{-mvxworks-pic} option, MIPS
74 Generate VxWorks PIC. This option tells the assembler to generate
75 VxWorks-style position-independent macro expansions.
77 @cindex MIPS architecture options
87 Generate code for a particular MIPS Instruction Set Architecture level.
88 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
89 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
90 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
91 @sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
92 @samp{-mips64}, and @samp{-mips64r2}
94 @sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
95 and @sc{MIPS64 Release 2}
96 ISA processors, respectively. You can also switch
97 instruction sets during the assembly; see @ref{MIPS ISA, Directives to
98 override the ISA level}.
102 Some macros have different expansions for 32-bit and 64-bit registers.
103 The register sizes are normally inferred from the ISA and ABI, but these
104 flags force a certain group of registers to be treated as 32 bits wide at
105 all times. @samp{-mgp32} controls the size of general-purpose registers
106 and @samp{-mfp32} controls the size of floating-point registers.
108 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
109 of registers to be changed for parts of an object. The default value is
110 restored by @code{.set gp=default} and @code{.set fp=default}.
112 On some MIPS variants there is a 32-bit mode flag; when this flag is
113 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
114 save the 32-bit registers on a context switch, so it is essential never
115 to use the 64-bit registers.
119 Assume that 64-bit registers are available. This is provided in the
120 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
122 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
123 of registers to be changed for parts of an object. The default value is
124 restored by @code{.set gp=default} and @code{.set fp=default}.
128 Generate code for the MIPS 16 processor. This is equivalent to putting
129 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
130 turns off this option.
133 @itemx -mno-micromips
134 Generate code for the microMIPS processor. This is equivalent to putting
135 @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
136 turns off this option. This is equivalent to putting @code{.set nomicromips}
137 at the start of the assembly file.
140 @itemx -mno-smartmips
141 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
142 provides a number of new instructions which target smartcard and
143 cryptographic applications. This is equivalent to putting
144 @code{.set smartmips} at the start of the assembly file.
145 @samp{-mno-smartmips} turns off this option.
149 Generate code for the MIPS-3D Application Specific Extension.
150 This tells the assembler to accept MIPS-3D instructions.
151 @samp{-no-mips3d} turns off this option.
155 Generate code for the MDMX Application Specific Extension.
156 This tells the assembler to accept MDMX instructions.
157 @samp{-no-mdmx} turns off this option.
161 Generate code for the DSP Release 1 Application Specific Extension.
162 This tells the assembler to accept DSP Release 1 instructions.
163 @samp{-mno-dsp} turns off this option.
167 Generate code for the DSP Release 2 Application Specific Extension.
168 This option implies -mdsp.
169 This tells the assembler to accept DSP Release 2 instructions.
170 @samp{-mno-dspr2} turns off this option.
174 Generate code for the MT Application Specific Extension.
175 This tells the assembler to accept MT instructions.
176 @samp{-mno-mt} turns off this option.
180 Generate code for the MCU Application Specific Extension.
181 This tells the assembler to accept MCU instructions.
182 @samp{-mno-mcu} turns off this option.
186 Cause nops to be inserted if the read of the destination register
187 of an mfhi or mflo instruction occurs in the following two instructions.
189 @item -mfix-loongson2f-jump
190 @itemx -mno-fix-loongson2f-jump
191 Eliminate instruction fetch from outside 256M region to work around the
192 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
193 the kernel may crash. The issue has been solved in latest processor
194 batches, but this fix has no side effect to them.
196 @item -mfix-loongson2f-nop
197 @itemx -mno-fix-loongson2f-nop
198 Replace nops by @code{or at,at,zero} to work around the Loongson2F
199 @samp{nop} errata. Without it, under extreme cases, cpu might
200 deadlock. The issue has been solved in latest loongson2f batches, but
201 this fix has no side effect to them.
204 @itemx -mno-fix-vr4120
205 Insert nops to work around certain VR4120 errata. This option is
206 intended to be used on GCC-generated code: it is not designed to catch
207 all problems in hand-written assembler code.
210 @itemx -mno-fix-vr4130
211 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
215 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
218 @itemx -mno-fix-cn63xxp1
219 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
220 certain CN63XXP1 errata.
224 Generate code for the LSI @sc{r4010} chip. This tells the assembler to
225 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
226 etc.), and to not schedule @samp{nop} instructions around accesses to
227 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
232 Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
233 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
234 instructions around accesses to the @samp{HI} and @samp{LO} registers.
235 @samp{-no-m4650} turns off this option.
241 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
242 @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
243 specific to that chip, and to schedule for that chip's hazards.
245 @item -march=@var{cpu}
246 Generate code for a particular MIPS cpu. It is exactly equivalent to
247 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
248 understood. Valid @var{cpu} value are:
332 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
333 accepted as synonyms for @samp{@var{n}f1_1}. These values are
336 @item -mtune=@var{cpu}
337 Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are
338 identical to @samp{-march=@var{cpu}}.
340 @item -mabi=@var{abi}
341 Record which ABI the source code uses. The recognized arguments
342 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
348 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
349 the beginning of the assembler input. @xref{MIPS symbol sizes}.
351 @cindex @code{-nocpp} ignored (MIPS)
353 This option is ignored. It is accepted for command-line compatibility with
354 other assemblers, which use it to turn off C style preprocessing. With
355 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
356 @sc{gnu} assembler itself never runs the C preprocessor.
360 Disable or enable floating-point instructions. Note that by default
361 floating-point instructions are always allowed even with CPU targets
362 that don't have support for these instructions.
365 @itemx -mdouble-float
366 Disable or enable double-precision floating-point operations. Note
367 that by default double-precision floating-point operations are always
368 allowed even with CPU targets that don't have support for these
371 @item --construct-floats
372 @itemx --no-construct-floats
373 The @code{--no-construct-floats} option disables the construction of
374 double width floating point constants by loading the two halves of the
375 value into the two single width floating point registers that make up
376 the double width register. This feature is useful if the processor
377 support the FR bit in its status register, and this bit is known (by
378 the programmer) to be set. This bit prevents the aliasing of the double
379 width register by the single width registers.
381 By default @code{--construct-floats} is selected, allowing construction
382 of these floating point constants.
386 @c FIXME! (1) reflect these options (next item too) in option summaries;
387 @c (2) stop teasing, say _which_ instructions expanded _how_.
388 @code{@value{AS}} automatically macro expands certain division and
389 multiplication instructions to check for overflow and division by zero. This
390 option causes @code{@value{AS}} to generate code to take a trap exception
391 rather than a break exception when an error is detected. The trap instructions
392 are only supported at Instruction Set Architecture level 2 and higher.
396 Generate code to take a break exception rather than a trap exception when an
397 error is detected. This is the default.
401 Control generation of @code{.pdr} sections. Off by default on IRIX, on
406 When generating code using the Unix calling conventions (selected by
407 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
408 which can go into a shared library. The @samp{-mno-shared} option
409 tells gas to generate code which uses the calling convention, but can
410 not go into a shared library. The resulting code is slightly more
411 efficient. This option only affects the handling of the
412 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
416 @section MIPS ECOFF object code
418 @cindex ECOFF sections
419 @cindex MIPS ECOFF sections
420 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
421 besides the usual @code{.text}, @code{.data} and @code{.bss}. The
422 additional sections are @code{.rdata}, used for read-only data,
423 @code{.sdata}, used for small data, and @code{.sbss}, used for small
426 @cindex small objects, MIPS ECOFF
427 @cindex @code{gp} register, MIPS
428 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
429 register to form the address of a ``small object''. Any object in the
430 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
431 For external objects, or for objects in the @code{.bss} section, you can use
432 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
433 @code{$gp}; the default value is 8, meaning that a reference to any object
434 eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
435 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
436 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
437 or @code{sbss} in any case). The size of an object in the @code{.bss} section
438 is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
439 size of an external object may be set with the @code{.extern} directive. For
440 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
441 in length, whie leaving @code{sym} otherwise undefined.
443 Using small @sc{ecoff} objects requires linker support, and assumes that the
444 @code{$gp} register is correctly initialized (normally done automatically by
445 the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
449 @section Directives for debugging information
451 @cindex MIPS debugging directives
452 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
453 generating debugging information which are not support by traditional @sc{mips}
454 assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
455 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
456 @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
457 generated by the three @code{.stab} directives can only be read by @sc{gdb},
458 not by traditional @sc{mips} debuggers (this enhancement is required to fully
459 support C++ debugging). These directives are primarily used by compilers, not
460 assembly language programmers!
462 @node MIPS symbol sizes
463 @section Directives to override the size of symbols
465 @cindex @code{.set sym32}
466 @cindex @code{.set nosym32}
467 The n64 ABI allows symbols to have any 64-bit value. Although this
468 provides a great deal of flexibility, it means that some macros have
469 much longer expansions than their 32-bit counterparts. For example,
470 the non-PIC expansion of @samp{dla $4,sym} is usually:
475 daddiu $4,$4,%higher(sym)
476 daddiu $1,$1,%lo(sym)
481 whereas the 32-bit expansion is simply:
485 daddiu $4,$4,%lo(sym)
488 n64 code is sometimes constructed in such a way that all symbolic
489 constants are known to have 32-bit values, and in such cases, it's
490 preferable to use the 32-bit expansion instead of the 64-bit
493 You can use the @code{.set sym32} directive to tell the assembler
494 that, from this point on, all expressions of the form
495 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
496 have 32-bit values. For example:
505 will cause the assembler to treat @samp{sym}, @code{sym+16} and
506 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
507 addresses is not affected.
509 The directive @code{.set nosym32} ends a @code{.set sym32} block and
510 reverts to the normal behavior. It is also possible to change the
511 symbol size using the command-line options @option{-msym32} and
514 These options and directives are always accepted, but at present,
515 they have no effect for anything other than n64.
518 @section Directives to override the ISA level
520 @cindex MIPS ISA override
521 @kindex @code{.set mips@var{n}}
522 @sc{gnu} @code{@value{AS}} supports an additional directive to change
523 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
524 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
526 The values other than 0 make the assembler accept instructions
527 for the corresponding @sc{isa} level, from that point on in the
528 assembly. @code{.set mips@var{n}} affects not only which instructions
529 are permitted, but also how certain macros are expanded. @code{.set
530 mips0} restores the @sc{isa} level to its original level: either the
531 level you selected with command line options, or the default for your
532 configuration. You can use this feature to permit specific @sc{mips3}
533 instructions while assembling in 32 bit mode. Use this directive with
536 @cindex MIPS CPU override
537 @kindex @code{.set arch=@var{cpu}}
538 The @code{.set arch=@var{cpu}} directive provides even finer control.
539 It changes the effective CPU target and allows the assembler to use
540 instructions specific to a particular CPU. All CPUs supported by the
541 @samp{-march} command line option are also selectable by this directive.
542 The original value is restored by @code{.set arch=default}.
544 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
545 in which it will assemble instructions for the MIPS 16 processor. Use
546 @code{.set nomips16} to return to normal 32 bit mode.
548 Traditional @sc{mips} assemblers do not support this directive.
550 The directive @code{.set micromips} puts the assembler into microMIPS mode,
551 in which it will assemble instructions for the microMIPS processor. Use
552 @code{.set nomicromips} to return to normal 32 bit mode.
554 Traditional @sc{mips} assemblers do not support this directive.
556 @node MIPS autoextend
557 @section Directives for extending MIPS 16 bit instructions
559 @kindex @code{.set autoextend}
560 @kindex @code{.set noautoextend}
561 By default, MIPS 16 instructions are automatically extended to 32 bits
562 when necessary. The directive @code{.set noautoextend} will turn this
563 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
564 must be explicitly extended with the @code{.e} modifier (e.g.,
565 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
566 to once again automatically extend instructions when necessary.
568 This directive is only meaningful when in MIPS 16 mode. Traditional
569 @sc{mips} assemblers do not support this directive.
572 @section Directive to mark data as an instruction
575 The @code{.insn} directive tells @code{@value{AS}} that the following
576 data is actually instructions. This makes a difference in MIPS 16 and
577 microMIPS modes: when loading the address of a label which precedes
578 instructions, @code{@value{AS}} automatically adds 1 to the value, so
579 that jumping to the loaded address will do the right thing.
581 @kindex @code{.global}
582 The @code{.global} and @code{.globl} directives supported by
583 @code{@value{AS}} will by default mark the symbol as pointing to a
584 region of data not code. This means that, for example, any
585 instructions following such a symbol will not be disassembled by
586 @code{objdump} as it will regard them as data. To change this
587 behaviour an optional section name can be placed after the symbol name
588 in the @code{.global} directive. If this section exists and is known
589 to be a code section, then the symbol will be marked as poiting at
590 code not data. Ie the syntax for the directive is:
592 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
594 Here is a short example:
597 .global foo .text, bar, baz .data
607 @node MIPS option stack
608 @section Directives to save and restore options
610 @cindex MIPS option stack
611 @kindex @code{.set push}
612 @kindex @code{.set pop}
613 The directives @code{.set push} and @code{.set pop} may be used to save
614 and restore the current settings for all the options which are
615 controlled by @code{.set}. The @code{.set push} directive saves the
616 current settings on a stack. The @code{.set pop} directive pops the
617 stack and restores the settings.
619 These directives can be useful inside an macro which must change an
620 option such as the ISA level or instruction reordering but does not want
621 to change the state of the code which invoked the macro.
623 Traditional @sc{mips} assemblers do not support these directives.
625 @node MIPS ASE instruction generation overrides
626 @section Directives to control generation of MIPS ASE instructions
628 @cindex MIPS MIPS-3D instruction generation override
629 @kindex @code{.set mips3d}
630 @kindex @code{.set nomips3d}
631 The directive @code{.set mips3d} makes the assembler accept instructions
632 from the MIPS-3D Application Specific Extension from that point on
633 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
634 instructions from being accepted.
636 @cindex SmartMIPS instruction generation override
637 @kindex @code{.set smartmips}
638 @kindex @code{.set nosmartmips}
639 The directive @code{.set smartmips} makes the assembler accept
640 instructions from the SmartMIPS Application Specific Extension to the
641 MIPS32 @sc{isa} from that point on in the assembly. The
642 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
645 @cindex MIPS MDMX instruction generation override
646 @kindex @code{.set mdmx}
647 @kindex @code{.set nomdmx}
648 The directive @code{.set mdmx} makes the assembler accept instructions
649 from the MDMX Application Specific Extension from that point on
650 in the assembly. The @code{.set nomdmx} directive prevents MDMX
651 instructions from being accepted.
653 @cindex MIPS DSP Release 1 instruction generation override
654 @kindex @code{.set dsp}
655 @kindex @code{.set nodsp}
656 The directive @code{.set dsp} makes the assembler accept instructions
657 from the DSP Release 1 Application Specific Extension from that point
658 on in the assembly. The @code{.set nodsp} directive prevents DSP
659 Release 1 instructions from being accepted.
661 @cindex MIPS DSP Release 2 instruction generation override
662 @kindex @code{.set dspr2}
663 @kindex @code{.set nodspr2}
664 The directive @code{.set dspr2} makes the assembler accept instructions
665 from the DSP Release 2 Application Specific Extension from that point
666 on in the assembly. This dirctive implies @code{.set dsp}. The
667 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
670 @cindex MIPS MT instruction generation override
671 @kindex @code{.set mt}
672 @kindex @code{.set nomt}
673 The directive @code{.set mt} makes the assembler accept instructions
674 from the MT Application Specific Extension from that point on
675 in the assembly. The @code{.set nomt} directive prevents MT
676 instructions from being accepted.
678 @cindex MIPS MCU instruction generation override
679 @kindex @code{.set mcu}
680 @kindex @code{.set nomcu}
681 The directive @code{.set mcu} makes the assembler accept instructions
682 from the MCU Application Specific Extension from that point on
683 in the assembly. The @code{.set nomcu} directive prevents MCU
684 instructions from being accepted.
686 Traditional @sc{mips} assemblers do not support these directives.
688 @node MIPS floating-point
689 @section Directives to override floating-point options
691 @cindex Disable floating-point instructions
692 @kindex @code{.set softfloat}
693 @kindex @code{.set hardfloat}
694 The directives @code{.set softfloat} and @code{.set hardfloat} provide
695 finer control of disabling and enabling float-point instructions.
696 These directives always override the default (that hard-float
697 instructions are accepted) or the command-line options
698 (@samp{-msoft-float} and @samp{-mhard-float}).
700 @cindex Disable single-precision floating-point operations
701 @kindex @code{.set singlefloat}
702 @kindex @code{.set doublefloat}
703 The directives @code{.set singlefloat} and @code{.set doublefloat}
704 provide finer control of disabling and enabling double-precision
705 float-point operations. These directives always override the default
706 (that double-precision operations are accepted) or the command-line
707 options (@samp{-msingle-float} and @samp{-mdouble-float}).
709 Traditional @sc{mips} assemblers do not support these directives.
712 @section Syntactical considerations for the MIPS assembler
714 * MIPS-Chars:: Special Characters
718 @subsection Special Characters
720 @cindex line comment character, MIPS
721 @cindex MIPS line comment character
722 The presence of a @samp{#} on a line indicates the start of a comment
723 that extends to the end of the current line.
725 If a @samp{#} appears as the first character of a line, the whole line
726 is treated as a comment, but in this case the line can also be a
727 logical line number directive (@pxref{Comments}) or a
728 preprocessor control command (@pxref{Preprocessing}).
730 @cindex line separator, MIPS
731 @cindex statement separator, MIPS
732 @cindex MIPS line separator
733 The @samp{;} character can be used to separate statements on the same