1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
8 @chapter MIPS Dependent Features
11 @node Machine Dependencies
12 @chapter MIPS Dependent Features
15 @cindex MIPS processor
16 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
17 different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
18 and MIPS64. For information about the @sc{mips} instruction set, see
19 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
20 For an overview of @sc{mips} assembly conventions, see ``Appendix D:
21 Assembly Language Programming'' in the same work.
24 * MIPS Opts:: Assembler options
25 * MIPS Object:: ECOFF object code
26 * MIPS Stabs:: Directives for debugging information
27 * MIPS ISA:: Directives to override the ISA level
28 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
29 * MIPS insn:: Directive to mark data as an instruction
30 * MIPS option stack:: Directives to save and restore options
34 @section Assembler options
36 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
40 @cindex @code{-G} option (MIPS)
42 This option sets the largest size of an object that can be referenced
43 implicitly with the @code{gp} register. It is only accepted for targets
44 that use @sc{ecoff} format. The default value is 8.
46 @cindex @code{-EB} option (MIPS)
47 @cindex @code{-EL} option (MIPS)
48 @cindex MIPS big-endian output
49 @cindex MIPS little-endian output
50 @cindex big-endian output, MIPS
51 @cindex little-endian output, MIPS
54 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
55 little-endian output at run time (unlike the other @sc{gnu} development
56 tools, which must be configured for one or the other). Use @samp{-EB}
57 to select big-endian output, and @samp{-EL} for little-endian.
59 @cindex MIPS architecture options
67 Generate code for a particular MIPS Instruction Set Architecture level.
68 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
69 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
70 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
71 @sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, and
72 @samp{-mips64} correspond to generic @sc{MIPS V}, @sc{MIPS32}, and
73 @sc{MIPS64} ISA processors, respectively. You can also switch
74 instruction sets during the assembly; see @ref{MIPS ISA, Directives to
75 override the ISA level}.
79 Some macros have different expansions for 32-bit and 64-bit registers.
80 The register sizes are normally inferred from the ISA and ABI, but these
81 flags force a certain group of registers to be treated as 32 bits wide at
82 all times. @samp{-mgp32} controls the size of general-purpose registers
83 and @samp{-mfp32} controls the size of floating-point registers.
85 On some MIPS variants there is a 32-bit mode flag; when this flag is
86 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
87 save the 32-bit registers on a context switch, so it is essential never
88 to use the 64-bit registers.
91 Assume that 64-bit general purpose registers are available. This is
92 provided in the interests of symmetry with -gp32.
96 Generate code for the MIPS 16 processor. This is equivalent to putting
97 @samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
98 turns off this option.
102 Cause nops to be inserted if the read of the destination register
103 of an mfhi or mflo instruction occurs in the following two instructions.
107 Generate code for the LSI @sc{r4010} chip. This tells the assembler to
108 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
109 etc.), and to not schedule @samp{nop} instructions around accesses to
110 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
115 Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
116 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
117 instructions around accesses to the @samp{HI} and @samp{LO} registers.
118 @samp{-no-m4650} turns off this option.
124 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
125 @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
126 specific to that chip, and to schedule for that chip's hazards.
128 @item -march=@var{cpu}
129 Generate code for a particular MIPS cpu. It is exactly equivalent to
130 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
131 understood. Valid @var{cpu} value are:
160 @item -mtune=@var{cpu}
161 Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are
162 identical to @samp{-march=@var{cpu}}.
164 @item -mcpu=@var{cpu}
165 Generate code and schedule for a particular MIPS cpu. This is exactly
166 equivalent to @samp{-march=@var{cpu}} and @samp{-mtune=@var{cpu}}. Valid
167 @var{cpu} values are identical to @samp{-march=@var{cpu}}.
168 Use of this option is discouraged.
171 @cindex @code{-nocpp} ignored (MIPS)
173 This option is ignored. It is accepted for command-line compatibility with
174 other assemblers, which use it to turn off C style preprocessing. With
175 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
176 @sc{gnu} assembler itself never runs the C preprocessor.
178 @item --construct-floats
179 @itemx --no-construct-floats
180 @cindex --construct-floats
181 @cindex --no-construct-floats
182 The @code{--no-construct-floats} option disables the construction of
183 double width floating point constants by loading the two halves of the
184 value into the two single width floating point registers that make up
185 the double width register. This feature is useful if the processor
186 support the FR bit in its status register, and this bit is known (by
187 the programmer) to be set. This bit prevents the aliasing of the double
188 width register by the single width registers.
190 By default @code{--construct-floats} is selected, allowing construction
191 of these floating point constants.
195 @c FIXME! (1) reflect these options (next item too) in option summaries;
196 @c (2) stop teasing, say _which_ instructions expanded _how_.
197 @code{@value{AS}} automatically macro expands certain division and
198 multiplication instructions to check for overflow and division by zero. This
199 option causes @code{@value{AS}} to generate code to take a trap exception
200 rather than a break exception when an error is detected. The trap instructions
201 are only supported at Instruction Set Architecture level 2 and higher.
205 Generate code to take a break exception rather than a trap exception when an
206 error is detected. This is the default.
209 When this option is used, @code{@value{AS}} will issue a warning every
210 time it generates a nop instruction from a macro.
214 @section MIPS ECOFF object code
216 @cindex ECOFF sections
217 @cindex MIPS ECOFF sections
218 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
219 besides the usual @code{.text}, @code{.data} and @code{.bss}. The
220 additional sections are @code{.rdata}, used for read-only data,
221 @code{.sdata}, used for small data, and @code{.sbss}, used for small
224 @cindex small objects, MIPS ECOFF
225 @cindex @code{gp} register, MIPS
226 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
227 register to form the address of a ``small object''. Any object in the
228 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
229 For external objects, or for objects in the @code{.bss} section, you can use
230 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
231 @code{$gp}; the default value is 8, meaning that a reference to any object
232 eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
233 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
234 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
235 or @code{sbss} in any case). The size of an object in the @code{.bss} section
236 is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
237 size of an external object may be set with the @code{.extern} directive. For
238 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
239 in length, whie leaving @code{sym} otherwise undefined.
241 Using small @sc{ecoff} objects requires linker support, and assumes that the
242 @code{$gp} register is correctly initialized (normally done automatically by
243 the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
247 @section Directives for debugging information
249 @cindex MIPS debugging directives
250 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
251 generating debugging information which are not support by traditional @sc{mips}
252 assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
253 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
254 @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
255 generated by the three @code{.stab} directives can only be read by @sc{gdb},
256 not by traditional @sc{mips} debuggers (this enhancement is required to fully
257 support C++ debugging). These directives are primarily used by compilers, not
258 assembly language programmers!
261 @section Directives to override the ISA level
263 @cindex MIPS ISA override
264 @kindex @code{.set mips@var{n}}
265 @sc{gnu} @code{@value{AS}} supports an additional directive to change
266 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
267 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32 or 64.
268 The values 1 to 5, 32, and 64 make the assembler accept instructions
269 for the corresponding @sc{isa} level, from that point on in the
270 assembly. @code{.set mips@var{n}} affects not only which instructions
271 are permitted, but also how certain macros are expanded. @code{.set
272 mips0} restores the @sc{isa} level to its original level: either the
273 level you selected with command line options, or the default for your
274 configuration. You can use this feature to permit specific @sc{r4000}
275 instructions while assembling in 32 bit mode. Use this directive with
278 The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
279 in which it will assemble instructions for the MIPS 16 processor. Use
280 @samp{.set nomips16} to return to normal 32 bit mode.
282 Traditional @sc{mips} assemblers do not support this directive.
284 @node MIPS autoextend
285 @section Directives for extending MIPS 16 bit instructions
287 @kindex @code{.set autoextend}
288 @kindex @code{.set noautoextend}
289 By default, MIPS 16 instructions are automatically extended to 32 bits
290 when necessary. The directive @samp{.set noautoextend} will turn this
291 off. When @samp{.set noautoextend} is in effect, any 32 bit instruction
292 must be explicitly extended with the @samp{.e} modifier (e.g.,
293 @samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used
294 to once again automatically extend instructions when necessary.
296 This directive is only meaningful when in MIPS 16 mode. Traditional
297 @sc{mips} assemblers do not support this directive.
300 @section Directive to mark data as an instruction
303 The @code{.insn} directive tells @code{@value{AS}} that the following
304 data is actually instructions. This makes a difference in MIPS 16 mode:
305 when loading the address of a label which precedes instructions,
306 @code{@value{AS}} automatically adds 1 to the value, so that jumping to
307 the loaded address will do the right thing.
309 @node MIPS option stack
310 @section Directives to save and restore options
312 @cindex MIPS option stack
313 @kindex @code{.set push}
314 @kindex @code{.set pop}
315 The directives @code{.set push} and @code{.set pop} may be used to save
316 and restore the current settings for all the options which are
317 controlled by @code{.set}. The @code{.set push} directive saves the
318 current settings on a stack. The @code{.set pop} directive pops the
319 stack and restores the settings.
321 These directives can be useful inside an macro which must change an
322 option such as the ISA level or instruction reordering but does not want
323 to change the state of the code which invoked the macro.
325 Traditional @sc{mips} assemblers do not support these directives.