1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
8 @chapter MIPS Dependent Features
11 @node Machine Dependencies
12 @chapter MIPS Dependent Features
15 @cindex MIPS processor
16 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
17 different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
18 and MIPS64. For information about the @sc{mips} instruction set, see
19 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
20 For an overview of @sc{mips} assembly conventions, see ``Appendix D:
21 Assembly Language Programming'' in the same work.
24 * MIPS Opts:: Assembler options
25 * MIPS Object:: ECOFF object code
26 * MIPS Stabs:: Directives for debugging information
27 * MIPS ISA:: Directives to override the ISA level
28 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
29 * MIPS insn:: Directive to mark data as an instruction
30 * MIPS option stack:: Directives to save and restore options
34 @section Assembler options
36 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
40 @cindex @code{-G} option (MIPS)
42 This option sets the largest size of an object that can be referenced
43 implicitly with the @code{gp} register. It is only accepted for targets
44 that use @sc{ecoff} format. The default value is 8.
46 @cindex @code{-EB} option (MIPS)
47 @cindex @code{-EL} option (MIPS)
48 @cindex MIPS big-endian output
49 @cindex MIPS little-endian output
50 @cindex big-endian output, MIPS
51 @cindex little-endian output, MIPS
54 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
55 little-endian output at run time (unlike the other @sc{gnu} development
56 tools, which must be configured for one or the other). Use @samp{-EB}
57 to select big-endian output, and @samp{-EL} for little-endian.
59 @cindex MIPS architecture options
67 Generate code for a particular MIPS Instruction Set Architecture level.
68 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
69 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
70 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
71 @sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, and
72 @samp{-mips64} correspond to generic @sc{MIPS V}, @sc{MIPS32}, and
73 @sc{MIPS64} ISA processors, respectively. You can also switch
74 instruction sets during the assembly; see @ref{MIPS ISA, Directives to
75 override the ISA level}.
78 Assume that 32-bit general purpose registers are available. This
79 affects synthetic instructions such as @code{move}, which will assemble
80 to a 32-bit or a 64-bit instruction depending on this flag. On some
81 MIPS variants there is a 32-bit mode flag; when this flag is set,
82 64-bit instructions generate a trap. Also, some 32-bit OSes only save
83 the 32-bit registers on a context switch, so it is essential never to
84 use the 64-bit registers.
87 Assume that 64-bit general purpose registers are available. This is
88 provided in the interests of symmetry with -gp32.
92 Generate code for the MIPS 16 processor. This is equivalent to putting
93 @samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
94 turns off this option.
98 Cause nops to be inserted if the read of the destination register
99 of an mfhi or mflo instruction occurs in the following two instructions.
103 Generate code for the LSI @sc{r4010} chip. This tells the assembler to
104 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
105 etc.), and to not schedule @samp{nop} instructions around accesses to
106 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
111 Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
112 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
113 instructions around accesses to the @samp{HI} and @samp{LO} registers.
114 @samp{-no-m4650} turns off this option.
120 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
121 @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
122 specific to that chip, and to schedule for that chip's hazards.
124 @item -mcpu=@var{cpu}
125 Generate code for a particular MIPS cpu. It is exactly equivalent to
126 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
127 understood. Valid @var{cpu} value are:
156 @cindex @code{-nocpp} ignored (MIPS)
158 This option is ignored. It is accepted for command-line compatibility with
159 other assemblers, which use it to turn off C style preprocessing. With
160 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
161 @sc{gnu} assembler itself never runs the C preprocessor.
163 @item --construct-floats
164 @itemx --no-construct-floats
165 @cindex --construct-floats
166 @cindex --no-construct-floats
167 The @code{--no-construct-floats} option disables the construction of
168 double width floating point constants by loading the two halves of the
169 value into the two single width floating point registers that make up
170 the double width register. This feature is useful if the processor
171 support the FR bit in its status register, and this bit is known (by
172 the programmer) to be set. This bit prevents the aliasing of the double
173 width register by the single width registers.
175 By default @code{--construct-floats} is selected, allowing construction
176 of these floating point constants.
180 @c FIXME! (1) reflect these options (next item too) in option summaries;
181 @c (2) stop teasing, say _which_ instructions expanded _how_.
182 @code{@value{AS}} automatically macro expands certain division and
183 multiplication instructions to check for overflow and division by zero. This
184 option causes @code{@value{AS}} to generate code to take a trap exception
185 rather than a break exception when an error is detected. The trap instructions
186 are only supported at Instruction Set Architecture level 2 and higher.
190 Generate code to take a break exception rather than a trap exception when an
191 error is detected. This is the default.
195 @section MIPS ECOFF object code
197 @cindex ECOFF sections
198 @cindex MIPS ECOFF sections
199 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
200 besides the usual @code{.text}, @code{.data} and @code{.bss}. The
201 additional sections are @code{.rdata}, used for read-only data,
202 @code{.sdata}, used for small data, and @code{.sbss}, used for small
205 @cindex small objects, MIPS ECOFF
206 @cindex @code{gp} register, MIPS
207 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
208 register to form the address of a ``small object''. Any object in the
209 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
210 For external objects, or for objects in the @code{.bss} section, you can use
211 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
212 @code{$gp}; the default value is 8, meaning that a reference to any object
213 eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
214 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
215 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
216 or @code{sbss} in any case). The size of an object in the @code{.bss} section
217 is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
218 size of an external object may be set with the @code{.extern} directive. For
219 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
220 in length, whie leaving @code{sym} otherwise undefined.
222 Using small @sc{ecoff} objects requires linker support, and assumes that the
223 @code{$gp} register is correctly initialized (normally done automatically by
224 the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
228 @section Directives for debugging information
230 @cindex MIPS debugging directives
231 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
232 generating debugging information which are not support by traditional @sc{mips}
233 assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
234 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
235 @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
236 generated by the three @code{.stab} directives can only be read by @sc{gdb},
237 not by traditional @sc{mips} debuggers (this enhancement is required to fully
238 support C++ debugging). These directives are primarily used by compilers, not
239 assembly language programmers!
242 @section Directives to override the ISA level
244 @cindex MIPS ISA override
245 @kindex @code{.set mips@var{n}}
246 @sc{gnu} @code{@value{AS}} supports an additional directive to change
247 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
248 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32 or 64.
249 The values 1 to 5, 32, and 64 make the assembler accept instructions
250 for the corresponding @sc{isa} level, from that point on in the
251 assembly. @code{.set mips@var{n}} affects not only which instructions
252 are permitted, but also how certain macros are expanded. @code{.set
253 mips0} restores the @sc{isa} level to its original level: either the
254 level you selected with command line options, or the default for your
255 configuration. You can use this feature to permit specific @sc{r4000}
256 instructions while assembling in 32 bit mode. Use this directive with
259 The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
260 in which it will assemble instructions for the MIPS 16 processor. Use
261 @samp{.set nomips16} to return to normal 32 bit mode.
263 Traditional @sc{mips} assemblers do not support this directive.
265 @node MIPS autoextend
266 @section Directives for extending MIPS 16 bit instructions
268 @kindex @code{.set autoextend}
269 @kindex @code{.set noautoextend}
270 By default, MIPS 16 instructions are automatically extended to 32 bits
271 when necessary. The directive @samp{.set noautoextend} will turn this
272 off. When @samp{.set noautoextend} is in effect, any 32 bit instruction
273 must be explicitly extended with the @samp{.e} modifier (e.g.,
274 @samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used
275 to once again automatically extend instructions when necessary.
277 This directive is only meaningful when in MIPS 16 mode. Traditional
278 @sc{mips} assemblers do not support this directive.
281 @section Directive to mark data as an instruction
284 The @code{.insn} directive tells @code{@value{AS}} that the following
285 data is actually instructions. This makes a difference in MIPS 16 mode:
286 when loading the address of a label which precedes instructions,
287 @code{@value{AS}} automatically adds 1 to the value, so that jumping to
288 the loaded address will do the right thing.
290 @node MIPS option stack
291 @section Directives to save and restore options
293 @cindex MIPS option stack
294 @kindex @code{.set push}
295 @kindex @code{.set pop}
296 The directives @code{.set push} and @code{.set pop} may be used to save
297 and restore the current settings for all the options which are
298 controlled by @code{.set}. The @code{.set push} directive saves the
299 current settings on a stack. The @code{.set pop} directive pops the
300 stack and restores the settings.
302 These directives can be useful inside an macro which must change an
303 option such as the ISA level or instruction reordering but does not want
304 to change the state of the code which invoked the macro.
306 Traditional @sc{mips} assemblers do not support these directives.