1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2013
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
9 @chapter MIPS Dependent Features
12 @node Machine Dependencies
13 @chapter MIPS Dependent Features
16 @cindex MIPS processor
17 @sc{gnu} @code{@value{AS}} for MIPS architectures supports several
18 different MIPS processors, and MIPS ISA levels I through V, MIPS32,
19 and MIPS64. For information about the MIPS instruction set, see
20 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
21 For an overview of MIPS assembly conventions, see ``Appendix D:
22 Assembly Language Programming'' in the same work.
25 * MIPS Options:: Assembler options
26 * MIPS Macros:: High-level assembly macros
27 * MIPS Symbol Sizes:: Directives to override the size of symbols
28 * MIPS Small Data:: Controlling the use of small data accesses
29 * MIPS ISA:: Directives to override the ISA level
30 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
31 * MIPS insn:: Directive to mark data as an instruction
32 * MIPS Option Stack:: Directives to save and restore options
33 * MIPS ASE Instruction Generation Overrides:: Directives to control
34 generation of MIPS ASE instructions
35 * MIPS Floating-Point:: Directives to override floating-point options
36 * MIPS Syntax:: MIPS specific syntactical considerations
40 @section Assembler options
42 The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
46 @cindex @code{-G} option (MIPS)
48 Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes.
49 @xref{MIPS Small Data,, Controlling the use of small data accesses}.
51 @cindex @code{-EB} option (MIPS)
52 @cindex @code{-EL} option (MIPS)
53 @cindex MIPS big-endian output
54 @cindex MIPS little-endian output
55 @cindex big-endian output, MIPS
56 @cindex little-endian output, MIPS
59 Any MIPS configuration of @code{@value{AS}} can select big-endian or
60 little-endian output at run time (unlike the other @sc{gnu} development
61 tools, which must be configured for one or the other). Use @samp{-EB}
62 to select big-endian output, and @samp{-EL} for little-endian.
65 @cindex PIC selection, MIPS
66 @cindex @option{-KPIC} option, MIPS
67 Generate SVR4-style PIC. This option tells the assembler to generate
68 SVR4-style position-independent macro expansions. It also tells the
69 assembler to mark the output file as PIC.
72 @cindex @option{-mvxworks-pic} option, MIPS
73 Generate VxWorks PIC. This option tells the assembler to generate
74 VxWorks-style position-independent macro expansions.
76 @cindex MIPS architecture options
86 Generate code for a particular MIPS Instruction Set Architecture level.
87 @samp{-mips1} corresponds to the R2000 and R3000 processors,
88 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the
89 R4000 processor, and @samp{-mips4} to the R8000 and
90 R10000 processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
91 @samp{-mips64}, and @samp{-mips64r2}
93 @sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
94 and @sc{MIPS64 Release 2}
95 ISA processors, respectively. You can also switch
96 instruction sets during the assembly; see @ref{MIPS ISA, Directives to
97 override the ISA level}.
101 Some macros have different expansions for 32-bit and 64-bit registers.
102 The register sizes are normally inferred from the ISA and ABI, but these
103 flags force a certain group of registers to be treated as 32 bits wide at
104 all times. @samp{-mgp32} controls the size of general-purpose registers
105 and @samp{-mfp32} controls the size of floating-point registers.
107 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
108 of registers to be changed for parts of an object. The default value is
109 restored by @code{.set gp=default} and @code{.set fp=default}.
111 On some MIPS variants there is a 32-bit mode flag; when this flag is
112 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
113 save the 32-bit registers on a context switch, so it is essential never
114 to use the 64-bit registers.
118 Assume that 64-bit registers are available. This is provided in the
119 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
121 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
122 of registers to be changed for parts of an object. The default value is
123 restored by @code{.set gp=default} and @code{.set fp=default}.
127 Generate code for the MIPS 16 processor. This is equivalent to putting
128 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
129 turns off this option.
132 @itemx -mno-micromips
133 Generate code for the microMIPS processor. This is equivalent to putting
134 @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
135 turns off this option. This is equivalent to putting @code{.set nomicromips}
136 at the start of the assembly file.
139 @itemx -mno-smartmips
140 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
141 provides a number of new instructions which target smartcard and
142 cryptographic applications. This is equivalent to putting
143 @code{.set smartmips} at the start of the assembly file.
144 @samp{-mno-smartmips} turns off this option.
148 Generate code for the MIPS-3D Application Specific Extension.
149 This tells the assembler to accept MIPS-3D instructions.
150 @samp{-no-mips3d} turns off this option.
154 Generate code for the MDMX Application Specific Extension.
155 This tells the assembler to accept MDMX instructions.
156 @samp{-no-mdmx} turns off this option.
160 Generate code for the DSP Release 1 Application Specific Extension.
161 This tells the assembler to accept DSP Release 1 instructions.
162 @samp{-mno-dsp} turns off this option.
166 Generate code for the DSP Release 2 Application Specific Extension.
167 This option implies -mdsp.
168 This tells the assembler to accept DSP Release 2 instructions.
169 @samp{-mno-dspr2} turns off this option.
173 Generate code for the MT Application Specific Extension.
174 This tells the assembler to accept MT instructions.
175 @samp{-mno-mt} turns off this option.
179 Generate code for the MCU Application Specific Extension.
180 This tells the assembler to accept MCU instructions.
181 @samp{-mno-mcu} turns off this option.
185 Generate code for the Virtualization Application Specific Extension.
186 This tells the assembler to accept Virtualization instructions.
187 @samp{-mno-virt} turns off this option.
191 Cause nops to be inserted if the read of the destination register
192 of an mfhi or mflo instruction occurs in the following two instructions.
194 @item -mfix-loongson2f-jump
195 @itemx -mno-fix-loongson2f-jump
196 Eliminate instruction fetch from outside 256M region to work around the
197 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
198 the kernel may crash. The issue has been solved in latest processor
199 batches, but this fix has no side effect to them.
201 @item -mfix-loongson2f-nop
202 @itemx -mno-fix-loongson2f-nop
203 Replace nops by @code{or at,at,zero} to work around the Loongson2F
204 @samp{nop} errata. Without it, under extreme cases, the CPU might
205 deadlock. The issue has been solved in later Loongson2F batches, but
206 this fix has no side effect to them.
209 @itemx -mno-fix-vr4120
210 Insert nops to work around certain VR4120 errata. This option is
211 intended to be used on GCC-generated code: it is not designed to catch
212 all problems in hand-written assembler code.
215 @itemx -mno-fix-vr4130
216 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
220 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
223 @itemx -mno-fix-cn63xxp1
224 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
225 certain CN63XXP1 errata.
229 Generate code for the LSI R4010 chip. This tells the assembler to
230 accept the R4010-specific instructions (@samp{addciu}, @samp{ffc},
231 etc.), and to not schedule @samp{nop} instructions around accesses to
232 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
237 Generate code for the MIPS R4650 chip. This tells the assembler to accept
238 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
239 instructions around accesses to the @samp{HI} and @samp{LO} registers.
240 @samp{-no-m4650} turns off this option.
246 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
247 R@var{nnnn} chip. This tells the assembler to accept instructions
248 specific to that chip, and to schedule for that chip's hazards.
250 @item -march=@var{cpu}
251 Generate code for a particular MIPS CPU. It is exactly equivalent to
252 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
253 understood. Valid @var{cpu} value are:
338 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
339 accepted as synonyms for @samp{@var{n}f1_1}. These values are
342 @item -mtune=@var{cpu}
343 Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are
344 identical to @samp{-march=@var{cpu}}.
346 @item -mabi=@var{abi}
347 Record which ABI the source code uses. The recognized arguments
348 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
354 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
355 the beginning of the assembler input. @xref{MIPS Symbol Sizes}.
357 @cindex @code{-nocpp} ignored (MIPS)
359 This option is ignored. It is accepted for command-line compatibility with
360 other assemblers, which use it to turn off C style preprocessing. With
361 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
362 @sc{gnu} assembler itself never runs the C preprocessor.
366 Disable or enable floating-point instructions. Note that by default
367 floating-point instructions are always allowed even with CPU targets
368 that don't have support for these instructions.
371 @itemx -mdouble-float
372 Disable or enable double-precision floating-point operations. Note
373 that by default double-precision floating-point operations are always
374 allowed even with CPU targets that don't have support for these
377 @item --construct-floats
378 @itemx --no-construct-floats
379 The @code{--no-construct-floats} option disables the construction of
380 double width floating point constants by loading the two halves of the
381 value into the two single width floating point registers that make up
382 the double width register. This feature is useful if the processor
383 support the FR bit in its status register, and this bit is known (by
384 the programmer) to be set. This bit prevents the aliasing of the double
385 width register by the single width registers.
387 By default @code{--construct-floats} is selected, allowing construction
388 of these floating point constants.
391 @itemx --no-relax-branch
392 The @samp{--relax-branch} option enables the relaxation of out-of-range
393 branches. Any branches whose target cannot be reached directly are
394 converted to a small instruction sequence including an inverse-condition
395 branch to the physically next instruction, and a jump to the original
396 target is inserted between the two instructions. In PIC code the jump
397 will involve further instructions for address calculation.
399 The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
400 @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
401 relaxation, because they have no complementing counterparts. They could
402 be relaxed with the use of a longer sequence involving another branch,
403 however this has not been implemented and if their target turns out of
404 reach, they produce an error even if branch relaxation is enabled.
406 Also no @sc{mips16} branches are ever relaxed.
408 By default @samp{--no-relax-branch} is selected, causing any out-of-range
409 branches to produce an error.
413 @c FIXME! (1) reflect these options (next item too) in option summaries;
414 @c (2) stop teasing, say _which_ instructions expanded _how_.
415 @code{@value{AS}} automatically macro expands certain division and
416 multiplication instructions to check for overflow and division by zero. This
417 option causes @code{@value{AS}} to generate code to take a trap exception
418 rather than a break exception when an error is detected. The trap instructions
419 are only supported at Instruction Set Architecture level 2 and higher.
423 Generate code to take a break exception rather than a trap exception when an
424 error is detected. This is the default.
428 Control generation of @code{.pdr} sections. Off by default on IRIX, on
433 When generating code using the Unix calling conventions (selected by
434 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
435 which can go into a shared library. The @samp{-mno-shared} option
436 tells gas to generate code which uses the calling convention, but can
437 not go into a shared library. The resulting code is slightly more
438 efficient. This option only affects the handling of the
439 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
443 @section High-level assembly macros
445 MIPS assemblers have traditionally provided a wider range of
446 instructions than the MIPS architecture itself. These extra
447 instructions are usually referred to as ``macro'' instructions
448 @footnote{The term ``macro'' is somewhat overloaded here, since
449 these macros have no relation to those defined by @code{.macro},
450 @pxref{Macro,, @code{.macro}}.}.
452 Some MIPS macro instructions extend an underlying architectural instruction
453 while others are entirely new. An example of the former type is @code{and},
454 which allows the third operand to be either a register or an arbitrary
455 immediate value. Examples of the latter type include @code{bgt}, which
456 branches to the third operand when the first operand is greater than
457 the second operand, and @code{ulh}, which implements an unaligned
460 One of the most common extensions provided by macros is to expand
461 memory offsets to the full address range (32 or 64 bits) and to allow
462 symbolic offsets such as @samp{my_data + 4} to be used in place of
463 integer constants. For example, the architectural instruction
464 @code{lbu} allows only a signed 16-bit offset, whereas the macro
465 @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}.
466 The implementation of these symbolic offsets depends on several factors,
467 such as whether the assembler is generating SVR4-style PIC (selected by
468 @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols
469 (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}),
470 and the small data limit (@pxref{MIPS Small Data,, Controlling the use
471 of small data accesses}).
473 @kindex @code{.set macro}
474 @kindex @code{.set nomacro}
475 Sometimes it is undesirable to have one assembly instruction expand
476 to several machine instructions. The directive @code{.set nomacro}
477 tells the assembler to warn when this happens. @code{.set macro}
478 restores the default behavior.
480 @cindex @code{at} register, MIPS
481 @kindex @code{.set at=@var{reg}}
482 Some macro instructions need a temporary register to store intermediate
483 results. This register is usually @code{$1}, also known as @code{$at},
484 but it can be changed to any core register @var{reg} using
485 @code{.set at=@var{reg}}. Note that @code{$at} always refers
486 to @code{$1} regardless of which register is being used as the
489 @kindex @code{.set at}
490 @kindex @code{.set noat}
491 Implicit uses of the temporary register in macros could interfere with
492 explicit uses in the assembly code. The assembler therefore warns
493 whenever it sees an explicit use of the temporary register. The directive
494 @code{.set noat} silences this warning while @code{.set at} restores
495 the default behavior. It is safe to use @code{.set noat} while
496 @code{.set nomacro} is in effect since single-instruction macros
497 never need a temporary register.
499 Note that while the @sc{gnu} assembler provides these macros for compatibility,
500 it does not make any attempt to optimize them with the surrounding code.
502 @node MIPS Symbol Sizes
503 @section Directives to override the size of symbols
505 @kindex @code{.set sym32}
506 @kindex @code{.set nosym32}
507 The n64 ABI allows symbols to have any 64-bit value. Although this
508 provides a great deal of flexibility, it means that some macros have
509 much longer expansions than their 32-bit counterparts. For example,
510 the non-PIC expansion of @samp{dla $4,sym} is usually:
515 daddiu $4,$4,%higher(sym)
516 daddiu $1,$1,%lo(sym)
521 whereas the 32-bit expansion is simply:
525 daddiu $4,$4,%lo(sym)
528 n64 code is sometimes constructed in such a way that all symbolic
529 constants are known to have 32-bit values, and in such cases, it's
530 preferable to use the 32-bit expansion instead of the 64-bit
533 You can use the @code{.set sym32} directive to tell the assembler
534 that, from this point on, all expressions of the form
535 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
536 have 32-bit values. For example:
545 will cause the assembler to treat @samp{sym}, @code{sym+16} and
546 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
547 addresses is not affected.
549 The directive @code{.set nosym32} ends a @code{.set sym32} block and
550 reverts to the normal behavior. It is also possible to change the
551 symbol size using the command-line options @option{-msym32} and
554 These options and directives are always accepted, but at present,
555 they have no effect for anything other than n64.
557 @node MIPS Small Data
558 @section Controlling the use of small data accesses
560 @c This section deliberately glosses over the possibility of using -G
561 @c in SVR4-style PIC, as could be done on IRIX. We don't support that.
562 @cindex small data, MIPS
563 @cindex @code{gp} register, MIPS
564 It often takes several instructions to load the address of a symbol.
565 For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion
566 of @samp{dla $4,addr} is usually:
570 daddiu $4,$4,%lo(addr)
573 The sequence is much longer when @samp{addr} is a 64-bit symbol.
574 @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}.
576 In order to cut down on this overhead, most embedded MIPS systems
577 set aside a 64-kilobyte ``small data'' area and guarantee that all
578 data of size @var{n} and smaller will be placed in that area.
579 The limit @var{n} is passed to both the assembler and the linker
580 using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,,
581 Assembler options}. Note that the same value of @var{n} must be used
582 when linking and when assembling all input files to the link; any
583 inconsistency could cause a relocation overflow error.
585 The size of an object in the @code{.bss} section is set by the
586 @code{.comm} or @code{.lcomm} directive that defines it. The size of
587 an external object may be set with the @code{.extern} directive. For
588 example, @samp{.extern sym,4} declares that the object at @code{sym}
589 is 4 bytes in length, while leaving @code{sym} otherwise undefined.
591 When no @option{-G} option is given, the default limit is 8 bytes.
592 The option @option{-G 0} prevents any data from being automatically
595 It is also possible to mark specific objects as small by putting them
596 in the special sections @code{.sdata} and @code{.sbss}, which are
597 ``small'' counterparts of @code{.data} and @code{.bss} respectively.
598 The toolchain will treat such data as small regardless of the
601 On startup, systems that support a small data area are expected to
602 initialize register @code{$28}, also known as @code{$gp}, in such a
603 way that small data can be accessed using a 16-bit offset from that
604 register. For example, when @samp{addr} is small data,
605 the @samp{dla $4,addr} instruction above is equivalent to:
608 daddiu $4,$28,%gp_rel(addr)
611 Small data is not supported for SVR4-style PIC.
614 @section Directives to override the ISA level
616 @cindex MIPS ISA override
617 @kindex @code{.set mips@var{n}}
618 @sc{gnu} @code{@value{AS}} supports an additional directive to change
619 the MIPS Instruction Set Architecture level on the fly: @code{.set
620 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
622 The values other than 0 make the assembler accept instructions
623 for the corresponding @sc{isa} level, from that point on in the
624 assembly. @code{.set mips@var{n}} affects not only which instructions
625 are permitted, but also how certain macros are expanded. @code{.set
626 mips0} restores the @sc{isa} level to its original level: either the
627 level you selected with command line options, or the default for your
628 configuration. You can use this feature to permit specific @sc{mips3}
629 instructions while assembling in 32 bit mode. Use this directive with
632 @cindex MIPS CPU override
633 @kindex @code{.set arch=@var{cpu}}
634 The @code{.set arch=@var{cpu}} directive provides even finer control.
635 It changes the effective CPU target and allows the assembler to use
636 instructions specific to a particular CPU. All CPUs supported by the
637 @samp{-march} command line option are also selectable by this directive.
638 The original value is restored by @code{.set arch=default}.
640 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
641 in which it will assemble instructions for the MIPS 16 processor. Use
642 @code{.set nomips16} to return to normal 32 bit mode.
644 Traditional MIPS assemblers do not support this directive.
646 The directive @code{.set micromips} puts the assembler into microMIPS mode,
647 in which it will assemble instructions for the microMIPS processor. Use
648 @code{.set nomicromips} to return to normal 32 bit mode.
650 Traditional MIPS assemblers do not support this directive.
652 @node MIPS autoextend
653 @section Directives for extending MIPS 16 bit instructions
655 @kindex @code{.set autoextend}
656 @kindex @code{.set noautoextend}
657 By default, MIPS 16 instructions are automatically extended to 32 bits
658 when necessary. The directive @code{.set noautoextend} will turn this
659 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
660 must be explicitly extended with the @code{.e} modifier (e.g.,
661 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
662 to once again automatically extend instructions when necessary.
664 This directive is only meaningful when in MIPS 16 mode. Traditional
665 MIPS assemblers do not support this directive.
668 @section Directive to mark data as an instruction
671 The @code{.insn} directive tells @code{@value{AS}} that the following
672 data is actually instructions. This makes a difference in MIPS 16 and
673 microMIPS modes: when loading the address of a label which precedes
674 instructions, @code{@value{AS}} automatically adds 1 to the value, so
675 that jumping to the loaded address will do the right thing.
677 @kindex @code{.global}
678 The @code{.global} and @code{.globl} directives supported by
679 @code{@value{AS}} will by default mark the symbol as pointing to a
680 region of data not code. This means that, for example, any
681 instructions following such a symbol will not be disassembled by
682 @code{objdump} as it will regard them as data. To change this
683 behaviour an optional section name can be placed after the symbol name
684 in the @code{.global} directive. If this section exists and is known
685 to be a code section, then the symbol will be marked as poiting at
686 code not data. Ie the syntax for the directive is:
688 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
690 Here is a short example:
693 .global foo .text, bar, baz .data
703 @node MIPS Option Stack
704 @section Directives to save and restore options
706 @cindex MIPS option stack
707 @kindex @code{.set push}
708 @kindex @code{.set pop}
709 The directives @code{.set push} and @code{.set pop} may be used to save
710 and restore the current settings for all the options which are
711 controlled by @code{.set}. The @code{.set push} directive saves the
712 current settings on a stack. The @code{.set pop} directive pops the
713 stack and restores the settings.
715 These directives can be useful inside an macro which must change an
716 option such as the ISA level or instruction reordering but does not want
717 to change the state of the code which invoked the macro.
719 Traditional MIPS assemblers do not support these directives.
721 @node MIPS ASE Instruction Generation Overrides
722 @section Directives to control generation of MIPS ASE instructions
724 @cindex MIPS MIPS-3D instruction generation override
725 @kindex @code{.set mips3d}
726 @kindex @code{.set nomips3d}
727 The directive @code{.set mips3d} makes the assembler accept instructions
728 from the MIPS-3D Application Specific Extension from that point on
729 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
730 instructions from being accepted.
732 @cindex SmartMIPS instruction generation override
733 @kindex @code{.set smartmips}
734 @kindex @code{.set nosmartmips}
735 The directive @code{.set smartmips} makes the assembler accept
736 instructions from the SmartMIPS Application Specific Extension to the
737 MIPS32 @sc{isa} from that point on in the assembly. The
738 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
741 @cindex MIPS MDMX instruction generation override
742 @kindex @code{.set mdmx}
743 @kindex @code{.set nomdmx}
744 The directive @code{.set mdmx} makes the assembler accept instructions
745 from the MDMX Application Specific Extension from that point on
746 in the assembly. The @code{.set nomdmx} directive prevents MDMX
747 instructions from being accepted.
749 @cindex MIPS DSP Release 1 instruction generation override
750 @kindex @code{.set dsp}
751 @kindex @code{.set nodsp}
752 The directive @code{.set dsp} makes the assembler accept instructions
753 from the DSP Release 1 Application Specific Extension from that point
754 on in the assembly. The @code{.set nodsp} directive prevents DSP
755 Release 1 instructions from being accepted.
757 @cindex MIPS DSP Release 2 instruction generation override
758 @kindex @code{.set dspr2}
759 @kindex @code{.set nodspr2}
760 The directive @code{.set dspr2} makes the assembler accept instructions
761 from the DSP Release 2 Application Specific Extension from that point
762 on in the assembly. This dirctive implies @code{.set dsp}. The
763 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
766 @cindex MIPS MT instruction generation override
767 @kindex @code{.set mt}
768 @kindex @code{.set nomt}
769 The directive @code{.set mt} makes the assembler accept instructions
770 from the MT Application Specific Extension from that point on
771 in the assembly. The @code{.set nomt} directive prevents MT
772 instructions from being accepted.
774 @cindex MIPS MCU instruction generation override
775 @kindex @code{.set mcu}
776 @kindex @code{.set nomcu}
777 The directive @code{.set mcu} makes the assembler accept instructions
778 from the MCU Application Specific Extension from that point on
779 in the assembly. The @code{.set nomcu} directive prevents MCU
780 instructions from being accepted.
782 @cindex Virtualization instruction generation override
783 @kindex @code{.set virt}
784 @kindex @code{.set novirt}
785 The directive @code{.set virt} makes the assembler accept instructions
786 from the Virtualization Application Specific Extension from that point
787 on in the assembly. The @code{.set novirt} directive prevents Virtualization
788 instructions from being accepted.
790 Traditional MIPS assemblers do not support these directives.
792 @node MIPS Floating-Point
793 @section Directives to override floating-point options
795 @cindex Disable floating-point instructions
796 @kindex @code{.set softfloat}
797 @kindex @code{.set hardfloat}
798 The directives @code{.set softfloat} and @code{.set hardfloat} provide
799 finer control of disabling and enabling float-point instructions.
800 These directives always override the default (that hard-float
801 instructions are accepted) or the command-line options
802 (@samp{-msoft-float} and @samp{-mhard-float}).
804 @cindex Disable single-precision floating-point operations
805 @kindex @code{.set singlefloat}
806 @kindex @code{.set doublefloat}
807 The directives @code{.set singlefloat} and @code{.set doublefloat}
808 provide finer control of disabling and enabling double-precision
809 float-point operations. These directives always override the default
810 (that double-precision operations are accepted) or the command-line
811 options (@samp{-msingle-float} and @samp{-mdouble-float}).
813 Traditional MIPS assemblers do not support these directives.
816 @section Syntactical considerations for the MIPS assembler
818 * MIPS-Chars:: Special Characters
822 @subsection Special Characters
824 @cindex line comment character, MIPS
825 @cindex MIPS line comment character
826 The presence of a @samp{#} on a line indicates the start of a comment
827 that extends to the end of the current line.
829 If a @samp{#} appears as the first character of a line, the whole line
830 is treated as a comment, but in this case the line can also be a
831 logical line number directive (@pxref{Comments}) or a
832 preprocessor control command (@pxref{Preprocessing}).
834 @cindex line separator, MIPS
835 @cindex statement separator, MIPS
836 @cindex MIPS line separator
837 The @samp{;} character can be used to separate statements on the same