1 @c Copyright (C) 2016-2020 Free Software Foundation, Inc.
2 @c This is part of the GAS anual.
3 @c For copying conditions, see the file as.texinfo
9 @chapter RISC-V Dependent Features
12 @node Machine Dependencies
13 @chapter RISC-V Dependent Features
16 @cindex RISC-V support
18 * RISC-V-Options:: RISC-V Options
19 * RISC-V-Directives:: RISC-V Directives
20 * RISC-V-Modifiers:: RISC-V Assembler Modifiers
21 * RISC-V-Formats:: RISC-V Instruction Formats
22 * RISC-V-ATTRIBUTE:: RISC-V Object Attribute
26 @section RISC-V Options
28 The following table lists all available RISC-V specific options.
33 @cindex @samp{-fpic} option, RISC-V
36 Generate position-independent code
38 @cindex @samp{-fno-pic} option, RISC-V
40 Don't generate position-independent code (default)
42 @cindex @samp{-march=ISA} option, RISC-V
44 Select the base isa, as specified by ISA. For example -march=rv32ima.
46 @cindex @samp{-mabi=ABI} option, RISC-V
48 Selects the ABI, which is either "ilp32" or "lp64", optionally followed
49 by "f", "d", or "q" to indicate single-precision, double-precision, or
50 quad-precision floating-point calling convention, or none to indicate
51 the soft-float calling convention. Also, "ilp32" can optionally be followed
52 by "e" to indicate the RVE ABI, which is always soft-float.
54 @cindex @samp{-mrelax} option, RISC-V
56 Take advantage of linker relaxations to reduce the number of instructions
57 required to materialize symbol addresses. (default)
59 @cindex @samp{-mno-relax} option, RISC-V
61 Don't do linker relaxations.
63 @cindex @samp{-march-attr} option, RISC-V
65 Generate the default contents for the riscv elf attribute section if the
66 .attribute directives are not set. This section is used to record the
67 information that a linker or runtime loader needs to check compatibility.
68 This information includes ISA string, stack alignment requirement, unaligned
69 memory accesses, and the major, minor and revision version of privileged
72 @cindex @samp{-mno-arch-attr} option, RISC-V
74 Don't generate the default riscv elf attribute section if the .attribute
75 directives are not set.
77 @cindex @samp{-mcsr-check} option, RISC-V
79 Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
80 The ISA-dependent CSR are only valid when the specific ISA is set. The
81 read-only CSR can not be written by the CSR instructions.
83 @cindex @samp{-mno-csr-check} option, RISC-V
85 Don't do CSR cheching.
89 @node RISC-V-Directives
90 @section RISC-V Directives
91 @cindex machine directives, RISC-V
92 @cindex RISC-V machine directives
94 The following table lists all available RISC-V specific directives.
98 @cindex @code{align} directive
99 @item .align @var{size-log-2}
100 Align to the given boundary, with the size given as log2 the number of bytes to
103 @cindex Data directives
104 @item .half @var{value}
105 @itemx .word @var{value}
106 @itemx .dword @var{value}
107 Emits a half-word, word, or double-word value at the current position.
109 @cindex DTP-relative data directives
110 @item .dtprelword @var{value}
111 @itemx .dtpreldword @var{value}
112 Emits a DTP-relative word (or double-word) at the current position. This is
113 meant to be used by the compiler in shared libraries for DWARF debug info for
114 thread local variables.
116 @cindex BSS directive
118 Sets the current section to the BSS section.
120 @cindex LEB128 directives
121 @item .uleb128 @var{value}
122 @itemx .sleb128 @var{value}
123 Emits a signed or unsigned LEB128 value at the current position. This only
124 accepts constant expressions, because symbol addresses can change with
125 relaxation, and we don't support relocations to modify LEB128 values at link
128 @cindex Option directive
129 @cindex @code{option} directive
130 @item .option @var{argument}
131 Modifies RISC-V specific assembler options inline with the assembly code.
132 This is used when particular instruction sequences must be assembled with a
133 specific set of options. For example, since we relax addressing sequences to
134 shorter GP-relative sequences when possible the initial load of GP must not be
135 relaxed and should be emitted as something like
140 la gp, __global_pointer$
144 in order to produce after linker relaxation the expected
147 auipc gp, %pcrel_hi(__global_pointer$)
148 addi gp, gp, %pcrel_lo(__global_pointer$)
157 It's not expected that options are changed in this manner during regular use,
158 but there are a handful of esoteric cases like the one above where users need
159 to disable particular features of the assembler for particular code sequences.
160 The complete list of option arguments is shown below:
165 Pushes or pops the current option stack. These should be used whenever
166 changing an option in line with assembly code in order to ensure the user's
167 command-line options are respected for the bulk of the file being assembled.
171 Enables or disables the generation of compressed instructions. Instructions
172 are opportunistically compressed by the RISC-V assembler when possible, but
173 sometimes this behavior is not desirable.
177 Enables or disables position-independent code generation. Unless you really
178 know what you're doing, this should only be at the top of a file.
182 Enables or disables relaxation. The RISC-V assembler and linker
183 opportunistically relax some code sequences, but sometimes this behavior is not
189 Enables or disables the CSR checking.
191 @cindex INSN directives
192 @item .insn @var{value}
193 @itemx .insn @var{value}
194 This directive permits the numeric representation of an instructions
195 and makes the assembler insert the operands according to one of the
196 instruction formats for @samp{.insn} (@ref{RISC-V-Formats}).
197 For example, the instruction @samp{add a0, a1, a2} could be written as
198 @samp{.insn r 0x33, 0, 0, a0, a1, a2}.
200 @cindex @code{.attribute} directive, RISC-V
201 @item .attribute @var{tag}, @var{value}
202 Set the object attribute @var{tag} to @var{value}.
204 The @var{tag} is either an attribute number, or one of the following:
205 @code{Tag_RISCV_arch}, @code{Tag_RISCV_stack_align},
206 @code{Tag_RISCV_unaligned_access}, @code{Tag_RISCV_priv_spec},
207 @code{Tag_RISCV_priv_spec_minor}, @code{Tag_RISCV_priv_spec_revision}.
211 @node RISC-V-Modifiers
212 @section RISC-V Assembler Modifiers
214 The RISC-V assembler supports following modifiers for relocatable addresses
215 used in RISC-V instruction operands. However, we also support some pseudo
216 instructions that are easier to use than these modifiers.
219 @item %lo(@var{symbol})
220 The low 12 bits of absolute address for @var{symbol}.
222 @item %hi(@var{symbol})
223 The high 20 bits of absolute address for @var{symbol}. This is usually
224 used with the %lo modifier to represent a 32-bit absolute address.
227 lui a0, %hi(@var{symbol}) // R_RISCV_HI20
228 addi a0, a0, %lo(@var{symbol}) // R_RISCV_LO12_I
230 lui a0, %hi(@var{symbol}) // R_RISCV_HI20
231 load/store a0, %lo(@var{symbol})(a0) // R_RISCV_LO12_I/S
234 @item %pcrel_lo(@var{label})
235 The low 12 bits of relative address between pc and @var{symbol}.
236 The @var{symbol} is related to the high part instruction which is marked
239 @item %pcrel_hi(@var{symbol})
240 The high 20 bits of relative address between pc and @var{symbol}.
241 This is usually used with the %pcrel_lo modifier to represent a +/-2GB
246 auipc a0, %pcrel_hi(@var{symbol}) // R_RISCV_PCREL_HI20
247 addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I
250 auipc a0, %pcrel_hi(@var{symbol}) // R_RISCV_PCREL_HI20
251 load/store a0, %pcrel_lo(@var{label})(a0) // R_RISCV_PCREL_LO12_I/S
254 Or you can use the pseudo lla/lw/sw/... instruction to do this.
260 @item %tprel_add(@var{symbol})
261 This is used purely to associate the R_RISCV_TPREL_ADD relocation for
262 TLS relaxation. This one is only valid as the fourth operand to the normally
263 3 operand add instruction.
265 @item %tprel_lo(@var{symbol})
266 The low 12 bits of relative address between tp and @var{symbol}.
268 @item %tprel_hi(@var{symbol})
269 The high 20 bits of relative address between tp and @var{symbol}. This is
270 usually used with the %tprel_lo and %tprel_add modifiers to access the thread
271 local variable @var{symbol} in TLS Local Exec.
274 lui a5, %tprel_hi(@var{symbol}) // R_RISCV_TPREL_HI20
275 add a5, a5, tp, %tprel_add(@var{symbol}) // R_RISCV_TPREL_ADD
276 load/store t0, %tprel_lo(@var{symbol})(a5) // R_RISCV_TPREL_LO12_I/S
279 @item %tls_ie_pcrel_hi(@var{symbol})
280 The high 20 bits of relative address between pc and GOT entry. It is
281 usually used with the %pcrel_lo modifier to access the thread local
282 variable @var{symbol} in TLS Initial Exec.
285 la.tls.ie a5, @var{symbol}
290 The pseudo la.tls.ie instruction can be expended to
294 auipc a5, %tls_ie_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GOT_HI20
295 load a5, %pcrel_lo(@var{label})(a5) // R_RISCV_PCREL_LO12_I
298 @item %tls_gd_pcrel_hi(@var{symbol})
299 The high 20 bits of relative address between pc and GOT entry. It is
300 usually used with the %pcrel_lo modifier to access the thread local variable
301 @var{symbol} in TLS Global Dynamic.
304 la.tls.gd a0, @var{symbol}
305 call __tls_get_addr@@plt
310 The pseudo la.tls.gd instruction can be expended to
314 auipc a0, %tls_gd_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GD_HI20
315 addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I
321 @section RISC-V Instruction Formats
322 @cindex instruction formats, risc-v
323 @cindex RISC-V instruction formats
325 The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 12
326 instruction formats where some of the formats have multiple variants.
327 For the @samp{.insn} pseudo directive the assembler recognizes some
329 Typically, the most general variant of the instruction format is used
330 by the @samp{.insn} directive.
332 The following table lists the abbreviations used in the table of
336 @multitable @columnfractions .15 .40
337 @item opcode @tab Unsigned immediate or opcode name for 7-bits opcode.
338 @item opcode2 @tab Unsigned immediate or opcode name for 2-bits opcode.
339 @item func7 @tab Unsigned immediate for 7-bits function code.
340 @item func6 @tab Unsigned immediate for 6-bits function code.
341 @item func4 @tab Unsigned immediate for 4-bits function code.
342 @item func3 @tab Unsigned immediate for 3-bits function code.
343 @item func2 @tab Unsigned immediate for 2-bits function code.
344 @item rd @tab Destination register number for operand x, can be GPR or FPR.
345 @item rd' @tab Destination register number for operand x,
346 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
347 @item rs1 @tab First source register number for operand x, can be GPR or FPR.
348 @item rs1' @tab First source register number for operand x,
349 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
350 @item rs2 @tab Second source register number for operand x, can be GPR or FPR.
351 @item rs2' @tab Second source register number for operand x,
352 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
353 @item simm12 @tab Sign-extended 12-bit immediate for operand x.
354 @item simm20 @tab Sign-extended 20-bit immediate for operand x.
355 @item simm6 @tab Sign-extended 6-bit immediate for operand x.
356 @item uimm8 @tab Unsigned 8-bit immediate for operand x.
357 @item symbol @tab Symbol or lable reference for operand x.
361 The following table lists all available opcode name:
367 Opcode space for compressed instructions.
370 Opcode space for load instructions.
373 Opcode space for floating-point load instructions.
376 Opcode space for store instructions.
379 Opcode space for floating-point store instructions.
382 Opcode space for auipc instruction.
385 Opcode space for lui instruction.
388 Opcode space for branch instructions.
391 Opcode space for jal instruction.
394 Opcode space for jalr instruction.
397 Opcode space for ALU instructions.
400 Opcode space for 32-bits ALU instructions.
403 Opcode space for ALU with immediate instructions.
406 Opcode space for 32-bits ALU with immediate instructions.
409 Opcode space for floating-point operation instructions.
412 Opcode space for madd instruction.
415 Opcode space for msub instruction.
418 Opcode space for nmadd instruction.
421 Opcode space for msub instruction.
424 Opcode space for atomic memory operation instructions.
427 Opcode space for misc instructions.
430 Opcode space for system instructions.
436 Opcode space for customize instructions.
440 An instruction is two or four bytes in length and must be aligned
441 on a 2 byte boundary. The first two bits of the instruction specify the
442 length of the instruction, 00, 01 and 10 indicates a two byte instruction,
443 11 indicates a four byte instruction.
445 The following table lists the RISC-V instruction formats that are available
446 with the @samp{.insn} pseudo directive:
449 @item R type: .insn r opcode, func3, func7, rd, rs1, rs2
451 +-------+-----+-----+-------+----+-------------+
452 | func7 | rs2 | rs1 | func3 | rd | opcode |
453 +-------+-----+-----+-------+----+-------------+
457 @item R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3
458 @itemx R4 type: .insn r4 opcode, func3, func2, rd, rs1, rs2, rs3
460 +-----+-------+-----+-----+-------+----+-------------+
461 | rs3 | func2 | rs2 | rs1 | func3 | rd | opcode |
462 +-----+-------+-----+-----+-------+----+-------------+
463 31 27 25 20 15 12 7 0
466 @item I type: .insn i opcode, func3, rd, rs1, simm12
468 +-------------+-----+-------+----+-------------+
469 | simm12 | rs1 | func3 | rd | opcode |
470 +-------------+-----+-------+----+-------------+
474 @item S type: .insn s opcode, func3, rd, rs1, simm12
476 +--------------+-----+-----+-------+-------------+-------------+
477 | simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode |
478 +--------------+-----+-----+-------+-------------+-------------+
482 @item SB type: .insn sb opcode, func3, rd, rs1, symbol
483 @itemx SB type: .insn sb opcode, func3, rd, simm12(rs1)
484 @itemx B type: .insn s opcode, func3, rd, rs1, symbol
485 @itemx B type: .insn s opcode, func3, rd, simm12(rs1)
487 +------------+--------------+-----+-----+-------+-------------+-------------+--------+
488 | simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode |
489 +------------+--------------+-----+-----+-------+-------------+-------------+--------+
490 31 30 25 20 15 12 7 0
493 @item U type: .insn u opcode, rd, simm20
495 +---------------------------+----+-------------+
496 | simm20 | rd | opcode |
497 +---------------------------+----+-------------+
501 @item UJ type: .insn uj opcode, rd, symbol
502 @itemx J type: .insn j opcode, rd, symbol
504 +------------+--------------+------------+---------------+----+-------------+
505 | simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode |
506 +------------+--------------+------------+---------------+----+-------------+
510 @item CR type: .insn cr opcode2, func4, rd, rs2
512 +---------+--------+-----+---------+
513 | func4 | rd/rs1 | rs2 | opcode2 |
514 +---------+--------+-----+---------+
518 @item CI type: .insn ci opcode2, func3, rd, simm6
520 +---------+-----+--------+-----+---------+
521 | func3 | imm | rd/rs1 | imm | opcode2 |
522 +---------+-----+--------+-----+---------+
526 @item CIW type: .insn ciw opcode2, func3, rd, uimm8
528 +---------+--------------+-----+---------+
529 | func3 | imm | rd' | opcode2 |
530 +---------+--------------+-----+---------+
534 @item CA type: .insn ca opcode2, func6, func2, rd, rs2
536 +---------+----------+-------+------+--------+
537 | func6 | rd'/rs1' | func2 | rs2' | opcode |
538 +---------+----------+-------+------+--------+
542 @item CB type: .insn cb opcode2, func3, rs1, symbol
544 +---------+--------+------+--------+---------+
545 | func3 | offset | rs1' | offset | opcode2 |
546 +---------+--------+------+--------+---------+
550 @item CJ type: .insn cj opcode2, symbol
552 +---------+--------------------+---------+
553 | func3 | jump target | opcode2 |
554 +---------+--------------------+---------+
561 For the complete list of all instruction format variants see
562 The RISC-V Instruction Set Manual Volume I: User-Level ISA.
564 @node RISC-V-ATTRIBUTE
565 @section RISC-V Object Attribute
566 @cindex Object Attribute, RISC-V
568 RISC-V attributes have a string value if the tag number is odd and an integer
569 value if the tag number is even.
572 @item Tag_RISCV_stack_align (4)
573 Tag_RISCV_strict_align records the N-byte stack alignment for this object. The
574 default value is 16 for RV32I or RV64I, and 4 for RV32E.
576 The smallest value will be used if object files with different
577 Tag_RISCV_stack_align values are merged.
579 @item Tag_RISCV_arch (5)
580 Tag_RISCV_arch contains a string for the target architecture taken from the
581 option @option{-march}. Different architectures will be integrated into a
582 superset when object files are merged.
584 Note that the version information of the target architecture must be presented
585 explicitly in the attribute and abbreviations must be expanded. The version
586 information, if not given by @option{-march}, must be in accordance with the
587 default specified by the tool. For example, the architecture @code{RV32I} has
588 to be recorded in the attribute as @code{RV32I2P0} in which @code{2P0} stands
589 for the default version of its base ISA. On the other hand, the architecture
590 @code{RV32G} has to be presented as @code{RV32I2P0_M2P0_A2P0_F2P0_D2P0} in
591 which the abbreviation @code{G} is expanded to the @code{IMAFD} combination
592 with default versions of the standard extensions.
594 @item Tag_RISCV_unaligned_access (6)
595 Tag_RISCV_unaligned_access is 0 for files that do not allow any unaligned
596 memory accesses, and 1 for files that do allow unaligned memory accesses.
598 @item Tag_RISCV_priv_spec (8)
599 @item Tag_RISCV_priv_spec_minor (10)
600 @item Tag_RISCV_priv_spec_revision (12)
601 Tag_RISCV_priv_spec contains the major/minor/revision version information of
602 the privileged specification. It will report errors if object files of
603 different privileged specification versions are merged.