2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
8 @chapter IBM S/390 Dependent Features
11 @node Machine Dependencies
12 @chapter IBM S/390 Dependent Features
17 The s390 version of @code{@value{AS}} supports two architectures modes
18 and seven chip levels. The architecture modes are the Enterprise System
19 Architecture (ESA) and the newer z/Architecture mode. The chip levels
20 are g5, g6, z900, z990, z9-109, z9-ec, z10 and z196.
23 * s390 Options:: Command-line Options.
24 * s390 Characters:: Special Characters.
25 * s390 Syntax:: Assembler Instruction syntax.
26 * s390 Directives:: Assembler Directives.
27 * s390 Floating Point:: Floating Point.
32 @cindex options for s390
35 The following table lists all available s390 specific options:
38 @cindex @samp{-m31} option, s390
39 @cindex @samp{-m64} option, s390
41 Select 31- or 64-bit ABI implying a word size of 32- or 64-bit.
43 These options are only available with the ELF object file format, and
44 require that the necessary BFD support has been included (on a 31-bit
45 platform you must add --enable-64-bit-bfd on the call to the configure
46 script to enable 64-bit usage and use s390x as target platform).
48 @cindex @samp{-mesa} option, s390
49 @cindex @samp{-mzarch} option, s390
51 Select the architecture mode, either the Enterprise System Architecture
52 (esa) mode or the z/Architecture mode (zarch).
54 The 64-bit instructions are only available with the z/Architecture mode.
55 The combination of @samp{-m64} and @samp{-mesa} results in a warning
58 @cindex @samp{-march=} option, s390
59 @item -march=@var{CPU}
60 This option specifies the target processor. The following processor names
70 Assembling an instruction that is not supported on the target processor
71 results in an error message. Do not specify @code{g5} or @code{g6}
74 @cindex @samp{-mregnames} option, s390
76 Allow symbolic names for registers.
78 @cindex @samp{-mno-regnames} option, s390
80 Do not allow symbolic names for registers.
82 @cindex @samp{-mwarn-areg-zero} option, s390
83 @item -mwarn-areg-zero
84 Warn whenever the operand for a base or index register has been specified
85 but evaluates to zero. This can indicate the misuse of general purpose
86 register 0 as an address register.
91 @section Special Characters
92 @cindex line comment character, s390
93 @cindex s390 line comment character
95 @samp{#} is the line comment character.
98 @section Instruction syntax
99 @cindex instruction syntax, s390
100 @cindex s390 instruction syntax
102 The assembler syntax closely follows the syntax outlined in
103 Enterprise Systems Architecture/390 Principles of Operation (SA22-7201)
104 and the z/Architecture Principles of Operation (SA22-7832).
106 Each instruction has two major parts, the instruction mnemonic
107 and the instruction operands. The instruction format varies.
110 * s390 Register:: Register Naming
111 * s390 Mnemonics:: Instruction Mnemonics
112 * s390 Operands:: Instruction Operands
113 * s390 Formats:: Instruction Formats
114 * s390 Aliases:: Instruction Aliases
115 * s390 Operand Modifier:: Instruction Operand Modifier
116 * s390 Instruction Marker:: Instruction Marker
117 * s390 Literal Pool Entries:: Literal Pool Entries
121 @subsection Register naming
122 @cindex register naming, s390
123 @cindex s390 register naming
125 The @code{@value{AS}} recognizes a number of predefined symbols for the
126 various processor registers. A register specification in one of the
127 instruction formats is an unsigned integer between 0 and 15. The specific
128 instruction and the position of the register in the instruction format
129 denotes the type of the register. The register symbols are prefixed with
133 @multitable {%rN} {the 16 general purpose registers, 0 <= N <= 15}
134 @item %rN @tab the 16 general purpose registers, 0 <= N <= 15
135 @item %fN @tab the 16 floating point registers, 0 <= N <= 15
136 @item %aN @tab the 16 access registers, 0 <= N <= 15
137 @item %cN @tab the 16 control registers, 0 <= N <= 15
138 @item %lit @tab an alias for the general purpose register %r13
139 @item %sp @tab an alias for the general purpose register %r15
144 @subsection Instruction Mnemonics
145 @cindex instruction mnemonics, s390
146 @cindex s390 instruction mnemonics
148 All instructions documented in the Principles of Operation are supported
149 with the mnemonic and order of operands as described.
150 The instruction mnemonic identifies the instruction format
151 (@ref{s390 Formats}) and the specific operation code for the instruction.
152 For example, the @samp{lr} mnemonic denotes the instruction format @samp{RR}
153 with the operation code @samp{0x18}.
155 The definition of the various mnemonics follows a scheme, where the first
156 character usually hint at the type of the instruction:
159 @multitable {sla, sll} {if r is the last character the instruction operates on registers}
160 @item a @tab add instruction, for example @samp{al} for add logical 32-bit
161 @item b @tab branch instruction, for example @samp{bc} for branch on condition
162 @item c @tab compare or convert instruction, for example @samp{cr} for compare
164 @item d @tab divide instruction, for example @samp{dlr} devide logical register
166 @item i @tab insert instruction, for example @samp{ic} insert character
167 @item l @tab load instruction, for example @samp{ltr} load and test register
168 @item mv @tab move instruction, for example @samp{mvc} move character
169 @item m @tab multiply instruction, for example @samp{mh} multiply halfword
170 @item n @tab and instruction, for example @samp{ni} and immediate
171 @item o @tab or instruction, for example @samp{oc} or character
172 @item sla, sll @tab shift left single instruction
173 @item sra, srl @tab shift right single instruction
174 @item st @tab store instruction, for example @samp{stm} store multiple
175 @item s @tab subtract instruction, for example @samp{slr} subtract
177 @item t @tab test or translate instruction, of example @samp{tm} test under mask
178 @item x @tab exclusive or instruction, for example @samp{xc} exclusive or
183 Certain characters at the end of the mnemonic may describe a property
187 @multitable {c} {if r is the last character the instruction operates on registers}
188 @item c @tab the instruction uses a 8-bit character operand
189 @item f @tab the instruction extends a 32-bit operand to 64 bit
190 @item g @tab the operands are treated as 64-bit values
191 @item h @tab the operand uses a 16-bit halfword operand
192 @item i @tab the instruction uses an immediate operand
193 @item l @tab the instruction uses unsigned, logical operands
194 @item m @tab the instruction uses a mask or operates on multiple values
195 @item r @tab if r is the last character, the instruction operates on registers
196 @item y @tab the instruction uses 20-bit displacements
200 There are many exceptions to the scheme outlined in the above lists, in
201 particular for the priviledged instructions. For non-priviledged
202 instruction it works quite well, for example the instruction @samp{clgfr}
203 c: compare instruction, l: unsigned operands, g: 64-bit operands,
204 f: 32- to 64-bit extension, r: register operands. The instruction compares
205 an 64-bit value in a register with the zero extended 32-bit value from
207 For a complete list of all mnemonics see appendix B in the Principles
211 @subsection Instruction Operands
212 @cindex instruction operands, s390
213 @cindex s390 instruction operands
215 Instruction operands can be grouped into three classes, operands located
216 in registers, immediate operands, and operands in storage.
218 A register operand can be located in general, floating-point, access,
219 or control register. The register is identified by a four-bit field.
220 The field containing the register operand is called the R field.
222 Immediate operands are contained within the instruction and can have
223 8, 16 or 32 bits. The field containing the immediate operand is called
224 the I field. Dependent on the instruction the I field is either signed
227 A storage operand consists of an address and a length. The address of a
228 storage operands can be specified in any of these ways:
231 @item The content of a single general R
232 @item The sum of the content of a general register called the base
233 register B plus the content of a displacement field D
234 @item The sum of the contents of two general registers called the
235 index register X and the base register B plus the content of a
237 @item The sum of the current instruction address and a 32-bit signed
238 immediate field multiplied by two.
241 The length of a storage operand can be:
244 @item Implied by the instruction
245 @item Specified by a bitmask
246 @item Specified by a four-bit or eight-bit length field L
247 @item Specified by the content of a general register
250 The notation for storage operand addresses formed from multiple fields is
255 the address for operand number n is formed from the content of general
256 register Bn called the base register and the displacement field Dn.
258 the address for operand number n is formed from the content of general
259 register Xn called the index register, general register Bn called the
260 base register and the displacement field Dn.
262 the address for operand number n is formed from the content of general
263 regiser Bn called the base register and the displacement field Dn.
264 The length of the operand n is specified by the field Ln.
267 The base registers Bn and the index registers Xn of a storage operand can
268 be skipped. If Bn and Xn are skipped, a zero will be stored to the operand
269 field. The notation changes as follows:
272 @multitable @columnfractions 0.30 0.30
273 @headitem full notation @tab short notation
274 @item Dn(0,Bn) @tab Dn(Bn)
275 @item Dn(0,0) @tab Dn
277 @item Dn(Ln,0) @tab Dn(Ln)
283 @subsection Instruction Formats
284 @cindex instruction formats, s390
285 @cindex s390 instruction formats
287 The Principles of Operation manuals lists 26 instruction formats where
288 some of the formats have multiple variants. For the @samp{.insn}
289 pseudo directive the assembler recognizes some of the formats.
290 Typically, the most general variant of the instruction format is used
291 by the @samp{.insn} directive.
293 The following table lists the abbreviations used in the table of
297 @multitable {OpCode / OpCd} {Displacement lower 12 bits for operand x.}
298 @item OpCode / OpCd @tab Part of the op code.
299 @item Bx @tab Base register number for operand x.
300 @item Dx @tab Displacement for operand x.
301 @item DLx @tab Displacement lower 12 bits for operand x.
302 @item DHx @tab Displacement higher 8-bits for operand x.
303 @item Rx @tab Register number for operand x.
304 @item Xx @tab Index register number for operand x.
305 @item Ix @tab Signed immediate for operand x.
306 @item Ux @tab Unsigned immediate for operand x.
310 An instruction is two, four, or six bytes in length and must be aligned
311 on a 2 byte boundary. The first two bits of the instruction specify the
312 length of the instruction, 00 indicates a two byte instruction, 01 and 10
313 indicates a four byte instruction, and 11 indicates a six byte instruction.
315 The following table lists the s390 instruction formats that are available
316 with the @samp{.insn} pseudo directive:
327 @item RI format: <insn> R1,I2
329 +--------+----+----+------------------+
330 | OpCode | R1 |OpCd| I2 |
331 +--------+----+----+------------------+
335 @item RIE format: <insn> R1,R3,I2
337 +--------+----+----+------------------+--------+--------+
338 | OpCode | R1 | R3 | I2 |////////| OpCode |
339 +--------+----+----+------------------+--------+--------+
343 @item RIL format: <insn> R1,I2
345 +--------+----+----+------------------------------------+
346 | OpCode | R1 |OpCd| I2 |
347 +--------+----+----+------------------------------------+
351 @item RILU format: <insn> R1,U2
353 +--------+----+----+------------------------------------+
354 | OpCode | R1 |OpCd| U2 |
355 +--------+----+----+------------------------------------+
359 @item RIS format: <insn> R1,I2,M3,D4(B4)
361 +--------+----+----+----+-------------+--------+--------+
362 | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode |
363 +--------+----+----+----+-------------+--------+--------+
364 0 8 12 16 20 32 36 47
367 @item RR format: <insn> R1,R2
375 @item RRE format: <insn> R1,R2
377 +------------------+--------+----+----+
378 | OpCode |////////| R1 | R2 |
379 +------------------+--------+----+----+
383 @item RRF format: <insn> R1,R2,R3,M4
385 +------------------+----+----+----+----+
386 | OpCode | R3 | M4 | R1 | R2 |
387 +------------------+----+----+----+----+
391 @item RRS format: <insn> R1,R2,M3,D4(B4)
393 +--------+----+----+----+-------------+----+----+--------+
394 | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode |
395 +--------+----+----+----+-------------+----+----+--------+
396 0 8 12 16 20 32 36 40 47
399 @item RS format: <insn> R1,R3,D2(B2)
401 +--------+----+----+----+-------------+
402 | OpCode | R1 | R3 | B2 | D2 |
403 +--------+----+----+----+-------------+
407 @item RSE format: <insn> R1,R3,D2(B2)
409 +--------+----+----+----+-------------+--------+--------+
410 | OpCode | R1 | R3 | B2 | D2 |////////| OpCode |
411 +--------+----+----+----+-------------+--------+--------+
412 0 8 12 16 20 32 40 47
415 @item RSI format: <insn> R1,R3,I2
417 +--------+----+----+------------------------------------+
418 | OpCode | R1 | R3 | I2 |
419 +--------+----+----+------------------------------------+
423 @item RSY format: <insn> R1,R3,D2(B2)
425 +--------+----+----+----+-------------+--------+--------+
426 | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode |
427 +--------+----+----+----+-------------+--------+--------+
428 0 8 12 16 20 32 40 47
431 @item RX format: <insn> R1,D2(X2,B2)
433 +--------+----+----+----+-------------+
434 | OpCode | R1 | X2 | B2 | D2 |
435 +--------+----+----+----+-------------+
439 @item RXE format: <insn> R1,D2(X2,B2)
441 +--------+----+----+----+-------------+--------+--------+
442 | OpCode | R1 | X2 | B2 | D2 |////////| OpCode |
443 +--------+----+----+----+-------------+--------+--------+
444 0 8 12 16 20 32 40 47
447 @item RXF format: <insn> R1,R3,D2(X2,B2)
449 +--------+----+----+----+-------------+----+---+--------+
450 | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode |
451 +--------+----+----+----+-------------+----+---+--------+
452 0 8 12 16 20 32 36 40 47
455 @item RXY format: <insn> R1,D2(X2,B2)
457 +--------+----+----+----+-------------+--------+--------+
458 | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode |
459 +--------+----+----+----+-------------+--------+--------+
460 0 8 12 16 20 32 36 40 47
463 @item S format: <insn> D2(B2)
465 +------------------+----+-------------+
467 +------------------+----+-------------+
471 @item SI format: <insn> D1(B1),I2
473 +--------+---------+----+-------------+
474 | OpCode | I2 | B1 | D1 |
475 +--------+---------+----+-------------+
479 @item SIY format: <insn> D1(B1),U2
481 +--------+---------+----+-------------+--------+--------+
482 | OpCode | I2 | B1 | DL1 | DH1 | OpCode |
483 +--------+---------+----+-------------+--------+--------+
484 0 8 16 20 32 36 40 47
487 @item SIL format: <insn> D1(B1),I2
489 +------------------+----+-------------+-----------------+
490 | OpCode | B1 | D1 | I2 |
491 +------------------+----+-------------+-----------------+
495 @item SS format: <insn> D1(R1,B1),D2(B3),R3
497 +--------+----+----+----+-------------+----+------------+
498 | OpCode | R1 | R3 | B1 | D1 | B2 | D2 |
499 +--------+----+----+----+-------------+----+------------+
500 0 8 12 16 20 32 36 47
503 @item SSE format: <insn> D1(B1),D2(B2)
505 +------------------+----+-------------+----+------------+
506 | OpCode | B1 | D1 | B2 | D2 |
507 +------------------+----+-------------+----+------------+
508 0 8 12 16 20 32 36 47
511 @item SSF format: <insn> D1(B1),D2(B2),R3
513 +--------+----+----+----+-------------+----+------------+
514 | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 |
515 +--------+----+----+----+-------------+----+------------+
516 0 8 12 16 20 32 36 47
521 For the complete list of all instruction format variants see the
522 Principles of Operation manuals.
525 @subsection Instruction Aliases
526 @cindex instruction aliases, s390
527 @cindex s390 instruction aliases
529 A specific bit pattern can have multiple mnemonics, for example
530 the bit pattern @samp{0xa7000000} has the mnemonics @samp{tmh} and
531 @samp{tmlh}. In addition, there are a number of mnemonics recognized by
532 @code{@value{AS}} that are not present in the Principles of Operation.
533 These are the short forms of the branch instructions, where the condition
534 code mask operand is encoded in the mnemonic. This is relevant for the
535 branch instructions, the compare and branch instructions, and the
536 compare and trap instructions.
538 For the branch instructions there are 20 condition code strings that can
539 be used as part of the mnemonic in place of a mask operand in the instruction
543 @multitable @columnfractions .30 .30
544 @headitem instruction @tab short form
545 @item bcr M1,R2 @tab b<m>r R2
546 @item bc M1,D2(X2,B2) @tab b<m> D2(X2,B2)
547 @item brc M1,I2 @tab j<m> I2
548 @item brcl M1,I2 @tab jg<m> I2
552 In the mnemonic for a branch instruction the condition code string <m>
553 can be any of the following:
556 @multitable {nle} {jump on not zero / if not zeros}
557 @item o @tab jump on overflow / if ones
558 @item h @tab jump on A high
559 @item p @tab jump on plus
560 @item nle @tab jump on not low or equal
561 @item l @tab jump on A low
562 @item m @tab jump on minus
563 @item nhe @tab jump on not high or equal
564 @item lh @tab jump on low or high
565 @item ne @tab jump on A not equal B
566 @item nz @tab jump on not zero / if not zeros
567 @item e @tab jump on A equal B
568 @item z @tab jump on zero / if zeroes
569 @item nlh @tab jump on not low or high
570 @item he @tab jump on high or equal
571 @item nl @tab jump on A not low
572 @item nm @tab jump on not minus / if not mixed
573 @item le @tab jump on low or equal
574 @item nh @tab jump on A not high
575 @item np @tab jump on not plus
576 @item no @tab jump on not overflow / if not ones
580 For the compare and branch, and compare and trap instructions there
581 are 12 condition code strings that can be used as part of the mnemonic in
582 place of a mask operand in the instruction format:
585 @multitable @columnfractions .40 .40
586 @headitem instruction @tab short form
587 @item crb R1,R2,M3,D4(B4) @tab crb<m> R1,R2,D4(B4)
588 @item cgrb R1,R2,M3,D4(B4) @tab cgrb<m> R1,R2,D4(B4)
589 @item crj R1,R2,M3,I4 @tab crj<m> R1,R2,I4
590 @item cgrj R1,R2,M3,I4 @tab cgrj<m> R1,R2,I4
591 @item cib R1,I2,M3,D4(B4) @tab cib<m> R1,I2,D4(B4)
592 @item cgib R1,I2,M3,D4(B4) @tab cgib<m> R1,I2,D4(B4)
593 @item cij R1,I2,M3,I4 @tab cij<m> R1,I2,I4
594 @item cgij R1,I2,M3,I4 @tab cgij<m> R1,I2,I4
595 @item crt R1,R2,M3 @tab crt<m> R1,R2
596 @item cgrt R1,R2,M3 @tab cgrt<m> R1,R2
597 @item cit R1,I2,M3 @tab cit<m> R1,I2
598 @item cgit R1,I2,M3 @tab cgit<m> R1,I2
599 @item clrb R1,R2,M3,D4(B4) @tab clrb<m> R1,R2,D4(B4)
600 @item clgrb R1,R2,M3,D4(B4) @tab clgrb<m> R1,R2,D4(B4)
601 @item clrj R1,R2,M3,I4 @tab clrj<m> R1,R2,I4
602 @item clgrj R1,R2,M3,I4 @tab clgrj<m> R1,R2,I4
603 @item clib R1,I2,M3,D4(B4) @tab clib<m> R1,I2,D4(B4)
604 @item clgib R1,I2,M3,D4(B4) @tab clgib<m> R1,I2,D4(B4)
605 @item clij R1,I2,M3,I4 @tab clij<m> R1,I2,I4
606 @item clgij R1,I2,M3,I4 @tab clgij<m> R1,I2,I4
607 @item clrt R1,R2,M3 @tab clrt<m> R1,R2
608 @item clgrt R1,R2,M3 @tab clgrt<m> R1,R2
609 @item clfit R1,I2,M3 @tab clfit<m> R1,I2
610 @item clgit R1,I2,M3 @tab clgit<m> R1,I2
614 In the mnemonic for a compare and branch and compare and trap instruction
615 the condition code string <m> can be any of the following:
618 @multitable {nle} {jump on not zero / if not zeros}
619 @item h @tab jump on A high
620 @item nle @tab jump on not low or equal
621 @item l @tab jump on A low
622 @item nhe @tab jump on not high or equal
623 @item ne @tab jump on A not equal B
624 @item lh @tab jump on low or high
625 @item e @tab jump on A equal B
626 @item nlh @tab jump on not low or high
627 @item nl @tab jump on A not low
628 @item he @tab jump on high or equal
629 @item nh @tab jump on A not high
630 @item le @tab jump on low or equal
634 @node s390 Operand Modifier
635 @subsection Instruction Operand Modifier
636 @cindex instruction operand modifier, s390
637 @cindex s390 instruction operand modifier
639 If a symbol modifier is attached to a symbol in an expression for an
640 instruction operand field, the symbol term is replaced with a reference
641 to an object in the global offset table (GOT) or the procedure linkage
642 table (PLT). The following expressions are allowed:
643 @samp{symbol@@modifier + constant},
644 @samp{symbol@@modifier + label + constant}, and
645 @samp{symbol@@modifier - label + constant}.
646 The term @samp{symbol} is the symbol that will be entered into the GOT or
647 PLT, @samp{label} is a local label, and @samp{constant} is an arbitrary
648 expression that the assembler can evaluate to a constant value.
650 The term @samp{(symbol + constant1)@@modifier +/- label + constant2}
651 is also accepted but a warning message is printed and the term is
652 converted to @samp{symbol@@modifier +/- label + constant1 + constant2}.
657 The @@got modifier can be used for displacement fields, 16-bit immediate
658 fields and 32-bit pc-relative immediate fields. The @@got12 modifier is
659 synonym to @@got. The symbol is added to the GOT. For displacement
660 fields and 16-bit immediate fields the symbol term is replaced with
661 the offset from the start of the GOT to the GOT slot for the symbol.
662 For a 32-bit pc-relative field the pc-relative offset to the GOT
663 slot from the current instruction address is used.
665 The @@gotent modifier can be used for 32-bit pc-relative immediate fields.
666 The symbol is added to the GOT and the symbol term is replaced with
667 the pc-relative offset from the current instruction to the GOT slot for the
670 The @@gotoff modifier can be used for 16-bit immediate fields. The symbol
671 term is replaced with the offset from the start of the GOT to the
672 address of the symbol.
674 The @@gotplt modifier can be used for displacement fields, 16-bit immediate
675 fields, and 32-bit pc-relative immediate fields. A procedure linkage
676 table entry is generated for the symbol and a jump slot for the symbol
677 is added to the GOT. For displacement fields and 16-bit immediate
678 fields the symbol term is replaced with the offset from the start of the
679 GOT to the jump slot for the symbol. For a 32-bit pc-relative field
680 the pc-relative offset to the jump slot from the current instruction
683 The @@plt modifier can be used for 16-bit and 32-bit pc-relative immediate
684 fields. A procedure linkage table entry is generated for the symbol.
685 The symbol term is replaced with the relative offset from the current
686 instruction to the PLT entry for the symbol.
688 The @@pltoff modifier can be used for 16-bit immediate fields. The symbol
689 term is replaced with the offset from the start of the PLT to the address
692 The @@gotntpoff modifier can be used for displacement fields. The symbol
693 is added to the static TLS block and the negated offset to the symbol
694 in the static TLS block is added to the GOT. The symbol term is replaced
695 with the offset to the GOT slot from the start of the GOT.
697 The @@indntpoff modifier can be used for 32-bit pc-relative immediate
698 fields. The symbol is added to the static TLS block and the negated offset
699 to the symbol in the static TLS block is added to the GOT. The symbol term
700 is replaced with the pc-relative offset to the GOT slot from the current
704 For more information about the thread local storage modifiers
705 @samp{gotntpoff} and @samp{indntpoff} see the ELF extension documentation
706 @samp{ELF Handling For Thread-Local Storage}.
708 @node s390 Instruction Marker
709 @subsection Instruction Marker
710 @cindex instruction marker, s390
711 @cindex s390 instruction marker
713 The thread local storage instruction markers are used by the linker to
714 perform code optimization.
718 The :tls_load marker is used to flag the load instruction in the initial
719 exec TLS model that retrieves the offset from the thread pointer to a
720 thread local storage variable from the GOT.
722 The :tls_gdcall marker is used to flag the branch-and-save instruction to
723 the __tls_get_offset function in the global dynamic TLS model.
725 The :tls_ldcall marker is used to flag the branch-and-save instruction to
726 the __tls_get_offset function in the local dynamic TLS model.
729 For more information about the thread local storage instruction marker
730 and the linker optimizations see the ELF extension documentation
731 @samp{ELF Handling For Thread-Local Storage}.
733 @node s390 Literal Pool Entries
734 @subsection Literal Pool Entries
735 @cindex literal pool entries, s390
736 @cindex s390 literal pool entries
738 A literal pool is a collection of values. To access the values a pointer
739 to the literal pool is loaded to a register, the literal pool register.
740 Usually, register %r13 is used as the literal pool register
741 (@ref{s390 Register}). Literal pool entries are created by adding the
742 suffix :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an
743 instruction operand. The expression is added to the literal pool and the
744 operand is replaced with the offset to the literal in the literal pool.
748 The literal pool entry is created as an 8-bit value. An operand modifier
749 must not be used for the original expression.
751 The literal pool entry is created as a 16 bit value. The operand modifier
752 @@got may be used in the original expression. The term @samp{x@@got:lit2}
753 will put the got offset for the global symbol x to the literal pool as
756 The literal pool entry is created as a 32-bit value. The operand modifier
757 @@got and @@plt may be used in the original expression. The term
758 @samp{x@@got:lit4} will put the got offset for the global symbol x to the
759 literal pool as a 32-bit value. The term @samp{x@@plt:lit4} will put the
760 plt offset for the global symbol x to the literal pool as a 32-bit value.
762 The literal pool entry is created as a 64-bit value. The operand modifier
763 @@got and @@plt may be used in the original expression. The term
764 @samp{x@@got:lit8} will put the got offset for the global symbol x to the
765 literal pool as a 64-bit value. The term @samp{x@@plt:lit8} will put the
766 plt offset for the global symbol x to the literal pool as a 64-bit value.
769 The assembler directive @samp{.ltorg} is used to emit all literal pool
770 entries to the current position.
772 @node s390 Directives
773 @section Assembler Directives
775 @code{@value{AS}} for s390 supports all of the standard ELF
776 assembler directives as outlined in the main part of this document.
777 Some directives have been extended and there are some additional
778 directives, which are only available for the s390 @code{@value{AS}}.
781 @cindex @code{.insn} directive, s390
783 This directive permits the numeric representation of an instructions
784 and makes the assembler insert the operands according to one of the
785 instructions formats for @samp{.insn} (@ref{s390 Formats}).
786 For example, the instruction @samp{l %r1,24(%r15)} could be written as
787 @samp{.insn rx,0x58000000,%r1,24(%r15)}.
788 @cindex @code{.short} directive, s390
789 @cindex @code{.long} directive, s390
790 @cindex @code{.quad} directive, s390
794 This directive places one or more 16-bit (.short), 32-bit (.long), or
795 64-bit (.quad) values into the current section. If an ELF or TLS modifier
796 is used only the following expressions are allowed:
797 @samp{symbol@@modifier + constant},
798 @samp{symbol@@modifier + label + constant}, and
799 @samp{symbol@@modifier - label + constant}.
800 The following modifiers are available:
804 The @@got modifier can be used for .short, .long and .quad. The @@got12
805 modifier is synonym to @@got. The symbol is added to the GOT. The symbol
806 term is replaced with offset from the start of the GOT to the GOT slot for
809 The @@gotoff modifier can be used for .short, .long and .quad. The symbol
810 term is replaced with the offset from the start of the GOT to the address
813 The @@gotplt modifier can be used for .long and .quad. A procedure linkage
814 table entry is generated for the symbol and a jump slot for the symbol
815 is added to the GOT. The symbol term is replaced with the offset from the
816 start of the GOT to the jump slot for the symbol.
818 The @@plt modifier can be used for .long and .quad. A procedure linkage
819 table entry us generated for the symbol. The symbol term is replaced with
820 the address of the PLT entry for the symbol.
822 The @@pltoff modifier can be used for .short, .long and .quad. The symbol
823 term is replaced with the offset from the start of the PLT to the address
827 The @@tlsgd and @@tlsldm modifier can be used for .long and .quad. A
828 tls_index structure for the symbol is added to the GOT. The symbol term is
829 replaced with the offset from the start of the GOT to the tls_index structure.
832 The @@gotntpoff and @@indntpoff modifier can be used for .long and .quad.
833 The symbol is added to the static TLS block and the negated offset to the
834 symbol in the static TLS block is added to the GOT. For @@gotntpoff the
835 symbol term is replaced with the offset from the start of the GOT to the
836 GOT slot, for @@indntpoff the symbol term is replaced with the address
839 The @@dtpoff modifier can be used for .long and .quad. The symbol term
840 is replaced with the offset of the symbol relative to the start of the
841 TLS block it is contained in.
843 The @@ntpoff modifier can be used for .long and .quad. The symbol term
844 is replaced with the offset of the symbol relative to the TCB pointer.
847 For more information about the thread local storage modifiers see the
848 ELF extension documentation @samp{ELF Handling For Thread-Local Storage}.
850 @cindex @code{.ltorg} directive, s390
852 This directive causes the current contents of the literal pool to be
853 dumped to the current location (@ref{s390 Literal Pool Entries}).
856 @node s390 Floating Point
857 @section Floating Point
858 @cindex floating point, s390
859 @cindex s390 floating point
861 The assembler recognizes both the @sc{ieee} floating-point instruction and
862 the hexadecimal floating-point instructions. The floating-point constructors
863 @samp{.float}, @samp{.single}, and @samp{.double} always emit the
864 @sc{ieee} format. To assemble hexadecimal floating-point constants the
865 @samp{.long} and @samp{.quad} directives must be used.