gas/doc/c-sh.texi

   1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004,
   2 @c 2005, 2008, 2010  Free Software Foundation, Inc.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @page
   6 @node SH-Dependent
   7 @chapter Renesas / SuperH SH Dependent Features
   8
   9 @cindex SH support
  10 @menu
  11 * SH Options::              Options
  12 * SH Syntax::               Syntax
  13 * SH Floating Point::       Floating Point
  14 * SH Directives::           SH Machine Directives
  15 * SH Opcodes::              Opcodes
  16 @end menu
  17
  18 @node SH Options
  19 @section Options
  20
  21 @cindex SH options
  22 @cindex options, SH
  23 @code{@value{AS}} has following command-line options for the Renesas
  24 (formerly Hitachi) / SuperH SH family.
  25
  26 @table @code
  27 @kindex --little
  28 @kindex --big
  29 @kindex --relax
  30 @kindex --small
  31 @kindex --dsp
  32 @kindex --renesas
  33 @kindex --allow-reg-prefix
  34
  35 @item --little
  36 Generate little endian code.
  37
  38 @item --big
  39 Generate big endian code.
  40
  41 @item --relax
  42 Alter jump instructions for long displacements.
  43
  44 @item --small
  45 Align sections to 4 byte boundaries, not 16.
  46
  47 @item --dsp
  48 Enable sh-dsp insns, and disable sh3e / sh4 insns.
  49
  50 @item --renesas
  51 Disable optimization with section symbol for compatibility with
  52 Renesas assembler.
  53
  54 @item --allow-reg-prefix
  55 Allow '$' as a register name prefix.
  56
  57 @kindex --fdpic
  58 @item --fdpic
  59 Generate an FDPIC object file.
  60
  61 @item --isa=sh4 | sh4a
  62 Specify the sh4 or sh4a instruction set.
  63 @item --isa=dsp
  64 Enable sh-dsp insns, and disable sh3e / sh4 insns.
  65 @item --isa=fp
  66 Enable sh2e, sh3e, sh4, and sh4a insn sets.
  67 @item --isa=all
  68 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
  69
  70 @item -h-tick-hex
  71 Support H'00 style hex constants in addition to 0x00 style.
  72
  73 @end table
  74
  75 @node SH Syntax
  76 @section Syntax
  77
  78 @menu
  79 * SH-Chars::                Special Characters
  80 * SH-Regs::                 Register Names
  81 * SH-Addressing::           Addressing Modes
  82 @end menu
  83
  84 @node SH-Chars
  85 @subsection Special Characters
  86
  87 @cindex line comment character, SH
  88 @cindex SH line comment character
  89 @samp{!} is the line comment character.
  90
  91 @cindex line separator, SH
  92 @cindex statement separator, SH
  93 @cindex SH line separator
  94 You can use @samp{;} instead of a newline to separate statements.
  95
  96 @cindex symbol names, @samp{$} in
  97 @cindex @code{$} in symbol names
  98 Since @samp{$} has no special meaning, you may use it in symbol names.
  99
 100 @node SH-Regs
 101 @subsection Register Names
 102
 103 @cindex SH registers
 104 @cindex registers, SH
 105 You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
 106 @samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
 107 @samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
 108 and @samp{r15} to refer to the SH registers.
 109
 110 The SH also has these control registers:
 111
 112 @table @code
 113 @item pr
 114 procedure register (holds return address)
 115
 116 @item pc
 117 program counter
 118
 119 @item mach
 120 @itemx macl
 121 high and low multiply accumulator registers
 122
 123 @item sr
 124 status register
 125
 126 @item gbr
 127 global base register
 128
 129 @item vbr
 130 vector base register (for interrupt vectors)
 131 @end table
 132
 133 @node SH-Addressing
 134 @subsection Addressing Modes
 135
 136 @cindex addressing modes, SH
 137 @cindex SH addressing modes
 138 @code{@value{AS}} understands the following addressing modes for the SH.
 139 @code{R@var{n}} in the following refers to any of the numbered
 140 registers, but @emph{not} the control registers.
 141
 142 @table @code
 143 @item R@var{n}
 144 Register direct
 145
 146 @item @@R@var{n}
 147 Register indirect
 148
 149 @item @@-R@var{n}
 150 Register indirect with pre-decrement
 151
 152 @item @@R@var{n}+
 153 Register indirect with post-increment
 154
 155 @item @@(@var{disp}, R@var{n})
 156 Register indirect with displacement
 157
 158 @item @@(R0, R@var{n})
 159 Register indexed
 160
 161 @item @@(@var{disp}, GBR)
 162 @code{GBR} offset
 163
 164 @item @@(R0, GBR)
 165 GBR indexed
 166
 167 @item @var{addr}
 168 @itemx @@(@var{disp}, PC)
 169 PC relative address (for branch or for addressing memory).  The
 170 @code{@value{AS}} implementation allows you to use the simpler form
 171 @var{addr} anywhere a PC relative address is called for; the alternate
 172 form is supported for compatibility with other assemblers.
 173
 174 @item #@var{imm}
 175 Immediate data
 176 @end table
 177
 178 @node SH Floating Point
 179 @section Floating Point
 180
 181 @cindex floating point, SH (@sc{ieee})
 182 @cindex SH floating point (@sc{ieee})
 183 SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
 184 SH groups can use @code{.float} directive to generate @sc{ieee}
 185 floating-point numbers.
 186
 187 SH2E and SH3E support single-precision floating point calculations as
 188 well as entirely PCAPI compatible emulation of double-precision
 189 floating point calculations. SH2E and SH3E instructions are a subset of
 190 the floating point calculations conforming to the IEEE754 standard.
 191
 192 In addition to single-precision and double-precision floating-point
 193 operation capability, the on-chip FPU of SH4 has a 128-bit graphic
 194 engine that enables 32-bit floating-point data to be processed 128
 195 bits at a time. It also supports 4 * 4 array operations and inner
 196 product operations. Also, a superscalar architecture is employed that
 197 enables simultaneous execution of two instructions (including FPU
 198 instructions), providing performance of up to twice that of
 199 conventional architectures at the same frequency.
 200
 201 @node SH Directives
 202 @section SH Machine Directives
 203
 204 @cindex SH machine directives
 205 @cindex machine directives, SH
 206 @cindex @code{uaword} directive, SH
 207 @cindex @code{ualong} directive, SH
 208
 209 @table @code
 210 @item uaword
 211 @itemx ualong
 212 @code{@value{AS}} will issue a warning when a misaligned @code{.word} or
 213 @code{.long} directive is used.  You may use @code{.uaword} or
 214 @code{.ualong} to indicate that the value is intentionally misaligned.
 215 @end table
 216
 217 @node SH Opcodes
 218 @section Opcodes
 219
 220 @cindex SH opcode summary
 221 @cindex opcode summary, SH
 222 @cindex mnemonics, SH
 223 @cindex instruction summary, SH
 224 For detailed information on the SH machine instruction set, see
 225 @cite{SH-Microcomputer User's Manual} (Renesas) or
 226 @cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
 227 @cite{SuperH (SH) 64-Bit RISC Series} (SuperH).
 228
 229 @code{@value{AS}} implements all the standard SH opcodes.  No additional
 230 pseudo-instructions are needed on this family.  Note, however, that
 231 because @code{@value{AS}} supports a simpler form of PC-relative
 232 addressing, you may simply write (for example)
 233
 234 @example
 235 mov.l  bar,r0
 236 @end example
 237
 238 @noindent
 239 where other assemblers might require an explicit displacement to
 240 @code{bar} from the program counter:
 241
 242 @example
 243 mov.l  @@(@var{disp}, PC)
 244 @end example
 245
 246 @ifset SMALL
 247 @c this table, due to the multi-col faking and hardcoded order, looks silly
 248 @c except in smallbook.  See comments below "@set SMALL" near top of this file.
 249
 250 Here is a summary of SH opcodes:
 251
 252 @page
 253 @smallexample
 254 @i{Legend:}
 255 Rn        @r{a numbered register}
 256 Rm        @r{another numbered register}
 257 #imm      @r{immediate data}
 258 disp      @r{displacement}
 259 disp8     @r{8-bit displacement}
 260 disp12    @r{12-bit displacement}
 261
 262 add #imm,Rn                    lds.l @@Rn+,PR
 263 add Rm,Rn                      mac.w @@Rm+,@@Rn+
 264 addc Rm,Rn                     mov #imm,Rn
 265 addv Rm,Rn                     mov Rm,Rn
 266 and #imm,R0                    mov.b Rm,@@(R0,Rn)
 267 and Rm,Rn                      mov.b Rm,@@-Rn
 268 and.b #imm,@@(R0,GBR)           mov.b Rm,@@Rn
 269 bf disp8                       mov.b @@(disp,Rm),R0
 270 bra disp12                     mov.b @@(disp,GBR),R0
 271 bsr disp12                     mov.b @@(R0,Rm),Rn
 272 bt disp8                       mov.b @@Rm+,Rn
 273 clrmac                         mov.b @@Rm,Rn
 274 clrt                           mov.b R0,@@(disp,Rm)
 275 cmp/eq #imm,R0                 mov.b R0,@@(disp,GBR)
 276 cmp/eq Rm,Rn                   mov.l Rm,@@(disp,Rn)
 277 cmp/ge Rm,Rn                   mov.l Rm,@@(R0,Rn)
 278 cmp/gt Rm,Rn                   mov.l Rm,@@-Rn
 279 cmp/hi Rm,Rn                   mov.l Rm,@@Rn
 280 cmp/hs Rm,Rn                   mov.l @@(disp,Rn),Rm
 281 cmp/pl Rn                      mov.l @@(disp,GBR),R0
 282 cmp/pz Rn                      mov.l @@(disp,PC),Rn
 283 cmp/str Rm,Rn                  mov.l @@(R0,Rm),Rn
 284 div0s Rm,Rn                    mov.l @@Rm+,Rn
 285 div0u                          mov.l @@Rm,Rn
 286 div1 Rm,Rn                     mov.l R0,@@(disp,GBR)
 287 exts.b Rm,Rn                   mov.w Rm,@@(R0,Rn)
 288 exts.w Rm,Rn                   mov.w Rm,@@-Rn
 289 extu.b Rm,Rn                   mov.w Rm,@@Rn
 290 extu.w Rm,Rn                   mov.w @@(disp,Rm),R0
 291 jmp @@Rn                        mov.w @@(disp,GBR),R0
 292 jsr @@Rn                        mov.w @@(disp,PC),Rn
 293 ldc Rn,GBR                     mov.w @@(R0,Rm),Rn
 294 ldc Rn,SR                      mov.w @@Rm+,Rn
 295 ldc Rn,VBR                     mov.w @@Rm,Rn
 296 ldc.l @@Rn+,GBR                 mov.w R0,@@(disp,Rm)
 297 ldc.l @@Rn+,SR                  mov.w R0,@@(disp,GBR)
 298 ldc.l @@Rn+,VBR                 mova @@(disp,PC),R0
 299 lds Rn,MACH                    movt Rn
 300 lds Rn,MACL                    muls Rm,Rn
 301 lds Rn,PR                      mulu Rm,Rn
 302 lds.l @@Rn+,MACH                neg Rm,Rn
 303 lds.l @@Rn+,MACL                negc Rm,Rn
 304 @page
 305 nop                            stc VBR,Rn
 306 not Rm,Rn                      stc.l GBR,@@-Rn
 307 or #imm,R0                     stc.l SR,@@-Rn
 308 or Rm,Rn                       stc.l VBR,@@-Rn
 309 or.b #imm,@@(R0,GBR)            sts MACH,Rn
 310 rotcl Rn                       sts MACL,Rn
 311 rotcr Rn                       sts PR,Rn
 312 rotl Rn                        sts.l MACH,@@-Rn
 313 rotr Rn                        sts.l MACL,@@-Rn
 314 rte                            sts.l PR,@@-Rn
 315 rts                            sub Rm,Rn
 316 sett                           subc Rm,Rn
 317 shal Rn                        subv Rm,Rn
 318 shar Rn                        swap.b Rm,Rn
 319 shll Rn                        swap.w Rm,Rn
 320 shll16 Rn                      tas.b @@Rn
 321 shll2 Rn                       trapa #imm
 322 shll8 Rn                       tst #imm,R0
 323 shlr Rn                        tst Rm,Rn
 324 shlr16 Rn                      tst.b #imm,@@(R0,GBR)
 325 shlr2 Rn                       xor #imm,R0
 326 shlr8 Rn                       xor Rm,Rn
 327 sleep                          xor.b #imm,@@(R0,GBR)
 328 stc GBR,Rn                     xtrct Rm,Rn
 329 stc SR,Rn
 330 @end smallexample
 331 @end ifset
 332
 333 @ifset Renesas-all
 334 @ifclear GENERIC
 335 @raisesections
 336 @end ifclear
 337 @end ifset
 338