1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004,
2 @c 2005, 2008, 2010, 2011, 2012 Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
7 @chapter Renesas / SuperH SH Dependent Features
11 * SH Options:: Options
13 * SH Floating Point:: Floating Point
14 * SH Directives:: SH Machine Directives
15 * SH Opcodes:: Opcodes
23 @code{@value{AS}} has following command-line options for the Renesas
24 (formerly Hitachi) / SuperH SH family.
33 @kindex --allow-reg-prefix
36 Generate little endian code.
39 Generate big endian code.
42 Alter jump instructions for long displacements.
45 Align sections to 4 byte boundaries, not 16.
48 Enable sh-dsp insns, and disable sh3e / sh4 insns.
51 Disable optimization with section symbol for compatibility with
54 @item --allow-reg-prefix
55 Allow '$' as a register name prefix.
59 Generate an FDPIC object file.
61 @item --isa=sh4 | sh4a
62 Specify the sh4 or sh4a instruction set.
64 Enable sh-dsp insns, and disable sh3e / sh4 insns.
66 Enable sh2e, sh3e, sh4, and sh4a insn sets.
68 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
71 Support H'00 style hex constants in addition to 0x00 style.
79 * SH-Chars:: Special Characters
80 * SH-Regs:: Register Names
81 * SH-Addressing:: Addressing Modes
85 @subsection Special Characters
87 @cindex line comment character, SH
88 @cindex SH line comment character
89 @samp{!} is the line comment character.
91 @cindex line separator, SH
92 @cindex statement separator, SH
93 @cindex SH line separator
94 You can use @samp{;} instead of a newline to separate statements.
96 If a @samp{#} appears as the first character of a line then the whole
97 line is treated as a comment, but in this case the line could also be
98 a logical line number directive (@pxref{Comments}) or a preprocessor
99 control command (@pxref{Preprocessing}).
101 @cindex symbol names, @samp{$} in
102 @cindex @code{$} in symbol names
103 Since @samp{$} has no special meaning, you may use it in symbol names.
106 @subsection Register Names
109 @cindex registers, SH
110 You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
111 @samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
112 @samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
113 and @samp{r15} to refer to the SH registers.
115 The SH also has these control registers:
119 procedure register (holds return address)
126 high and low multiply accumulator registers
135 vector base register (for interrupt vectors)
139 @subsection Addressing Modes
141 @cindex addressing modes, SH
142 @cindex SH addressing modes
143 @code{@value{AS}} understands the following addressing modes for the SH.
144 @code{R@var{n}} in the following refers to any of the numbered
145 registers, but @emph{not} the control registers.
155 Register indirect with pre-decrement
158 Register indirect with post-increment
160 @item @@(@var{disp}, R@var{n})
161 Register indirect with displacement
163 @item @@(R0, R@var{n})
166 @item @@(@var{disp}, GBR)
173 @itemx @@(@var{disp}, PC)
174 PC relative address (for branch or for addressing memory). The
175 @code{@value{AS}} implementation allows you to use the simpler form
176 @var{addr} anywhere a PC relative address is called for; the alternate
177 form is supported for compatibility with other assemblers.
183 @node SH Floating Point
184 @section Floating Point
186 @cindex floating point, SH (@sc{ieee})
187 @cindex SH floating point (@sc{ieee})
188 SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
189 SH groups can use @code{.float} directive to generate @sc{ieee}
190 floating-point numbers.
192 SH2E and SH3E support single-precision floating point calculations as
193 well as entirely PCAPI compatible emulation of double-precision
194 floating point calculations. SH2E and SH3E instructions are a subset of
195 the floating point calculations conforming to the IEEE754 standard.
197 In addition to single-precision and double-precision floating-point
198 operation capability, the on-chip FPU of SH4 has a 128-bit graphic
199 engine that enables 32-bit floating-point data to be processed 128
200 bits at a time. It also supports 4 * 4 array operations and inner
201 product operations. Also, a superscalar architecture is employed that
202 enables simultaneous execution of two instructions (including FPU
203 instructions), providing performance of up to twice that of
204 conventional architectures at the same frequency.
207 @section SH Machine Directives
209 @cindex SH machine directives
210 @cindex machine directives, SH
211 @cindex @code{uaword} directive, SH
212 @cindex @code{ualong} directive, SH
213 @cindex @code{uaquad} directive, SH
219 @code{@value{AS}} will issue a warning when a misaligned @code{.word},
220 @code{.long}, or @code{.quad} directive is used. You may use
221 @code{.uaword}, @code{.ualong}, or @code{.uaquad} to indicate that the
222 value is intentionally misaligned.
228 @cindex SH opcode summary
229 @cindex opcode summary, SH
230 @cindex mnemonics, SH
231 @cindex instruction summary, SH
232 For detailed information on the SH machine instruction set, see
233 @cite{SH-Microcomputer User's Manual} (Renesas) or
234 @cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
235 @cite{SuperH (SH) 64-Bit RISC Series} (SuperH).
237 @code{@value{AS}} implements all the standard SH opcodes. No additional
238 pseudo-instructions are needed on this family. Note, however, that
239 because @code{@value{AS}} supports a simpler form of PC-relative
240 addressing, you may simply write (for example)
247 where other assemblers might require an explicit displacement to
248 @code{bar} from the program counter:
251 mov.l @@(@var{disp}, PC)
255 @c this table, due to the multi-col faking and hardcoded order, looks silly
256 @c except in smallbook. See comments below "@set SMALL" near top of this file.
258 Here is a summary of SH opcodes:
263 Rn @r{a numbered register}
264 Rm @r{another numbered register}
265 #imm @r{immediate data}
266 disp @r{displacement}
267 disp8 @r{8-bit displacement}
268 disp12 @r{12-bit displacement}
270 add #imm,Rn lds.l @@Rn+,PR
271 add Rm,Rn mac.w @@Rm+,@@Rn+
272 addc Rm,Rn mov #imm,Rn
274 and #imm,R0 mov.b Rm,@@(R0,Rn)
275 and Rm,Rn mov.b Rm,@@-Rn
276 and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
277 bf disp8 mov.b @@(disp,Rm),R0
278 bra disp12 mov.b @@(disp,GBR),R0
279 bsr disp12 mov.b @@(R0,Rm),Rn
280 bt disp8 mov.b @@Rm+,Rn
282 clrt mov.b R0,@@(disp,Rm)
283 cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
284 cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
285 cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
286 cmp/gt Rm,Rn mov.l Rm,@@-Rn
287 cmp/hi Rm,Rn mov.l Rm,@@Rn
288 cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
289 cmp/pl Rn mov.l @@(disp,GBR),R0
290 cmp/pz Rn mov.l @@(disp,PC),Rn
291 cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
292 div0s Rm,Rn mov.l @@Rm+,Rn
294 div1 Rm,Rn mov.l R0,@@(disp,GBR)
295 exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
296 exts.w Rm,Rn mov.w Rm,@@-Rn
297 extu.b Rm,Rn mov.w Rm,@@Rn
298 extu.w Rm,Rn mov.w @@(disp,Rm),R0
299 jmp @@Rn mov.w @@(disp,GBR),R0
300 jsr @@Rn mov.w @@(disp,PC),Rn
301 ldc Rn,GBR mov.w @@(R0,Rm),Rn
302 ldc Rn,SR mov.w @@Rm+,Rn
303 ldc Rn,VBR mov.w @@Rm,Rn
304 ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
305 ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
306 ldc.l @@Rn+,VBR mova @@(disp,PC),R0
308 lds Rn,MACL muls Rm,Rn
310 lds.l @@Rn+,MACH neg Rm,Rn
311 lds.l @@Rn+,MACL negc Rm,Rn
314 not Rm,Rn stc.l GBR,@@-Rn
315 or #imm,R0 stc.l SR,@@-Rn
316 or Rm,Rn stc.l VBR,@@-Rn
317 or.b #imm,@@(R0,GBR) sts MACH,Rn
320 rotl Rn sts.l MACH,@@-Rn
321 rotr Rn sts.l MACL,@@-Rn
332 shlr16 Rn tst.b #imm,@@(R0,GBR)
335 sleep xor.b #imm,@@(R0,GBR)
336 stc GBR,Rn xtrct Rm,Rn