1 @c Copyright (C) 1991-2014 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter SPARC Dependent Features
10 @node Machine Dependencies
11 @chapter SPARC Dependent Features
16 * Sparc-Opts:: Options
17 * Sparc-Aligned-Data:: Option to enforce aligned data
18 * Sparc-Syntax:: Syntax
19 * Sparc-Float:: Floating Point
20 * Sparc-Directives:: Sparc Machine Directives
26 @cindex options for SPARC
28 @cindex architectures, SPARC
29 @cindex SPARC architectures
30 The SPARC chip family includes several successive versions, using the same
31 core instruction set, but including a few additional instructions at
32 each version. There are exceptions to this however. For details on what
33 instructions each variant supports, please see the chip's architecture
36 By default, @code{@value{AS}} assumes the core instruction set (SPARC
37 v6), but ``bumps'' the architecture level as needed: it switches to
38 successively higher architectures as it encounters instructions that
39 only exist in the higher levels.
41 If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump
42 past sparclite by default, an option must be passed to enable the
45 GAS treats sparclite as being compatible with v8, unless an architecture
46 is explicitly requested. SPARC v9 is always incompatible with sparclite.
48 @c The order here is the same as the order of enum sparc_opcode_arch_val
49 @c to give the user a sense of the order of the "bumping".
71 @item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite
72 @itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv
73 @itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v
74 @itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
75 @itemx -Asparcvis3 | -Asparcvis3r
76 Use one of the @samp{-A} options to select one of the SPARC
77 architectures explicitly. If you select an architecture explicitly,
78 @code{@value{AS}} reports a fatal error if it encounters an instruction
79 or feature requiring an incompatible or higher level.
81 @samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc},
82 @samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment.
84 @samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d}, and
85 @samp{-Av9v} select a 64 bit environment and are not available unless GAS
86 is explicitly configured with 64 bit environment support.
88 @samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with
89 UltraSPARC VIS 1.0 extensions.
91 @samp{-Av8plusb} and @samp{-Av9b} enable the UltraSPARC VIS 2.0 instructions,
92 as well as the instructions enabled by @samp{-Av8plusa} and @samp{-Av9a}.
94 @samp{-Av8plusc} and @samp{-Av9c} enable the UltraSPARC Niagara instructions,
95 as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}.
97 @samp{-Av8plusd} and @samp{-Av9d} enable the floating point fused
98 multiply-add, VIS 3.0, and HPC extension instructions, as well as the
99 instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}.
101 @samp{-Av8plusv} and @samp{-Av9v} enable the 'random', transactional
102 memory, floating point unfused multiply-add, integer multiply-add, and
103 cache sparing store instructions, as well as the instructions enabled
104 by @samp{-Av8plusd} and @samp{-Av9d}.
106 @samp{-Asparc} specifies a v9 environment. It is equivalent to
107 @samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise.
109 @samp{-Asparcvis} specifies a v9a environment. It is equivalent to
110 @samp{-Av9a} if the word size is 64-bit, and @samp{-Av8plusa} otherwise.
112 @samp{-Asparcvis2} specifies a v9b environment. It is equivalent to
113 @samp{-Av9b} if the word size is 64-bit, and @samp{-Av8plusb} otherwise.
115 @samp{-Asparcfmaf} specifies a v9b environment with the floating point
116 fused multiply-add instructions enabled.
118 @samp{-Asparcima} specifies a v9b environment with the integer
119 multiply-add instructions enabled.
121 @samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0,
122 HPC , and floating point fused multiply-add instructions enabled.
124 @samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0,
125 HPC, transactional memory, random, and floating point unfused multiply-add
126 instructions enabled.
128 @item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
129 @itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a
130 @itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v
131 @itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
132 @itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
133 @itemx -xarch=sparcvis3r
134 For compatibility with the SunOS v9 assembler. These options are
135 equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
136 -Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9v, -Asparc, -Asparcvis,
137 -Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, and -Asparcvis3r,
141 Warn whenever it is necessary to switch to another level.
142 If an architecture level is explicitly requested, GAS will not issue
143 warnings until that level is reached, and will then bump the level
144 as required (except between incompatible levels).
147 Select the word size, either 32 bits or 64 bits.
148 These options are only available with the ELF object file format,
149 and require that the necessary BFD support has been included.
152 @node Sparc-Aligned-Data
153 @section Enforcing aligned data
155 @cindex data alignment on SPARC
156 @cindex SPARC data alignment
157 SPARC GAS normally permits data to be misaligned. For example, it
158 permits the @code{.long} pseudo-op to be used on a byte boundary.
159 However, the native SunOS assemblers issue an error when they see
162 @kindex --enforce-aligned-data
163 You can use the @code{--enforce-aligned-data} option to make SPARC GAS
164 also issue an error about misaligned data, just as the SunOS
167 The @code{--enforce-aligned-data} option is not the default because gcc
168 issues misaligned data pseudo-ops when it initializes certain packed
169 data structures (structures defined using the @code{packed} attribute).
170 You may have to assemble with GAS in order to initialize packed data
171 structures in your own code.
174 @cindex syntax, SPARC
176 @section Sparc Syntax
177 The assembler syntax closely follows The Sparc Architecture Manual,
178 versions 8 and 9, as well as most extensions defined by Sun
179 for their UltraSPARC and Niagara line of processors.
182 * Sparc-Chars:: Special Characters
183 * Sparc-Regs:: Register Names
184 * Sparc-Constants:: Constant Names
185 * Sparc-Relocs:: Relocations
186 * Sparc-Size-Translations:: Size Translations
190 @subsection Special Characters
192 @cindex line comment character, Sparc
193 @cindex Sparc line comment character
194 A @samp{!} character appearing anywhere on a line indicates the start
195 of a comment that extends to the end of that line.
197 If a @samp{#} appears as the first character of a line then the whole
198 line is treated as a comment, but in this case the line could also be
199 a logical line number directive (@pxref{Comments}) or a preprocessor
200 control command (@pxref{Preprocessing}).
202 @cindex line separator, Sparc
203 @cindex statement separator, Sparc
204 @cindex Sparc line separator
205 @samp{;} can be used instead of a newline to separate statements.
208 @subsection Register Names
209 @cindex Sparc registers
210 @cindex register names, Sparc
212 The Sparc integer register file is broken down into global,
213 outgoing, local, and incoming.
217 The 8 global registers are referred to as @samp{%g@var{n}}.
220 The 8 outgoing registers are referred to as @samp{%o@var{n}}.
223 The 8 local registers are referred to as @samp{%l@var{n}}.
226 The 8 incoming registers are referred to as @samp{%i@var{n}}.
229 The frame pointer register @samp{%i6} can be referenced using
230 the alias @samp{%fp}.
233 The stack pointer register @samp{%o6} can be referenced using
234 the alias @samp{%sp}.
237 Floating point registers are simply referred to as @samp{%f@var{n}}.
238 When assembling for pre-V9, only 32 floating point registers
239 are available. For V9 and later there are 64, but there are
240 restrictions when referencing the upper 32 registers. They
241 can only be accessed as double or quad, and thus only even
242 or quad numbered accesses are allowed. For example, @samp{%f34}
243 is a legal floating point register, but @samp{%f35} is not.
245 Certain V9 instructions allow access to ancillary state registers.
246 Most simply they can be referred to as @samp{%asr@var{n}} where
247 @var{n} can be from 16 to 31. However, there are some aliases
248 defined to reference ASR registers defined for various UltraSPARC
253 The tick compare register is referred to as @samp{%tick_cmpr}.
256 The system tick register is referred to as @samp{%stick}. An alias,
257 @samp{%sys_tick}, exists but is deprecated and should not be used
261 The system tick compare register is referred to as @samp{%stick_cmpr}.
262 An alias, @samp{%sys_tick_cmpr}, exists but is deprecated and should
263 not be used by new software.
266 The software interrupt register is referred to as @samp{%softint}.
269 The set software interrupt register is referred to as @samp{%set_softint}.
270 The mnemonic @samp{%softint_set} is provided as an alias.
273 The clear software interrupt register is referred to as
274 @samp{%clear_softint}. The mnemonic @samp{%softint_clear} is provided
278 The performance instrumentation counters register is referred to as
282 The performance control register is referred to as @samp{%pcr}.
285 The graphics status register is referred to as @samp{%gsr}.
288 The V9 dispatch control register is referred to as @samp{%dcr}.
291 Various V9 branch and conditional move instructions allow
292 specification of which set of integer condition codes to
293 test. These are referred to as @samp{%xcc} and @samp{%icc}.
295 In V9, there are 4 sets of floating point condition codes
296 which are referred to as @samp{%fcc@var{n}}.
298 Several special privileged and non-privileged registers
303 The V9 address space identifier register is referred to as @samp{%asi}.
306 The V9 restorable windows register is referred to as @samp{%canrestore}.
309 The V9 savable windows register is referred to as @samp{%cansave}.
312 The V9 clean windows register is referred to as @samp{%cleanwin}.
315 The V9 current window pointer register is referred to as @samp{%cwp}.
318 The floating-point queue register is referred to as @samp{%fq}.
321 The V8 co-processor queue register is referred to as @samp{%cq}.
324 The floating point status register is referred to as @samp{%fsr}.
327 The other windows register is referred to as @samp{%otherwin}.
330 The V9 program counter register is referred to as @samp{%pc}.
333 The V9 next program counter register is referred to as @samp{%npc}.
336 The V9 processor interrupt level register is referred to as @samp{%pil}.
339 The V9 processor state register is referred to as @samp{%pstate}.
342 The trap base address register is referred to as @samp{%tba}.
345 The V9 tick register is referred to as @samp{%tick}.
348 The V9 trap level is referred to as @samp{%tl}.
351 The V9 trap program counter is referred to as @samp{%tpc}.
354 The V9 trap next program counter is referred to as @samp{%tnpc}.
357 The V9 trap state is referred to as @samp{%tstate}.
360 The V9 trap type is referred to as @samp{%tt}.
363 The V9 condition codes is referred to as @samp{%ccr}.
366 The V9 floating-point registers state is referred to as @samp{%fprs}.
369 The V9 version register is referred to as @samp{%ver}.
372 The V9 window state register is referred to as @samp{%wstate}.
375 The Y register is referred to as @samp{%y}.
378 The V8 window invalid mask register is referred to as @samp{%wim}.
381 The V8 processor state register is referred to as @samp{%psr}.
384 The V9 global register level register is referred to as @samp{%gl}.
387 Several special register names exist for hypervisor mode code:
391 The hyperprivileged processor state register is referred to as
395 The hyperprivileged trap state register is referred to as @samp{%htstate}.
398 The hyperprivileged interrupt pending register is referred to as
402 The hyperprivileged trap base address register is referred to as
406 The hyperprivileged implementation version register is referred
410 The hyperprivileged system tick compare register is referred
411 to as @samp{%hstick_cmpr}. Note that there is no @samp{%hstick}
412 register, the normal @samp{%stick} is used.
415 @node Sparc-Constants
416 @subsection Constants
417 @cindex Sparc constants
418 @cindex constants, Sparc
420 Several Sparc instructions take an immediate operand field for
421 which mnemonic names exist. Two such examples are @samp{membar}
422 and @samp{prefetch}. Another example are the set of V9
423 memory access instruction that allow specification of an
424 address space identifier.
426 The @samp{membar} instruction specifies a memory barrier that is
427 the defined by the operand which is a bitmask. The supported
432 @samp{#Sync} requests that all operations (including nonmemory
433 reference operations) appearing prior to the @code{membar} must have
434 been performed and the effects of any exceptions become visible before
435 any instructions after the @code{membar} may be initiated. This
436 corresponds to @code{membar} cmask field bit 2.
439 @samp{#MemIssue} requests that all memory reference operations
440 appearing prior to the @code{membar} must have been performed before
441 any memory operation after the @code{membar} may be initiated. This
442 corresponds to @code{membar} cmask field bit 1.
445 @samp{#Lookaside} requests that a store appearing prior to the
446 @code{membar} must complete before any load following the
447 @code{membar} referencing the same address can be initiated. This
448 corresponds to @code{membar} cmask field bit 0.
451 @samp{#StoreStore} defines that the effects of all stores appearing
452 prior to the @code{membar} instruction must be visible to all
453 processors before the effect of any stores following the
454 @code{membar}. Equivalent to the deprecated @code{stbar} instruction.
455 This corresponds to @code{membar} mmask field bit 3.
458 @samp{#LoadStore} defines all loads appearing prior to the
459 @code{membar} instruction must have been performed before the effect
460 of any stores following the @code{membar} is visible to any other
461 processor. This corresponds to @code{membar} mmask field bit 2.
464 @samp{#StoreLoad} defines that the effects of all stores appearing
465 prior to the @code{membar} instruction must be visible to all
466 processors before loads following the @code{membar} may be performed.
467 This corresponds to @code{membar} mmask field bit 1.
470 @samp{#LoadLoad} defines that all loads appearing prior to the
471 @code{membar} instruction must have been performed before any loads
472 following the @code{membar} may be performed. This corresponds to
473 @code{membar} mmask field bit 0.
477 These values can be ored together, for example:
481 membar #StoreLoad | #LoadLoad
482 membar #StoreLoad | #StoreStore
485 The @code{prefetch} and @code{prefetcha} instructions take a prefetch
486 function code. The following prefetch function code constant
487 mnemonics are available:
491 @samp{#n_reads} requests a prefetch for several reads, and corresponds
492 to a prefetch function code of 0.
494 @samp{#one_read} requests a prefetch for one read, and corresponds
495 to a prefetch function code of 1.
497 @samp{#n_writes} requests a prefetch for several writes (and possibly
498 reads), and corresponds to a prefetch function code of 2.
500 @samp{#one_write} requests a prefetch for one write, and corresponds
501 to a prefetch function code of 3.
503 @samp{#page} requests a prefetch page, and corresponds to a prefetch
506 @samp{#invalidate} requests a prefetch invalidate, and corresponds to
507 a prefetch function code of 16.
509 @samp{#unified} requests a prefetch to the nearest unified cache, and
510 corresponds to a prefetch function code of 17.
512 @samp{#n_reads_strong} requests a strong prefetch for several reads,
513 and corresponds to a prefetch function code of 20.
515 @samp{#one_read_strong} requests a strong prefetch for one read,
516 and corresponds to a prefetch function code of 21.
518 @samp{#n_writes_strong} requests a strong prefetch for several writes,
519 and corresponds to a prefetch function code of 22.
521 @samp{#one_write_strong} requests a strong prefetch for one write,
522 and corresponds to a prefetch function code of 23.
524 Onle one prefetch code may be specified. Here are some examples:
527 prefetch [%l0 + %l2], #one_read
528 prefetch [%g2 + 8], #n_writes
529 prefetcha [%g1] 0x8, #unified
530 prefetcha [%o0 + 0x10] %asi, #n_reads
533 The actual behavior of a given prefetch function code is processor
534 specific. If a processor does not implement a given prefetch
535 function code, it will treat the prefetch instruction as a nop.
537 For instructions that accept an immediate address space identifier,
538 @code{@value{AS}} provides many mnemonics corresponding to
539 V9 defined as well as UltraSPARC and Niagara extended values.
540 For example, @samp{#ASI_P} and @samp{#ASI_BLK_INIT_QUAD_LDD_AIUS}.
541 See the V9 and processor specific manuals for details.
546 @subsection Relocations
547 @cindex Sparc relocations
548 @cindex relocations, Sparc
550 ELF relocations are available as defined in the 32-bit and 64-bit
551 Sparc ELF specifications.
553 @code{R_SPARC_HI22} is obtained using @samp{%hi} and @code{R_SPARC_LO10}
554 is obtained using @samp{%lo}. Likewise @code{R_SPARC_HIX22} is
555 obtained from @samp{%hix} and @code{R_SPARC_LOX10} is obtained
556 using @samp{%lox}. For example:
559 sethi %hi(symbol), %g1
560 or %g1, %lo(symbol), %g1
562 sethi %hix(symbol), %g1
563 xor %g1, %lox(symbol), %g1
566 These ``high'' mnemonics extract bits 31:10 of their operand,
567 and the ``low'' mnemonics extract bits 9:0 of their operand.
569 V9 code model relocations can be requested as follows:
573 @code{R_SPARC_HH22} is requested using @samp{%hh}. It can
574 also be generated using @samp{%uhi}.
576 @code{R_SPARC_HM10} is requested using @samp{%hm}. It can
577 also be generated using @samp{%ulo}.
579 @code{R_SPARC_LM22} is requested using @samp{%lm}.
582 @code{R_SPARC_H44} is requested using @samp{%h44}.
584 @code{R_SPARC_M44} is requested using @samp{%m44}.
586 @code{R_SPARC_L44} is requested using @samp{%l44} or @samp{%l34}.
588 @code{R_SPARC_H34} is requested using @samp{%h34}.
591 The @samp{%l34} generates a @code{R_SPARC_L44} relocation because it
592 calculates the necessary value, and therefore no explicit
593 @code{R_SPARC_L34} relocation needed to be created for this purpose.
595 The @samp{%h34} and @samp{%l34} relocations are used for the abs34 code
596 model. Here is an example abs34 address generation sequence:
599 sethi %h34(symbol), %g1
601 or %g1, %l34(symbol), %g1
604 The PC relative relocation @code{R_SPARC_PC22} can be obtained by
605 enclosing an operand inside of @samp{%pc22}. Likewise, the
606 @code{R_SPARC_PC10} relocation can be obtained using @samp{%pc10}.
607 These are mostly used when assembling PIC code. For example, the
608 standard PIC sequence on Sparc to get the base of the global offset
609 table, PC relative, into a register, can be performed as:
612 sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
613 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
616 Several relocations exist to allow the link editor to potentially
617 optimize GOT data references. The @code{R_SPARC_GOTDATA_OP_HIX22}
618 relocation can obtained by enclosing an operand inside of
619 @samp{%gdop_hix22}. The @code{R_SPARC_GOTDATA_OP_LOX10}
620 relocation can obtained by enclosing an operand inside of
621 @samp{%gdop_lox10}. Likewise, @code{R_SPARC_GOTDATA_OP} can be
622 obtained by enclosing an operand inside of @samp{%gdop}.
623 For example, assuming the GOT base is in register @code{%l7}:
626 sethi %gdop_hix22(symbol), %l1
627 xor %l1, %gdop_lox10(symbol), %l1
628 ld [%l7 + %l1], %l2, %gdop(symbol)
631 There are many relocations that can be requested for access to
632 thread local storage variables. All of the Sparc TLS mnemonics
637 @code{R_SPARC_TLS_GD_HI22} is requested using @samp{%tgd_hi22}.
639 @code{R_SPARC_TLS_GD_LO10} is requested using @samp{%tgd_lo10}.
641 @code{R_SPARC_TLS_GD_ADD} is requested using @samp{%tgd_add}.
643 @code{R_SPARC_TLS_GD_CALL} is requested using @samp{%tgd_call}.
646 @code{R_SPARC_TLS_LDM_HI22} is requested using @samp{%tldm_hi22}.
648 @code{R_SPARC_TLS_LDM_LO10} is requested using @samp{%tldm_lo10}.
650 @code{R_SPARC_TLS_LDM_ADD} is requested using @samp{%tldm_add}.
652 @code{R_SPARC_TLS_LDM_CALL} is requested using @samp{%tldm_call}.
655 @code{R_SPARC_TLS_LDO_HIX22} is requested using @samp{%tldo_hix22}.
657 @code{R_SPARC_TLS_LDO_LOX10} is requested using @samp{%tldo_lox10}.
659 @code{R_SPARC_TLS_LDO_ADD} is requested using @samp{%tldo_add}.
662 @code{R_SPARC_TLS_IE_HI22} is requested using @samp{%tie_hi22}.
664 @code{R_SPARC_TLS_IE_LO10} is requested using @samp{%tie_lo10}.
666 @code{R_SPARC_TLS_IE_LD} is requested using @samp{%tie_ld}.
668 @code{R_SPARC_TLS_IE_LDX} is requested using @samp{%tie_ldx}.
670 @code{R_SPARC_TLS_IE_ADD} is requested using @samp{%tie_add}.
673 @code{R_SPARC_TLS_LE_HIX22} is requested using @samp{%tle_hix22}.
675 @code{R_SPARC_TLS_LE_LOX10} is requested using @samp{%tle_lox10}.
678 Here are some example TLS model sequences.
680 First, General Dynamic:
683 sethi %tgd_hi22(symbol), %l1
684 add %l1, %tgd_lo10(symbol), %l1
685 add %l7, %l1, %o0, %tgd_add(symbol)
686 call __tls_get_addr, %tgd_call(symbol)
693 sethi %tldm_hi22(symbol), %l1
694 add %l1, %tldm_lo10(symbol), %l1
695 add %l7, %l1, %o0, %tldm_add(symbol)
696 call __tls_get_addr, %tldm_call(symbol)
699 sethi %tldo_hix22(symbol), %l1
700 xor %l1, %tldo_lox10(symbol), %l1
701 add %o0, %l1, %l1, %tldo_add(symbol)
707 sethi %tie_hi22(symbol), %l1
708 add %l1, %tie_lo10(symbol), %l1
709 ld [%l7 + %l1], %o0, %tie_ld(symbol)
710 add %g7, %o0, %o0, %tie_add(symbol)
712 sethi %tie_hi22(symbol), %l1
713 add %l1, %tie_lo10(symbol), %l1
714 ldx [%l7 + %l1], %o0, %tie_ldx(symbol)
715 add %g7, %o0, %o0, %tie_add(symbol)
718 And finally, Local Exec:
721 sethi %tle_hix22(symbol), %l1
722 add %l1, %tle_lox10(symbol), %l1
726 When assembling for 64-bit, and a secondary constant addend is
727 specified in an address expression that would normally generate
728 an @code{R_SPARC_LO10} relocation, the assembler will emit an
729 @code{R_SPARC_OLO10} instead.
731 @node Sparc-Size-Translations
732 @subsection Size Translations
733 @cindex Sparc size translations
734 @cindex size, translations, Sparc
736 Often it is desirable to write code in an operand size agnostic
737 manner. @code{@value{AS}} provides support for this via
738 operand size opcode translations. Translations are supported
739 for loads, stores, shifts, compare-and-swap atomics, and the
740 @samp{clr} synthetic instruction.
742 If generating 32-bit code, @code{@value{AS}} will generate the
743 32-bit opcode. Whereas if 64-bit code is being generated,
744 the 64-bit opcode will be emitted. For example @code{ldn}
745 will be transformed into @code{ld} for 32-bit code and
746 @code{ldx} for 64-bit code.
748 Here is an example meant to demonstrate all the supported
760 casna [%o0] %asi, %o1, %o2
764 In 32-bit mode @code{@value{AS}} will emit:
775 casa [%o0] %asi, %o1, %o2
779 And in 64-bit mode @code{@value{AS}} will emit:
790 casxa [%o0] %asi, %o1, %o2
794 Finally, the @samp{.nword} translating directive is supported
795 as well. It is documented in the section on Sparc machine
799 @section Floating Point
801 @cindex floating point, SPARC (@sc{ieee})
802 @cindex SPARC floating point (@sc{ieee})
803 The Sparc uses @sc{ieee} floating-point numbers.
805 @node Sparc-Directives
806 @section Sparc Machine Directives
808 @cindex SPARC machine directives
809 @cindex machine directives, SPARC
810 The Sparc version of @code{@value{AS}} supports the following additional
814 @cindex @code{align} directive, SPARC
816 This must be followed by the desired alignment in bytes.
818 @cindex @code{common} directive, SPARC
820 This must be followed by a symbol name, a positive number, and
821 @code{"bss"}. This behaves somewhat like @code{.comm}, but the
824 @cindex @code{half} directive, SPARC
826 This is functionally identical to @code{.short}.
828 @cindex @code{nword} directive, SPARC
830 On the Sparc, the @code{.nword} directive produces native word sized value,
831 ie. if assembling with -32 it is equivalent to @code{.word}, if assembling
832 with -64 it is equivalent to @code{.xword}.
834 @cindex @code{proc} directive, SPARC
836 This directive is ignored. Any text following it on the same
837 line is also ignored.
839 @cindex @code{register} directive, SPARC
841 This directive declares use of a global application or system register.
842 It must be followed by a register name %g2, %g3, %g6 or %g7, comma and
843 the symbol name for that register. If symbol name is @code{#scratch},
844 it is a scratch register, if it is @code{#ignore}, it just suppresses any
845 errors about using undeclared global register, but does not emit any
846 information about it into the object file. This can be useful e.g. if you
847 save the register before use and restore it after.
849 @cindex @code{reserve} directive, SPARC
851 This must be followed by a symbol name, a positive number, and
852 @code{"bss"}. This behaves somewhat like @code{.lcomm}, but the
855 @cindex @code{seg} directive, SPARC
857 This must be followed by @code{"text"}, @code{"data"}, or
858 @code{"data1"}. It behaves like @code{.text}, @code{.data}, or
861 @cindex @code{skip} directive, SPARC
863 This is functionally identical to the @code{.space} directive.
865 @cindex @code{word} directive, SPARC
867 On the Sparc, the @code{.word} directive produces 32 bit values,
868 instead of the 16 bit values it produces on many other machines.
870 @cindex @code{xword} directive, SPARC
872 On the Sparc V9 processor, the @code{.xword} directive produces