1 @c Copyright (C) 1991-2017 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter SPARC Dependent Features
10 @node Machine Dependencies
11 @chapter SPARC Dependent Features
16 * Sparc-Opts:: Options
17 * Sparc-Aligned-Data:: Option to enforce aligned data
18 * Sparc-Syntax:: Syntax
19 * Sparc-Float:: Floating Point
20 * Sparc-Directives:: Sparc Machine Directives
26 @cindex options for SPARC
28 @cindex architectures, SPARC
29 @cindex SPARC architectures
30 The SPARC chip family includes several successive versions, using the same
31 core instruction set, but including a few additional instructions at
32 each version. There are exceptions to this however. For details on what
33 instructions each variant supports, please see the chip's architecture
36 By default, @code{@value{AS}} assumes the core instruction set (SPARC
37 v6), but ``bumps'' the architecture level as needed: it switches to
38 successively higher architectures as it encounters instructions that
39 only exist in the higher levels.
41 If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump
42 past sparclite by default, an option must be passed to enable the
45 GAS treats sparclite as being compatible with v8, unless an architecture
46 is explicitly requested. SPARC v9 is always incompatible with sparclite.
48 @c The order here is the same as the order of enum sparc_opcode_arch_val
49 @c to give the user a sense of the order of the "bumping".
73 @item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite
74 @itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv | -Av8plusm
75 @itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m
76 @itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
77 @itemx -Asparcvis3 | -Asparcvis3r | -Asparc5
78 Use one of the @samp{-A} options to select one of the SPARC
79 architectures explicitly. If you select an architecture explicitly,
80 @code{@value{AS}} reports a fatal error if it encounters an instruction
81 or feature requiring an incompatible or higher level.
83 @samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc},
84 @samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment.
86 @samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d},
87 @samp{-Av9e}, @samp{-Av9v} and @samp{-Av9m} select a 64 bit
88 environment and are not available unless GAS is explicitly configured
89 with 64 bit environment support.
91 @samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with
92 UltraSPARC VIS 1.0 extensions.
94 @samp{-Av8plusb} and @samp{-Av9b} enable the UltraSPARC VIS 2.0 instructions,
95 as well as the instructions enabled by @samp{-Av8plusa} and @samp{-Av9a}.
97 @samp{-Av8plusc} and @samp{-Av9c} enable the UltraSPARC Niagara instructions,
98 as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}.
100 @samp{-Av8plusd} and @samp{-Av9d} enable the floating point fused
101 multiply-add, VIS 3.0, and HPC extension instructions, as well as the
102 instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}.
104 @samp{-Av8pluse} and @samp{-Av9e} enable the cryptographic
105 instructions, as well as the instructions enabled by @samp{-Av8plusd}
108 @samp{-Av8plusv} and @samp{-Av9v} enable floating point unfused
109 multiply-add, and integer multiply-add, as well as the instructions
110 enabled by @samp{-Av8pluse} and @samp{-Av9e}.
112 @samp{-Av8plusm} and @samp{-Av9m} enable the VIS 4.0, subtract extended,
113 xmpmul, xmontmul and xmontsqr instructions, as well as the instructions
114 enabled by @samp{-Av8plusv} and @samp{-Av9v}.
116 @samp{-Asparc} specifies a v9 environment. It is equivalent to
117 @samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise.
119 @samp{-Asparcvis} specifies a v9a environment. It is equivalent to
120 @samp{-Av9a} if the word size is 64-bit, and @samp{-Av8plusa} otherwise.
122 @samp{-Asparcvis2} specifies a v9b environment. It is equivalent to
123 @samp{-Av9b} if the word size is 64-bit, and @samp{-Av8plusb} otherwise.
125 @samp{-Asparcfmaf} specifies a v9b environment with the floating point
126 fused multiply-add instructions enabled.
128 @samp{-Asparcima} specifies a v9b environment with the integer
129 multiply-add instructions enabled.
131 @samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0,
132 HPC , and floating point fused multiply-add instructions enabled.
134 @samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0, HPC,
135 and floating point unfused multiply-add instructions enabled.
137 @samp{-Asparc5} is equivalent to @samp{-Av9m}.
139 @item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
140 @itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm | -xarch=v9 | -xarch=v9a
141 @itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v | -xarch=v9m
142 @itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
143 @itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
144 @itemx -xarch=sparcvis3r | -xarch=sparc5
145 For compatibility with the SunOS v9 assembler. These options are
146 equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
147 -Av8plusv, -Av8plusm, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9e, -Av9v, -Av9m,
148 -Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf, -Asparcima,
149 -Asparcvis3, and -Asparcvis3r, respectively.
152 Warn whenever it is necessary to switch to another level.
153 If an architecture level is explicitly requested, GAS will not issue
154 warnings until that level is reached, and will then bump the level
155 as required (except between incompatible levels).
158 Select the word size, either 32 bits or 64 bits.
159 These options are only available with the ELF object file format,
160 and require that the necessary BFD support has been included.
162 @item --dcti-couples-detect
163 Warn if a DCTI (delayed control transfer instruction) couple is found
164 when generating code for a variant of the SPARC architecture in which
165 the execution of the couple is unpredictable, or very slow. This is
169 @node Sparc-Aligned-Data
170 @section Enforcing aligned data
172 @cindex data alignment on SPARC
173 @cindex SPARC data alignment
174 SPARC GAS normally permits data to be misaligned. For example, it
175 permits the @code{.long} pseudo-op to be used on a byte boundary.
176 However, the native SunOS assemblers issue an error when they see
179 @kindex --enforce-aligned-data
180 You can use the @code{--enforce-aligned-data} option to make SPARC GAS
181 also issue an error about misaligned data, just as the SunOS
184 The @code{--enforce-aligned-data} option is not the default because gcc
185 issues misaligned data pseudo-ops when it initializes certain packed
186 data structures (structures defined using the @code{packed} attribute).
187 You may have to assemble with GAS in order to initialize packed data
188 structures in your own code.
191 @cindex syntax, SPARC
193 @section Sparc Syntax
194 The assembler syntax closely follows The Sparc Architecture Manual,
195 versions 8 and 9, as well as most extensions defined by Sun
196 for their UltraSPARC and Niagara line of processors.
199 * Sparc-Chars:: Special Characters
200 * Sparc-Regs:: Register Names
201 * Sparc-Constants:: Constant Names
202 * Sparc-Relocs:: Relocations
203 * Sparc-Size-Translations:: Size Translations
207 @subsection Special Characters
209 @cindex line comment character, Sparc
210 @cindex Sparc line comment character
211 A @samp{!} character appearing anywhere on a line indicates the start
212 of a comment that extends to the end of that line.
214 If a @samp{#} appears as the first character of a line then the whole
215 line is treated as a comment, but in this case the line could also be
216 a logical line number directive (@pxref{Comments}) or a preprocessor
217 control command (@pxref{Preprocessing}).
219 @cindex line separator, Sparc
220 @cindex statement separator, Sparc
221 @cindex Sparc line separator
222 @samp{;} can be used instead of a newline to separate statements.
225 @subsection Register Names
226 @cindex Sparc registers
227 @cindex register names, Sparc
229 The Sparc integer register file is broken down into global,
230 outgoing, local, and incoming.
234 The 8 global registers are referred to as @samp{%g@var{n}}.
237 The 8 outgoing registers are referred to as @samp{%o@var{n}}.
240 The 8 local registers are referred to as @samp{%l@var{n}}.
243 The 8 incoming registers are referred to as @samp{%i@var{n}}.
246 The frame pointer register @samp{%i6} can be referenced using
247 the alias @samp{%fp}.
250 The stack pointer register @samp{%o6} can be referenced using
251 the alias @samp{%sp}.
254 Floating point registers are simply referred to as @samp{%f@var{n}}.
255 When assembling for pre-V9, only 32 floating point registers
256 are available. For V9 and later there are 64, but there are
257 restrictions when referencing the upper 32 registers. They
258 can only be accessed as double or quad, and thus only even
259 or quad numbered accesses are allowed. For example, @samp{%f34}
260 is a legal floating point register, but @samp{%f35} is not.
262 Floating point registers accessed as double can also be referred using
263 the @samp{%d@var{n}} notation, where @var{n} is even. Similarly,
264 floating point registers accessed as quad can be referred using the
265 @samp{%q@var{n}} notation, where @var{n} is a multiple of 4. For
266 example, @samp{%f4} can be denoted as both @samp{%d4} and @samp{%q4}.
267 On the other hand, @samp{%f2} can be denoted as @samp{%d2} but not as
270 Certain V9 instructions allow access to ancillary state registers.
271 Most simply they can be referred to as @samp{%asr@var{n}} where
272 @var{n} can be from 16 to 31. However, there are some aliases
273 defined to reference ASR registers defined for various UltraSPARC
278 The tick compare register is referred to as @samp{%tick_cmpr}.
281 The system tick register is referred to as @samp{%stick}. An alias,
282 @samp{%sys_tick}, exists but is deprecated and should not be used
286 The system tick compare register is referred to as @samp{%stick_cmpr}.
287 An alias, @samp{%sys_tick_cmpr}, exists but is deprecated and should
288 not be used by new software.
291 The software interrupt register is referred to as @samp{%softint}.
294 The set software interrupt register is referred to as @samp{%set_softint}.
295 The mnemonic @samp{%softint_set} is provided as an alias.
298 The clear software interrupt register is referred to as
299 @samp{%clear_softint}. The mnemonic @samp{%softint_clear} is provided
303 The performance instrumentation counters register is referred to as
307 The performance control register is referred to as @samp{%pcr}.
310 The graphics status register is referred to as @samp{%gsr}.
313 The V9 dispatch control register is referred to as @samp{%dcr}.
316 Various V9 branch and conditional move instructions allow
317 specification of which set of integer condition codes to
318 test. These are referred to as @samp{%xcc} and @samp{%icc}.
320 Additionally, GAS supports the so-called ``natural'' condition codes;
321 these are referred to as @samp{%ncc} and reference to @samp{%icc} if
322 the word size is 32, @samp{%xcc} if the word size is 64.
324 In V9, there are 4 sets of floating point condition codes
325 which are referred to as @samp{%fcc@var{n}}.
327 Several special privileged and non-privileged registers
332 The V9 address space identifier register is referred to as @samp{%asi}.
335 The V9 restorable windows register is referred to as @samp{%canrestore}.
338 The V9 savable windows register is referred to as @samp{%cansave}.
341 The V9 clean windows register is referred to as @samp{%cleanwin}.
344 The V9 current window pointer register is referred to as @samp{%cwp}.
347 The floating-point queue register is referred to as @samp{%fq}.
350 The V8 co-processor queue register is referred to as @samp{%cq}.
353 The floating point status register is referred to as @samp{%fsr}.
356 The other windows register is referred to as @samp{%otherwin}.
359 The V9 program counter register is referred to as @samp{%pc}.
362 The V9 next program counter register is referred to as @samp{%npc}.
365 The V9 processor interrupt level register is referred to as @samp{%pil}.
368 The V9 processor state register is referred to as @samp{%pstate}.
371 The trap base address register is referred to as @samp{%tba}.
374 The V9 tick register is referred to as @samp{%tick}.
377 The V9 trap level is referred to as @samp{%tl}.
380 The V9 trap program counter is referred to as @samp{%tpc}.
383 The V9 trap next program counter is referred to as @samp{%tnpc}.
386 The V9 trap state is referred to as @samp{%tstate}.
389 The V9 trap type is referred to as @samp{%tt}.
392 The V9 condition codes is referred to as @samp{%ccr}.
395 The V9 floating-point registers state is referred to as @samp{%fprs}.
398 The V9 version register is referred to as @samp{%ver}.
401 The V9 window state register is referred to as @samp{%wstate}.
404 The Y register is referred to as @samp{%y}.
407 The V8 window invalid mask register is referred to as @samp{%wim}.
410 The V8 processor state register is referred to as @samp{%psr}.
413 The V9 global register level register is referred to as @samp{%gl}.
416 Several special register names exist for hypervisor mode code:
420 The hyperprivileged processor state register is referred to as
424 The hyperprivileged trap state register is referred to as @samp{%htstate}.
427 The hyperprivileged interrupt pending register is referred to as
431 The hyperprivileged trap base address register is referred to as
435 The hyperprivileged implementation version register is referred
439 The hyperprivileged system tick offset register is referred to as
440 @samp{%hstick_offset}. Note that there is no @samp{%hstick} register,
441 the normal @samp{%stick} is used.
444 The hyperprivileged system tick enable register is referred to as
445 @samp{%hstick_enable}.
448 The hyperprivileged system tick compare register is referred
449 to as @samp{%hstick_cmpr}.
452 @node Sparc-Constants
453 @subsection Constants
454 @cindex Sparc constants
455 @cindex constants, Sparc
457 Several Sparc instructions take an immediate operand field for
458 which mnemonic names exist. Two such examples are @samp{membar}
459 and @samp{prefetch}. Another example are the set of V9
460 memory access instruction that allow specification of an
461 address space identifier.
463 The @samp{membar} instruction specifies a memory barrier that is
464 the defined by the operand which is a bitmask. The supported
469 @samp{#Sync} requests that all operations (including nonmemory
470 reference operations) appearing prior to the @code{membar} must have
471 been performed and the effects of any exceptions become visible before
472 any instructions after the @code{membar} may be initiated. This
473 corresponds to @code{membar} cmask field bit 2.
476 @samp{#MemIssue} requests that all memory reference operations
477 appearing prior to the @code{membar} must have been performed before
478 any memory operation after the @code{membar} may be initiated. This
479 corresponds to @code{membar} cmask field bit 1.
482 @samp{#Lookaside} requests that a store appearing prior to the
483 @code{membar} must complete before any load following the
484 @code{membar} referencing the same address can be initiated. This
485 corresponds to @code{membar} cmask field bit 0.
488 @samp{#StoreStore} defines that the effects of all stores appearing
489 prior to the @code{membar} instruction must be visible to all
490 processors before the effect of any stores following the
491 @code{membar}. Equivalent to the deprecated @code{stbar} instruction.
492 This corresponds to @code{membar} mmask field bit 3.
495 @samp{#LoadStore} defines all loads appearing prior to the
496 @code{membar} instruction must have been performed before the effect
497 of any stores following the @code{membar} is visible to any other
498 processor. This corresponds to @code{membar} mmask field bit 2.
501 @samp{#StoreLoad} defines that the effects of all stores appearing
502 prior to the @code{membar} instruction must be visible to all
503 processors before loads following the @code{membar} may be performed.
504 This corresponds to @code{membar} mmask field bit 1.
507 @samp{#LoadLoad} defines that all loads appearing prior to the
508 @code{membar} instruction must have been performed before any loads
509 following the @code{membar} may be performed. This corresponds to
510 @code{membar} mmask field bit 0.
514 These values can be ored together, for example:
518 membar #StoreLoad | #LoadLoad
519 membar #StoreLoad | #StoreStore
522 The @code{prefetch} and @code{prefetcha} instructions take a prefetch
523 function code. The following prefetch function code constant
524 mnemonics are available:
528 @samp{#n_reads} requests a prefetch for several reads, and corresponds
529 to a prefetch function code of 0.
531 @samp{#one_read} requests a prefetch for one read, and corresponds
532 to a prefetch function code of 1.
534 @samp{#n_writes} requests a prefetch for several writes (and possibly
535 reads), and corresponds to a prefetch function code of 2.
537 @samp{#one_write} requests a prefetch for one write, and corresponds
538 to a prefetch function code of 3.
540 @samp{#page} requests a prefetch page, and corresponds to a prefetch
543 @samp{#invalidate} requests a prefetch invalidate, and corresponds to
544 a prefetch function code of 16.
546 @samp{#unified} requests a prefetch to the nearest unified cache, and
547 corresponds to a prefetch function code of 17.
549 @samp{#n_reads_strong} requests a strong prefetch for several reads,
550 and corresponds to a prefetch function code of 20.
552 @samp{#one_read_strong} requests a strong prefetch for one read,
553 and corresponds to a prefetch function code of 21.
555 @samp{#n_writes_strong} requests a strong prefetch for several writes,
556 and corresponds to a prefetch function code of 22.
558 @samp{#one_write_strong} requests a strong prefetch for one write,
559 and corresponds to a prefetch function code of 23.
561 Onle one prefetch code may be specified. Here are some examples:
564 prefetch [%l0 + %l2], #one_read
565 prefetch [%g2 + 8], #n_writes
566 prefetcha [%g1] 0x8, #unified
567 prefetcha [%o0 + 0x10] %asi, #n_reads
570 The actual behavior of a given prefetch function code is processor
571 specific. If a processor does not implement a given prefetch
572 function code, it will treat the prefetch instruction as a nop.
574 For instructions that accept an immediate address space identifier,
575 @code{@value{AS}} provides many mnemonics corresponding to
576 V9 defined as well as UltraSPARC and Niagara extended values.
577 For example, @samp{#ASI_P} and @samp{#ASI_BLK_INIT_QUAD_LDD_AIUS}.
578 See the V9 and processor specific manuals for details.
583 @subsection Relocations
584 @cindex Sparc relocations
585 @cindex relocations, Sparc
587 ELF relocations are available as defined in the 32-bit and 64-bit
588 Sparc ELF specifications.
590 @code{R_SPARC_HI22} is obtained using @samp{%hi} and @code{R_SPARC_LO10}
591 is obtained using @samp{%lo}. Likewise @code{R_SPARC_HIX22} is
592 obtained from @samp{%hix} and @code{R_SPARC_LOX10} is obtained
593 using @samp{%lox}. For example:
596 sethi %hi(symbol), %g1
597 or %g1, %lo(symbol), %g1
599 sethi %hix(symbol), %g1
600 xor %g1, %lox(symbol), %g1
603 These ``high'' mnemonics extract bits 31:10 of their operand,
604 and the ``low'' mnemonics extract bits 9:0 of their operand.
606 V9 code model relocations can be requested as follows:
610 @code{R_SPARC_HH22} is requested using @samp{%hh}. It can
611 also be generated using @samp{%uhi}.
613 @code{R_SPARC_HM10} is requested using @samp{%hm}. It can
614 also be generated using @samp{%ulo}.
616 @code{R_SPARC_LM22} is requested using @samp{%lm}.
619 @code{R_SPARC_H44} is requested using @samp{%h44}.
621 @code{R_SPARC_M44} is requested using @samp{%m44}.
623 @code{R_SPARC_L44} is requested using @samp{%l44} or @samp{%l34}.
625 @code{R_SPARC_H34} is requested using @samp{%h34}.
628 The @samp{%l34} generates a @code{R_SPARC_L44} relocation because it
629 calculates the necessary value, and therefore no explicit
630 @code{R_SPARC_L34} relocation needed to be created for this purpose.
632 The @samp{%h34} and @samp{%l34} relocations are used for the abs34 code
633 model. Here is an example abs34 address generation sequence:
636 sethi %h34(symbol), %g1
638 or %g1, %l34(symbol), %g1
641 The PC relative relocation @code{R_SPARC_PC22} can be obtained by
642 enclosing an operand inside of @samp{%pc22}. Likewise, the
643 @code{R_SPARC_PC10} relocation can be obtained using @samp{%pc10}.
644 These are mostly used when assembling PIC code. For example, the
645 standard PIC sequence on Sparc to get the base of the global offset
646 table, PC relative, into a register, can be performed as:
649 sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
650 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
653 Several relocations exist to allow the link editor to potentially
654 optimize GOT data references. The @code{R_SPARC_GOTDATA_OP_HIX22}
655 relocation can obtained by enclosing an operand inside of
656 @samp{%gdop_hix22}. The @code{R_SPARC_GOTDATA_OP_LOX10}
657 relocation can obtained by enclosing an operand inside of
658 @samp{%gdop_lox10}. Likewise, @code{R_SPARC_GOTDATA_OP} can be
659 obtained by enclosing an operand inside of @samp{%gdop}.
660 For example, assuming the GOT base is in register @code{%l7}:
663 sethi %gdop_hix22(symbol), %l1
664 xor %l1, %gdop_lox10(symbol), %l1
665 ld [%l7 + %l1], %l2, %gdop(symbol)
668 There are many relocations that can be requested for access to
669 thread local storage variables. All of the Sparc TLS mnemonics
674 @code{R_SPARC_TLS_GD_HI22} is requested using @samp{%tgd_hi22}.
676 @code{R_SPARC_TLS_GD_LO10} is requested using @samp{%tgd_lo10}.
678 @code{R_SPARC_TLS_GD_ADD} is requested using @samp{%tgd_add}.
680 @code{R_SPARC_TLS_GD_CALL} is requested using @samp{%tgd_call}.
683 @code{R_SPARC_TLS_LDM_HI22} is requested using @samp{%tldm_hi22}.
685 @code{R_SPARC_TLS_LDM_LO10} is requested using @samp{%tldm_lo10}.
687 @code{R_SPARC_TLS_LDM_ADD} is requested using @samp{%tldm_add}.
689 @code{R_SPARC_TLS_LDM_CALL} is requested using @samp{%tldm_call}.
692 @code{R_SPARC_TLS_LDO_HIX22} is requested using @samp{%tldo_hix22}.
694 @code{R_SPARC_TLS_LDO_LOX10} is requested using @samp{%tldo_lox10}.
696 @code{R_SPARC_TLS_LDO_ADD} is requested using @samp{%tldo_add}.
699 @code{R_SPARC_TLS_IE_HI22} is requested using @samp{%tie_hi22}.
701 @code{R_SPARC_TLS_IE_LO10} is requested using @samp{%tie_lo10}.
703 @code{R_SPARC_TLS_IE_LD} is requested using @samp{%tie_ld}.
705 @code{R_SPARC_TLS_IE_LDX} is requested using @samp{%tie_ldx}.
707 @code{R_SPARC_TLS_IE_ADD} is requested using @samp{%tie_add}.
710 @code{R_SPARC_TLS_LE_HIX22} is requested using @samp{%tle_hix22}.
712 @code{R_SPARC_TLS_LE_LOX10} is requested using @samp{%tle_lox10}.
715 Here are some example TLS model sequences.
717 First, General Dynamic:
720 sethi %tgd_hi22(symbol), %l1
721 add %l1, %tgd_lo10(symbol), %l1
722 add %l7, %l1, %o0, %tgd_add(symbol)
723 call __tls_get_addr, %tgd_call(symbol)
730 sethi %tldm_hi22(symbol), %l1
731 add %l1, %tldm_lo10(symbol), %l1
732 add %l7, %l1, %o0, %tldm_add(symbol)
733 call __tls_get_addr, %tldm_call(symbol)
736 sethi %tldo_hix22(symbol), %l1
737 xor %l1, %tldo_lox10(symbol), %l1
738 add %o0, %l1, %l1, %tldo_add(symbol)
744 sethi %tie_hi22(symbol), %l1
745 add %l1, %tie_lo10(symbol), %l1
746 ld [%l7 + %l1], %o0, %tie_ld(symbol)
747 add %g7, %o0, %o0, %tie_add(symbol)
749 sethi %tie_hi22(symbol), %l1
750 add %l1, %tie_lo10(symbol), %l1
751 ldx [%l7 + %l1], %o0, %tie_ldx(symbol)
752 add %g7, %o0, %o0, %tie_add(symbol)
755 And finally, Local Exec:
758 sethi %tle_hix22(symbol), %l1
759 add %l1, %tle_lox10(symbol), %l1
763 When assembling for 64-bit, and a secondary constant addend is
764 specified in an address expression that would normally generate
765 an @code{R_SPARC_LO10} relocation, the assembler will emit an
766 @code{R_SPARC_OLO10} instead.
768 @node Sparc-Size-Translations
769 @subsection Size Translations
770 @cindex Sparc size translations
771 @cindex size, translations, Sparc
773 Often it is desirable to write code in an operand size agnostic
774 manner. @code{@value{AS}} provides support for this via
775 operand size opcode translations. Translations are supported
776 for loads, stores, shifts, compare-and-swap atomics, and the
777 @samp{clr} synthetic instruction.
779 If generating 32-bit code, @code{@value{AS}} will generate the
780 32-bit opcode. Whereas if 64-bit code is being generated,
781 the 64-bit opcode will be emitted. For example @code{ldn}
782 will be transformed into @code{ld} for 32-bit code and
783 @code{ldx} for 64-bit code.
785 Here is an example meant to demonstrate all the supported
797 casna [%o0] %asi, %o1, %o2
801 In 32-bit mode @code{@value{AS}} will emit:
812 casa [%o0] %asi, %o1, %o2
816 And in 64-bit mode @code{@value{AS}} will emit:
827 casxa [%o0] %asi, %o1, %o2
831 Finally, the @samp{.nword} translating directive is supported
832 as well. It is documented in the section on Sparc machine
836 @section Floating Point
838 @cindex floating point, SPARC (@sc{ieee})
839 @cindex SPARC floating point (@sc{ieee})
840 The Sparc uses @sc{ieee} floating-point numbers.
842 @node Sparc-Directives
843 @section Sparc Machine Directives
845 @cindex SPARC machine directives
846 @cindex machine directives, SPARC
847 The Sparc version of @code{@value{AS}} supports the following additional
851 @cindex @code{align} directive, SPARC
853 This must be followed by the desired alignment in bytes.
855 @cindex @code{common} directive, SPARC
857 This must be followed by a symbol name, a positive number, and
858 @code{"bss"}. This behaves somewhat like @code{.comm}, but the
861 @cindex @code{half} directive, SPARC
863 This is functionally identical to @code{.short}.
865 @cindex @code{nword} directive, SPARC
867 On the Sparc, the @code{.nword} directive produces native word sized value,
868 ie. if assembling with -32 it is equivalent to @code{.word}, if assembling
869 with -64 it is equivalent to @code{.xword}.
871 @cindex @code{proc} directive, SPARC
873 This directive is ignored. Any text following it on the same
874 line is also ignored.
876 @cindex @code{register} directive, SPARC
878 This directive declares use of a global application or system register.
879 It must be followed by a register name %g2, %g3, %g6 or %g7, comma and
880 the symbol name for that register. If symbol name is @code{#scratch},
881 it is a scratch register, if it is @code{#ignore}, it just suppresses any
882 errors about using undeclared global register, but does not emit any
883 information about it into the object file. This can be useful e.g. if you
884 save the register before use and restore it after.
886 @cindex @code{reserve} directive, SPARC
888 This must be followed by a symbol name, a positive number, and
889 @code{"bss"}. This behaves somewhat like @code{.lcomm}, but the
892 @cindex @code{seg} directive, SPARC
894 This must be followed by @code{"text"}, @code{"data"}, or
895 @code{"data1"}. It behaves like @code{.text}, @code{.data}, or
898 @cindex @code{skip} directive, SPARC
900 This is functionally identical to the @code{.space} directive.
902 @cindex @code{word} directive, SPARC
904 On the Sparc, the @code{.word} directive produces 32 bit values,
905 instead of the 16 bit values it produces on many other machines.
907 @cindex @code{xword} directive, SPARC
909 On the Sparc V9 processor, the @code{.xword} directive produces