1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2002
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
8 @chapter SPARC Dependent Features
11 @node Machine Dependencies
12 @chapter SPARC Dependent Features
17 * Sparc-Opts:: Options
18 * Sparc-Aligned-Data:: Option to enforce aligned data
19 * Sparc-Syntax:: Syntax
20 * Sparc-Float:: Floating Point
21 * Sparc-Directives:: Sparc Machine Directives
27 @cindex options for SPARC
29 @cindex architectures, SPARC
30 @cindex SPARC architectures
31 The SPARC chip family includes several successive levels, using the same
32 core instruction set, but including a few additional instructions at
33 each level. There are exceptions to this however. For details on what
34 instructions each variant supports, please see the chip's architecture
37 By default, @code{@value{AS}} assumes the core instruction set (SPARC
38 v6), but ``bumps'' the architecture level as needed: it switches to
39 successively higher architectures as it encounters instructions that
40 only exist in the higher levels.
42 If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump
43 passed sparclite by default, an option must be passed to enable the
46 GAS treats sparclite as being compatible with v8, unless an architecture
47 is explicitly requested. SPARC v9 is always incompatible with sparclite.
49 @c The order here is the same as the order of enum sparc_opcode_arch_val
50 @c to give the user a sense of the order of the "bumping".
60 @item -Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
61 @itemx -Av8plus | -Av8plusa | -Av9 | -Av9a
62 Use one of the @samp{-A} options to select one of the SPARC
63 architectures explicitly. If you select an architecture explicitly,
64 @code{@value{AS}} reports a fatal error if it encounters an instruction
65 or feature requiring an incompatible or higher level.
67 @samp{-Av8plus} and @samp{-Av8plusa} select a 32 bit environment.
69 @samp{-Av9} and @samp{-Av9a} select a 64 bit environment and are not
70 available unless GAS is explicitly configured with 64 bit environment
73 @samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with
74 UltraSPARC extensions.
76 @item -xarch=v8plus | -xarch=v8plusa
77 For compatibility with the Solaris v9 assembler. These options are
78 equivalent to -Av8plus and -Av8plusa, respectively.
81 Warn whenever it is necessary to switch to another level.
82 If an architecture level is explicitly requested, GAS will not issue
83 warnings until that level is reached, and will then bump the level
84 as required (except between incompatible levels).
87 Select the word size, either 32 bits or 64 bits.
88 These options are only available with the ELF object file format,
89 and require that the necessary BFD support has been included.
92 @node Sparc-Aligned-Data
93 @section Enforcing aligned data
95 @cindex data alignment on SPARC
96 @cindex SPARC data alignment
97 SPARC GAS normally permits data to be misaligned. For example, it
98 permits the @code{.long} pseudo-op to be used on a byte boundary.
99 However, the native SunOS and Solaris assemblers issue an error when
100 they see misaligned data.
102 @kindex --enforce-aligned-data
103 You can use the @code{--enforce-aligned-data} option to make SPARC GAS
104 also issue an error about misaligned data, just as the SunOS and Solaris
107 The @code{--enforce-aligned-data} option is not the default because gcc
108 issues misaligned data pseudo-ops when it initializes certain packed
109 data structures (structures defined using the @code{packed} attribute).
110 You may have to assemble with GAS in order to initialize packed data
111 structures in your own code.
114 @cindex syntax, SPARC
116 @section Sparc Syntax
117 The assembler syntax closely follows The Sparc Architecture Manual,
118 versions 8 and 9, as well as most extensions defined by Sun
119 for their UltraSPARC and Niagara line of processors.
122 * Sparc-Chars:: Special Characters
123 * Sparc-Regs:: Register Names
124 * Sparc-Relocs:: Relocations
128 @subsection Special Characters
130 @cindex line comment character, Sparc
131 @cindex Sparc line comment character
132 @samp{#} is the line comment character.
134 @cindex line separator, Sparc
135 @cindex statement separator, Sparc
136 @cindex Sparc line separator
137 @samp{;} can be used instead of a newline to separate statements.
140 @subsection Register Names
141 @cindex Sparc registers
142 @cindex register names, Sparc
144 The Sparc integer register file is broken down into global,
145 outgoing, local, and incoming.
149 The 8 global registers are referred to as @samp{%g@var{n}}.
152 The 8 outgoing registers are referred to as @samp{%o@var{n}}.
155 The 8 local registers are referred to as @samp{%l@var{n}}.
158 The 8 incoming registers are referred to as @samp{%i@var{n}}.
161 The frame pointer register @samp{%i6} can be referenced using
162 the alias @samp{%fp}.
165 The stack pointer register @samp{%o6} can be referenced using
166 the alias @samp{%sp}.
169 Floating point registers are simply referred to as @samp{%f@var{n}}.
170 When assembling for pre-V9, only 32 floating point registers
171 are available. For V9 and later there are 64, but there are
172 restrictions when referencing the upper 32 registers. They
173 can only be accessed as double or quad, and thus only even
174 or quad numbered accesses are allowed. For example, @samp{%f34}
175 is a legal floating point register, but @samp{%f35} is not.
177 Certain V9 instructions allow access to ancillary state registers.
178 Most simply they can be referred to as @samp{%asr@var{n}} where
179 @var{n} can be from 16 to 31. However, there are some aliased
180 defined to reference ASR registers defined for various UltraSPARC
185 The tick compare register is referred to as @samp{%tick_cmpr}.
188 The system tick register is referred to as @samp{%sys_tick}.
191 The system tick compare register is referred to as @samp{%sys_tick_cmpr}.
194 The software interrupt register is referred to as @samp{%softint}.
197 The set software interrupt register is referred to as @samp{%set_softint}.
200 The clear software interrupt register is referred to as
201 @samp{%clear_softint}.
204 The performance instrumentation counters register is referred to as
208 The performance control register is referred to as @samp{%pcr}.
211 The graphics status register is referred to as @samp{%gsr}.
214 The dispatch control register is referred to as @samp{%dcr}.
217 Various V9 branch and conditional move instructions allow
218 specification of which set of integer condition codes to
219 test. These are referred to as @samp{%xcc} and @samp{%icc}.
221 In V9, there are 4 sets of floating point condition codes
222 which are referred to as @samp{%fcc@var{n}}.
224 Several special privileged and non-privileged registers
229 The V9 address space identifier register is referred to as @samp{%asi}.
232 The V9 restorable windows register is referred to as @samp{%canrestore}.
235 The V9 savable windows register is referred to as @samp{%cansave}.
238 The V9 clean windows register is referred to as @samp{%cleanwin}.
241 The V9 current window pointer register is referred to as @samp{%cwp}.
244 The floating-point queue register is referred to as @samp{%fq}.
247 The co-processor queue register is referred to as @samp{%cq}.
250 The floating point status register is referred to as @samp{%fsr}.
253 The other windows register is referred to as @samp{%otherwin}.
256 The V9 program counter register is referred to as @samp{%pc}.
259 The V9 next program counter register is referred to as @samp{%npc}.
262 The V9 processor interrupt level register is referred to as @samp{%pil}.
265 The V9 processor state register is referred to as @samp{%pstate}.
268 The trap base address register is referred to as @samp{%tba}.
271 The V9 tick register is referred to as @samp{%tick}.
274 The V9 trap level is referred to as @samp{%tl}.
277 The V9 trap program counter is referred to as @samp{%tpc}.
280 The V9 trap next program counter is referred to as @samp{%tnpc}.
283 The V9 trap state is referred to as @samp{%tstate}.
286 The V9 trap type is referred to as @samp{%tt}.
289 The V9 condition codes is referred to as @samp{%ccr}.
292 The V9 floating-point registers state is referred to as @samp{%fprs}.
295 The V9 version register is referred to as @samp{%ver}.
298 The V9 window state register is referred to as @samp{%wstate}.
301 The Y register is referred to as @samp{%y}.
304 The V8 window invalid mask register is referred to as @samp{%wim}.
307 The V8 processor state register is referred to as @samp{%psr}.
310 The global register level register is referred to as @samp{%gl}.
313 Several special register names exist for hypervisor mode code:
317 The hyperprivileged processor state register is referred to as
321 The hyperprivileged trap state register is referred to as @samp{%htstate}.
324 The hyperprivileged interrupt pending register is referred to as
328 The hyperprivileged trap base address register is referred to as
332 The hyperprivileged implementation version register is referred
336 The hyperprivileged system tick compare register is referred
337 to as @samp{%hstick_cmpr}.
341 @subsection Relocations
342 @cindex Sparc relocations
343 @cindex relocations, Sparc
345 ELF relocations are available as defined in the 32-bit and 64-bit
346 Sparc ELF specifications.
348 @code{R_SPARC_HI22} is obtained using @samp{%hi} and @code{R_SPARC_LO10}
349 is obtained using @samp{%lo}. Likewise @code{R_SPARC_HIX22} is
350 obtained from @samp{%hix} and @code{R_SPARC_LOX10} is obtained
351 using @samp{%lox}. For example:
354 sethi %hi(symbol), %g1
355 or %g1, %lo(symbol), %g1
357 sethi %hix(symbol), %g1
358 xor %g1, %lox(symbol), %g1
361 These ``high'' mnemonics extract bits 31:10 of their operand,
362 and the ``low'' mnemonics extract bits 9:0 of their operand.
364 V9 code model relocations can be requested as follows:
368 @code{R_SPARC_HH22} is requested using @samp{%hh}. It can
369 also be generated using @samp{%uhi}.
371 @code{R_SPARC_HM10} is requested using @samp{%hm}. It can
372 also be generated using @samp{%ulo}.
374 @code{R_SPARC_LM22} is requested using @samp{%lm}.
377 @code{R_SPARC_H44} is requested using @samp{%h44}.
379 @code{R_SPARC_M44} is requested using @samp{%m44}.
381 @code{R_SPARC_L44} is requested using @samp{%l44}.
384 The PC relative relocation @code{R_SPARC_PC22} can be obtained by
385 enclosing an operand inside of @samp{%pc22}. Likewise, the
386 @code{R_SPARC_PC10} relocation can be obtained using @samp{%pc10}.
387 These are mostly used when assembling PIC code. For example, the
388 standard PIC sequence on Sparc to get the base of the global offset
389 table, PC relative, into a register, can be performed as:
392 sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
393 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
396 Several relocations exist to allow the link editor to potentially
397 optimize GOT data references. The @code{R_SPARC_GOTDATA_OP_HIX22}
398 relocation can obtained by enclosing an operand inside of
399 @samp{%gdop_hix22}. The @code{R_SPARC_GOTDATA_OP_LOX10}
400 relocation can obtained by enclosing an operand inside of
401 @samp{%gdop_lox10}. Likewise, @code{R_SPARC_GOTDATA_OP} can be
402 obtained by enclosing an operand inside of @samp{%gdop}.
403 For example, assuming the GOT base is in register @code{%l7}:
406 sethi %gdop_hix22(symbol), %l1
407 xor %l1, %gdop_lox10(symbol), %l1
408 ld [%l7 + %l1], %l2, %gdop(symbol)
411 There are many relocations that can be requested for access to
412 thread local storage variables. All of the Sparc TLS mnemonics
417 @code{R_SPARC_TLS_GD_HI22} is requested using @samp{%tgd_hi22}.
419 @code{R_SPARC_TLS_GD_LO10} is requested using @samp{%tgd_lo10}.
421 @code{R_SPARC_TLS_GD_ADD} is requested using @samp{%tgd_add}.
423 @code{R_SPARC_TLS_GD_CALL} is requested using @samp{%tgd_call}.
426 @code{R_SPARC_TLS_LDM_HI22} is requested using @samp{%tldm_hi22}.
428 @code{R_SPARC_TLS_LDM_LO10} is requested using @samp{%tldm_lo10}.
430 @code{R_SPARC_TLS_LDM_ADD} is requested using @samp{%tldm_add}.
432 @code{R_SPARC_TLS_LDM_CALL} is requested using @samp{%tldm_call}.
435 @code{R_SPARC_TLS_LDO_HIX22} is requested using @samp{%tldo_hix22}.
437 @code{R_SPARC_TLS_LDO_LOX10} is requested using @samp{%tldo_lox10}.
439 @code{R_SPARC_TLS_LDO_ADD} is requested using @samp{%tldo_add}.
442 @code{R_SPARC_TLS_IE_HI22} is requested using @samp{%tie_hi22}.
444 @code{R_SPARC_TLS_IE_LO10} is requested using @samp{%tie_lo10}.
446 @code{R_SPARC_TLS_IE_LD} is requested using @samp{%tie_ld}.
448 @code{R_SPARC_TLS_IE_LDX} is requested using @samp{%tie_ldx}.
450 @code{R_SPARC_TLS_IE_ADD} is requested using @samp{%tie_add}.
453 @code{R_SPARC_TLS_LE_HIX22} is requested using @samp{%tle_hix22}.
455 @code{R_SPARC_TLS_LE_LOX10} is requested using @samp{%tle_lox10}.
458 Here are some example TLS model sequences.
460 First, General Dynamic:
463 sethi %tgd_hi22(symbol), %l1
464 add %l1, %tgd_lo10(symbol), %l1
465 add %l7, %l1, %o0, %tgd_add(symbol)
466 call __tls_get_addr, %tgd_call(symbol)
473 sethi %tldm_hi22(symbol), %l1
474 add %l1, %tldm_lo10(symbol), %l1
475 add %l7, %l1, %o0, %tldm_add(symbol)
476 call __tls_get_addr, %tldm_call(symbol)
479 sethi %tldo_hix22(symbol), %l1
480 xor %l1, %tldo_lox10(symbol), %l1
481 add %o0, %l1, %l1, %tldo_add(symbol)
487 sethi %tie_hi22(symbol), %l1
488 add %l1, %tie_lo10(symbol), %l1
489 ld [%l7 + %l1], %o0, %tie_ld(symbol)
490 add %g7, %o0, %o0, %tie_add(symbol)
492 sethi %tie_hi22(symbol), %l1
493 add %l1, %tie_lo10(symbol), %l1
494 ldx [%l7 + %l1], %o0, %tie_ldx(symbol)
495 add %g7, %o0, %o0, %tie_add(symbol)
498 And finally, Local Exec:
501 sethi %tle_hix22(symbol), %l1
502 add %l1, %tle_lox10(symbol), %l1
506 When assembling for 64-bit, and a secondary constant addend is
507 specified in an address expression that would normally generate
508 an @code{R_SPARC_LO10} relocation, the assembler will emit an
509 @code{R_SPARC_OLO10} instead.
512 @section Floating Point
514 @cindex floating point, SPARC (@sc{ieee})
515 @cindex SPARC floating point (@sc{ieee})
516 The Sparc uses @sc{ieee} floating-point numbers.
518 @node Sparc-Directives
519 @section Sparc Machine Directives
521 @cindex SPARC machine directives
522 @cindex machine directives, SPARC
523 The Sparc version of @code{@value{AS}} supports the following additional
527 @cindex @code{align} directive, SPARC
529 This must be followed by the desired alignment in bytes.
531 @cindex @code{common} directive, SPARC
533 This must be followed by a symbol name, a positive number, and
534 @code{"bss"}. This behaves somewhat like @code{.comm}, but the
537 @cindex @code{half} directive, SPARC
539 This is functionally identical to @code{.short}.
541 @cindex @code{nword} directive, SPARC
543 On the Sparc, the @code{.nword} directive produces native word sized value,
544 ie. if assembling with -32 it is equivalent to @code{.word}, if assembling
545 with -64 it is equivalent to @code{.xword}.
547 @cindex @code{proc} directive, SPARC
549 This directive is ignored. Any text following it on the same
550 line is also ignored.
552 @cindex @code{register} directive, SPARC
554 This directive declares use of a global application or system register.
555 It must be followed by a register name %g2, %g3, %g6 or %g7, comma and
556 the symbol name for that register. If symbol name is @code{#scratch},
557 it is a scratch register, if it is @code{#ignore}, it just suppresses any
558 errors about using undeclared global register, but does not emit any
559 information about it into the object file. This can be useful e.g. if you
560 save the register before use and restore it after.
562 @cindex @code{reserve} directive, SPARC
564 This must be followed by a symbol name, a positive number, and
565 @code{"bss"}. This behaves somewhat like @code{.lcomm}, but the
568 @cindex @code{seg} directive, SPARC
570 This must be followed by @code{"text"}, @code{"data"}, or
571 @code{"data1"}. It behaves like @code{.text}, @code{.data}, or
574 @cindex @code{skip} directive, SPARC
576 This is functionally identical to the @code{.space} directive.
578 @cindex @code{word} directive, SPARC
580 On the Sparc, the @code{.word} directive produces 32 bit values,
581 instead of the 16 bit values it produces on many other machines.
583 @cindex @code{xword} directive, SPARC
585 On the Sparc V9 processor, the @code{.xword} directive produces