1 @c Copyright (C) 1997, 1998 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
6 @chapter v850 Dependent Features
10 * V850 Options:: Options
11 * V850 Syntax:: Syntax
12 * V850 Floating Point:: Floating Point
13 * V850 Directives:: V850 Machine Directives
14 * V850 Opcodes:: Opcodes
19 @cindex V850 options (none)
20 @cindex options for V850 (none)
21 @code{@value{AS}} supports the following additional command-line options
22 for the V850 processor family:
24 @cindex command line options, V850
25 @cindex V850 command line options
28 @cindex @code{-wsigned_overflow} command line option, V850
29 @item -wsigned_overflow
30 Causes warnings to be produced when signed immediate values overflow the
31 space available for then within their opcodes. By default this option
32 is disabled as it is possible to receive spurious warnings due to using
33 exact bit patterns as immediate constants.
35 @cindex @code{-wunsigned_overflow} command line option, V850
36 @item -wunsigned_overflow
37 Causes warnings to be produced when unsigned immediate values overflow
38 the space available for then within their opcodes. By default this
39 option is disabled as it is possible to receive spurious warnings due to
40 using exact bit patterns as immediate constants.
42 @cindex @code{-mv850} command line option, V850
44 Specifies that the assembled code should be marked as being targeted at
45 the V850 processor. This allows the linker to detect attempts to link
46 such code with code assembled for other processors.
48 @c start-sanitize-v850e
49 @cindex @code{-mv850e} command line option, V850
51 Specifies that the assembled code should be marked as being targeted at
52 the V850E processor. This allows the linker to detect attempts to link
53 such code with code assembled for other processors.
56 @c start-sanitize-v850e
57 @cindex @code{-mv850ea} command line option, V850
59 Specifies that the assembled code should be marked as being targeted at
60 the V850EA processor. This allows the linker to detect attempts to link
61 such code with code assembled for other processors.
63 @cindex @code{-mv850any} command line option, V850
65 Specifies that the assembled code should be marked as being targeted at
66 the V850 processor but support instructions that are specific to the
67 extended variants of the process. This allows the production of
68 binaries that contain target specific code, but which are also intended
69 to be used in a generic fashion. For example libgcc.a contains generic
70 routines used by the code produced by GCC for all versions of the v850
71 architecture, together with support routines only used by the V850E and
82 * V850-Chars:: Special Characters
83 * V850-Regs:: Register Names
87 @subsection Special Characters
89 @cindex line comment character, V850
90 @cindex V850 line comment character
91 @samp{#} is the line comment character.
93 @subsection Register Names
95 @cindex V850 register names
96 @cindex register names, V850
97 @code{@value{AS}} supports the following names for registers:
99 @cindex @code{zero} register, V850
100 @item general register 0
102 @item general register 1
104 @item general register 2
106 @cindex @code{sp} register, V850
107 @item general register 3
109 @cindex @code{gp} register, V850
110 @item general register 4
112 @cindex @code{tp} register, V850
113 @item general register 5
115 @item general register 6
117 @item general register 7
119 @item general register 8
121 @item general register 9
123 @item general register 10
125 @item general register 11
127 @item general register 12
129 @item general register 13
131 @item general register 14
133 @item general register 15
135 @item general register 16
137 @item general register 17
139 @item general register 18
141 @item general register 19
143 @item general register 20
145 @item general register 21
147 @item general register 22
149 @item general register 23
151 @item general register 24
153 @item general register 25
155 @item general register 26
157 @item general register 27
159 @item general register 28
161 @item general register 29
163 @cindex @code{ep} register, V850
164 @item general register 30
166 @cindex @code{lp} register, V850
167 @item general register 31
169 @cindex @code{eipc} register, V850
170 @item system register 0
172 @cindex @code{eipsw} register, V850
173 @item system register 1
175 @cindex @code{fepc} register, V850
176 @item system register 2
178 @cindex @code{fepsw} register, V850
179 @item system register 3
181 @cindex @code{ecr} register, V850
182 @item system register 4
184 @cindex @code{psw} register, V850
185 @item system register 5
187 @c start-sanitize-v850e
188 @cindex @code{ctpc} register, V850
189 @item system register 16
191 @cindex @code{ctpsw} register, V850
192 @item system register 17
194 @cindex @code{dbpc} register, V850
195 @item system register 18
197 @cindex @code{dbpsw} register, V850
198 @item system register 19
200 @cindex @code{ctbp} register, V850
201 @item system register 20
203 @c end-sanitize-v850e
206 @node V850 Floating Point
207 @section Floating Point
209 @cindex floating point, V850 (@sc{ieee})
210 @cindex V850 floating point (@sc{ieee})
211 The V850 family uses @sc{ieee} floating-point numbers.
213 @node V850 Directives
214 @section V850 Machine Directives
216 @cindex machine directives, V850
217 @cindex V850 machine directives
219 @cindex @code{offset} directive, V850
220 @item .offset @var{<expression>}
221 Moves the offset into the current section to the specified amount.
223 @cindex @code{section} directive, V850
224 @item .section "name", <type>
225 This is an extension to the standard .section directive. It sets the
226 current section to be <type> and creates an alias for this section
229 @cindex @code{.v850} directive, V850
231 Specifies that the assembled code should be marked as being targeted at
232 the V850 processor. This allows the linker to detect attempts to link
233 such code with code assembled for other processors.
235 @c start-sanitize-v850e
236 @cindex @code{.v850e} directive, V850
238 Specifies that the assembled code should be marked as being targeted at
239 the V850E processor. This allows the linker to detect attempts to link
240 such code with code assembled for other processors.
241 @c end-sanitize-v850e
243 @c start-sanitize-v850e
244 @cindex @code{.v850ea} directive, V850
246 Specifies that the assembled code should be marked as being targeted at
247 the V850EA processor. This allows the linker to detect attempts to link
248 such code with code assembled for other processors.
249 @c end-sanitize-v850e
257 @cindex opcodes for V850
258 @code{@value{AS}} implements all the standard V850 opcodes.
260 @code{@value{AS}} also implements the following pseudo ops:
264 @cindex @code{hi0} pseudo-op, V850
266 Computes the higher 16 bits of the given expression and stores it into
267 the immediate operand field of the given instruction. For example:
269 @samp{mulhi hi0(here - there), r5, r6}
271 computes the difference between the address of labels 'here' and
272 'there', takes the upper 16 bits of this difference, shifts it down 16
273 bits and then mutliplies it by the lower 16 bits in register 5, putting
274 the result into register 6.
276 @cindex @code{lo} pseudo-op, V850
278 Computes the lower 16 bits of the given expression and stores it into
279 the immediate operand field of the given instruction. For example:
281 @samp{addi lo(here - there), r5, r6}
283 computes the difference between the address of labels 'here' and
284 'there', takes the lower 16 bits of this difference and adds it to
285 register 5, putting the result into register 6.
287 @cindex @code{hi} pseudo-op, V850
289 Computes the higher 16 bits of the given expression and then adds the
290 value of the most significant bit of the lower 16 bits of the expression
291 and stores the result into the immediate operand field of the given
292 instruction. For example the following code can be used to compute the
293 address of the label 'here' and store it into register 6:
295 @samp{movhi hi(here), r0, r6}
296 @samp{movea lo(here), r6, r6}
298 The reason for this special behaviour is that movea performs a sign
299 extention on its immediate operand. So for example if the address of
300 'here' was 0xFFFFFFFF then without the special behaviour of the hi()
301 pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the
302 movea instruction would takes its immediate operand, 0xFFFF, sign extend
303 it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF
304 which is wrong (the fifth nibble is E). With the hi() pseudo op adding
305 in the top bit of the lo() pseudo op, the movhi instruction actually
306 stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction
307 stores 0xFFFFFFFF into r6 - the right value.
309 @c start-sanitize-v850e
310 @cindex @code{hilo} pseudo-op, V850
312 Computes the 32 bit value of the given expression and stores it into
313 the immediate operand field of the given instruction (which must be a
314 mov instruction). For example:
316 @samp{mov hilo(here), r6}
318 computes the absolute address of label 'here' and puts the result into
320 @c end-sanitize-v850e
322 @cindex @code{sdaoff} pseudo-op, V850
324 Computes the offset of the named variable from the start of the Small
325 Data Area (whoes address is held in register 4, the GP register) and
326 stores the result as a 16 bit signed value in the immediate operand
327 field of the given instruction. For example:
329 @samp{ld.w sdaoff(_a_variable)[gp],r6}
331 loads the contents of the location pointed to by the label '_a_variable'
332 into register 6, provided that the label is located somewhere within +/-
333 32K of the address held in the GP register. [Note the linker assumes
334 that the GP register contains a fixed address set to the address of the
335 label called '__gp'. This can either be set up automatically by the
336 linker, or specifically set by using the @samp{--defsym __gp=<value>}
337 command line option].
339 @cindex @code{tdaoff} pseudo-op, V850
341 Computes the offset of the named variable from the start of the Tiny
342 Data Area (whoes address is held in register 30, the EP register) and
343 stores the result as a
344 @c start-sanitize-v850e
346 @c end-sanitize-v850e
347 7 or 8 bit unsigned value in the immediate
348 operand field of the given instruction. For example:
350 @samp{sld.w tdaoff(_a_variable)[ep],r6}
352 loads the contents of the location pointed to by the label '_a_variable'
353 into register 6, provided that the label is located somewhere within +256
354 bytes of the address held in the EP register. [Note the linker assumes
355 that the EP register contains a fixed address set to the address of the
356 label called '__ep'. This can either be set up automatically by the
357 linker, or specifically set by using the @samp{--defsym __ep=<value>}
358 command line option].
360 @cindex @code{zdaoff} pseudo-op, V850
362 Computes the offset of the named variable from address 0 and stores the
363 result as a 16 bit signed value in the immediate operand field of the
364 given instruction. For example:
366 @samp{movea zdaoff(_a_variable),zero,r6}
368 puts the address of the label '_a_variable' into register 6, assuming
369 that the label is somewhere within the first 32K of memory. (Strictly
370 speaking it also possible to access the last 32K of memory as well, as
371 the offsets are signed).
373 @c start-sanitize-v850e
374 @cindex @code{ctoff} pseudo-op, V850
376 Computes the offset of the named variable from the start of the Call
377 Table Area (whoes address is helg in system register 20, the CTBP
378 register) and stores the result a 6 or 16 bit unsigned value in the
379 immediate field of then given instruction or piece of data. For
382 @samp{callt ctoff(table_func1)}
384 will put the call the function whoes address is held in the call table
385 at the location labeled 'table_func1'.
386 @c end-sanitize-v850e
391 For information on the V850 instruction set, see @cite{V850
392 Family 32-/16-Bit single-Chip Microcontroller Architecture Manual} from NEC.