2 Copyright 1997, 1999, 2000, 2001 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 /*======================================================================*/
23 * Herein lies the support for dynamic specification of processor
24 * instructions and registers. Mnemonics, values, and formats for each
25 * instruction and register are specified in an ascii file consisting of
26 * table entries. The grammar for the table is defined in the document
27 * "Processor instruction table specification".
29 * Instructions use the gnu assembler syntax, with the addition of
30 * allowing mnemonics for register.
31 * Eg. "func $2,reg3,0x100,symbol ; comment"
34 * reg3 - mnemonic for processor's register defined in table
35 * 0xddd..d - immediate value
36 * symbol - address of label or external symbol
38 * First, itbl_parse reads in the table of register and instruction
39 * names and formats, and builds a list of entries for each
40 * processor/type combination. lex and yacc are used to parse
41 * the entries in the table and call functions defined here to
42 * add each entry to our list.
44 * Then, when assembling or disassembling, these functions are called to
45 * 1) get information on a processor's registers and
46 * 2) assemble/disassemble an instruction.
47 * To assemble(disassemble) an instruction, the function
48 * itbl_assemble(itbl_disassemble) is called to search the list of
49 * instruction entries, and if a match is found, uses the format
50 * described in the instruction entry structure to complete the action.
52 * Eg. Suppose we have a Mips coprocessor "cop3" with data register "d2"
53 * and we want to define function "pig" which takes two operands.
55 * Given the table entries:
56 * "p3 insn pig 0x1:24-21 dreg:20-16 immed:15-0"
58 * and that the instruction encoding for coprocessor pz has encoding:
59 * #define MIPS_ENCODE_COP_NUM(z) ((0x21|(z<<1))<<25)
60 * #define ITBL_ENCODE_PNUM(pnum) MIPS_ENCODE_COP_NUM(pnum)
62 * a structure to describe the instruction might look something like:
63 * struct itbl_entry = {
64 * e_processor processor = e_p3
65 * e_type type = e_insn
69 * struct itbl_range range = 24-21
70 * struct itbl_field *field = {
71 * e_type type = e_dreg
72 * struct itbl_range range = 20-16
73 * struct itbl_field *next = {
74 * e_type type = e_immed
75 * struct itbl_range range = 15-0
76 * struct itbl_field *next = 0
79 * struct itbl_entry *next = 0
82 * And the assembler instructions:
86 * would both assemble to the hex value:
95 #include <itbl-parse.h>
101 #define ASSERT(x) assert(x)
102 #define DBG(x) printf x
109 #define min(a,b) (a<b?a:b)
112 int itbl_have_entries
= 0;
114 /*======================================================================*/
115 /* structures for keeping itbl format entries */
118 int sbit
; /* mask starting bit position */
119 int ebit
; /* mask ending bit position */
123 e_type type
; /* dreg/creg/greg/immed/symb */
124 struct itbl_range range
; /* field's bitfield range within instruction */
125 unsigned long flags
; /* field flags */
126 struct itbl_field
*next
; /* next field in list */
129 /* These structures define the instructions and registers for a processor.
130 * If the type is an instruction, the structure defines the format of an
131 * instruction where the fields are the list of operands.
132 * The flags field below uses the same values as those defined in the
133 * gnu assembler and are machine specific. */
135 e_processor processor
; /* processor number */
136 e_type type
; /* dreg/creg/greg/insn */
137 char *name
; /* mnemionic name for insn/register */
138 unsigned long value
; /* opcode/instruction mask/register number */
139 unsigned long flags
; /* effects of the instruction */
140 struct itbl_range range
; /* bit range within instruction for value */
141 struct itbl_field
*fields
; /* list of operand definitions (if any) */
142 struct itbl_entry
*next
; /* next entry */
145 /* local data and structures */
147 static int itbl_num_opcodes
= 0;
148 /* Array of entries for each processor and entry type */
149 static struct itbl_entry
*entries
[e_nprocs
][e_ntypes
] = {
156 /* local prototypes */
157 static unsigned long build_opcode (struct itbl_entry
*e
);
158 static e_type
get_type (int yytype
);
159 static e_processor
get_processor (int yyproc
);
160 static struct itbl_entry
**get_entries (e_processor processor
,
162 static struct itbl_entry
*find_entry_byname (e_processor processor
,
163 e_type type
, char *name
);
164 static struct itbl_entry
*find_entry_byval (e_processor processor
,
165 e_type type
, unsigned long val
, struct itbl_range
*r
);
166 static struct itbl_entry
*alloc_entry (e_processor processor
,
167 e_type type
, char *name
, unsigned long value
);
168 static unsigned long apply_range (unsigned long value
, struct itbl_range r
);
169 static unsigned long extract_range (unsigned long value
, struct itbl_range r
);
170 static struct itbl_field
*alloc_field (e_type type
, int sbit
,
171 int ebit
, unsigned long flags
);
173 /*======================================================================*/
174 /* Interfaces to the parser */
176 /* Open the table and use lex and yacc to parse the entries.
177 * Return 1 for failure; 0 for success. */
180 itbl_parse (char *insntbl
)
183 extern int yyparse (void);
185 yyin
= fopen (insntbl
, FOPEN_RT
);
188 printf ("Can't open processor instruction specification file \"%s\"\n",
197 itbl_have_entries
= 1;
201 /* Add a register entry */
204 itbl_add_reg (int yyprocessor
, int yytype
, char *regname
,
207 return alloc_entry (get_processor (yyprocessor
), get_type (yytype
), regname
,
208 (unsigned long) regnum
);
211 /* Add an instruction entry */
214 itbl_add_insn (int yyprocessor
, char *name
, unsigned long value
,
215 int sbit
, int ebit
, unsigned long flags
)
217 struct itbl_entry
*e
;
218 e
= alloc_entry (get_processor (yyprocessor
), e_insn
, name
, value
);
221 e
->range
.sbit
= sbit
;
222 e
->range
.ebit
= ebit
;
229 /* Add an operand to an instruction entry */
232 itbl_add_operand (struct itbl_entry
*e
, int yytype
, int sbit
,
233 int ebit
, unsigned long flags
)
235 struct itbl_field
*f
, **last_f
;
238 /* Add to end of fields' list. */
239 f
= alloc_field (get_type (yytype
), sbit
, ebit
, flags
);
244 last_f
= &(*last_f
)->next
;
251 /*======================================================================*/
252 /* Interfaces for assembler and disassembler */
257 static void append_insns_as_macros (void);
259 /* Initialize for gas. */
264 struct itbl_entry
*e
, **es
;
268 if (!itbl_have_entries
)
271 /* Since register names don't have a prefix, put them in the symbol table so
272 they can't be used as symbols. This simplifies argument parsing as
273 we can let gas parse registers for us. */
274 /* Use symbol_create instead of symbol_new so we don't try to
275 output registers into the object file's symbol table. */
277 for (type
= e_regtype0
; type
< e_nregtypes
; type
++)
278 for (procn
= e_p0
; procn
< e_nprocs
; procn
++)
280 es
= get_entries (procn
, type
);
281 for (e
= *es
; e
; e
= e
->next
)
283 symbol_table_insert (symbol_create (e
->name
, reg_section
,
284 e
->value
, &zero_address_frag
));
287 append_insns_as_macros ();
290 /* Append insns to opcodes table and increase number of opcodes
291 * Structure of opcodes table:
295 * const char *args; - string describing the arguments.
296 * unsigned long match; - opcode, or ISA level if pinfo=INSN_MACRO
297 * unsigned long mask; - opcode mask, or macro id if pinfo=INSN_MACRO
298 * unsigned long pinfo; - insn flags, or INSN_MACRO
301 * {"li", "t,i", 0x34000000, 0xffe00000, WR_t },
302 * {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
305 static char *form_args (struct itbl_entry
*e
);
307 append_insns_as_macros (void)
309 struct ITBL_OPCODE_STRUCT
*new_opcodes
, *o
;
310 struct itbl_entry
*e
, **es
;
311 int n
, id
, size
, new_size
, new_num_opcodes
;
313 if (!itbl_have_entries
)
316 if (!itbl_num_opcodes
) /* no new instructions to add! */
320 DBG (("previous num_opcodes=%d\n", ITBL_NUM_OPCODES
));
322 new_num_opcodes
= ITBL_NUM_OPCODES
+ itbl_num_opcodes
;
323 ASSERT (new_num_opcodes
>= itbl_num_opcodes
);
325 size
= sizeof (struct ITBL_OPCODE_STRUCT
) * ITBL_NUM_OPCODES
;
327 DBG (("I get=%d\n", size
/ sizeof (ITBL_OPCODES
[0])));
329 new_size
= sizeof (struct ITBL_OPCODE_STRUCT
) * new_num_opcodes
;
330 ASSERT (new_size
> size
);
332 /* FIXME since ITBL_OPCODES culd be a static table,
333 we can't realloc or delete the old memory. */
334 new_opcodes
= (struct ITBL_OPCODE_STRUCT
*) malloc (new_size
);
337 printf (_("Unable to allocate memory for new instructions\n"));
340 if (size
) /* copy preexisting opcodes table */
341 memcpy (new_opcodes
, ITBL_OPCODES
, size
);
343 /* FIXME! some NUMOPCODES are calculated expressions.
344 These need to be changed before itbls can be supported. */
346 id
= ITBL_NUM_MACROS
; /* begin the next macro id after the last */
347 o
= &new_opcodes
[ITBL_NUM_OPCODES
]; /* append macro to opcodes list */
348 for (n
= e_p0
; n
< e_nprocs
; n
++)
350 es
= get_entries (n
, e_insn
);
351 for (e
= *es
; e
; e
= e
->next
)
353 /* name, args, mask, match, pinfo
354 * {"li", "t,i", 0x34000000, 0xffe00000, WR_t },
355 * {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
356 * Construct args from itbl_fields.
359 o
->args
= strdup (form_args (e
));
360 o
->mask
= apply_range (e
->value
, e
->range
);
361 /* FIXME how to catch during assembly? */
362 /* mask to identify this insn */
363 o
->match
= apply_range (e
->value
, e
->range
);
367 o
->mask
= id
++; /* FIXME how to catch during assembly? */
368 o
->match
= 0; /* for macros, the insn_isa number */
369 o
->pinfo
= INSN_MACRO
;
372 /* Don't add instructions which caused an error */
379 ITBL_OPCODES
= new_opcodes
;
380 ITBL_NUM_OPCODES
= new_num_opcodes
;
383 At this point, we can free the entries, as they should have
384 been added to the assembler's tables.
385 Don't free name though, since name is being used by the new
388 Eventually, we should also free the new opcodes table itself
394 form_args (struct itbl_entry
*e
)
398 struct itbl_field
*f
;
401 for (f
= e
->fields
; f
; f
= f
->next
)
421 c
= 0; /* ignore; unknown field type */
433 #endif /* !STAND_ALONE */
435 /* Get processor's register name from val */
438 itbl_get_reg_val (char *name
, unsigned long *pval
)
443 for (p
= e_p0
; p
< e_nprocs
; p
++)
445 for (t
= e_regtype0
; t
< e_nregtypes
; t
++)
447 if (itbl_get_val (p
, t
, name
, pval
))
455 itbl_get_name (e_processor processor
, e_type type
, unsigned long val
)
457 struct itbl_entry
*r
;
458 /* type depends on instruction passed */
459 r
= find_entry_byval (processor
, type
, val
, 0);
463 return 0; /* error; invalid operand */
466 /* Get processor's register value from name */
469 itbl_get_val (e_processor processor
, e_type type
, char *name
,
472 struct itbl_entry
*r
;
473 /* type depends on instruction passed */
474 r
= find_entry_byname (processor
, type
, name
);
481 /* Assemble instruction "name" with operands "s".
482 * name - name of instruction
484 * returns - long word for assembled instruction */
487 itbl_assemble (char *name
, char *s
)
489 unsigned long opcode
;
490 struct itbl_entry
*e
= NULL
;
491 struct itbl_field
*f
;
496 return 0; /* error! must have an opcode name/expr */
498 /* find entry in list of instructions for all processors */
499 for (processor
= 0; processor
< e_nprocs
; processor
++)
501 e
= find_entry_byname (processor
, e_insn
, name
);
506 return 0; /* opcode not in table; invalid instruction */
507 opcode
= build_opcode (e
);
509 /* parse opcode's args (if any) */
510 for (f
= e
->fields
; f
; f
= f
->next
) /* for each arg, ... */
512 struct itbl_entry
*r
;
515 return 0; /* error - not enough operands */
516 n
= itbl_get_field (&s
);
517 /* n should be in form $n or 0xhhh (are symbol names valid?? */
523 /* Accept either a string name
524 * or '$' followed by the register number */
528 value
= strtol (n
, 0, 10);
529 /* FIXME! could have "0l"... then what?? */
530 if (value
== 0 && *n
!= '0')
531 return 0; /* error; invalid operand */
535 r
= find_entry_byname (e
->processor
, f
->type
, n
);
539 return 0; /* error; invalid operand */
543 /* use assembler's symbol table to find symbol */
544 /* FIXME!! Do we need this?
545 if so, what about relocs??
546 my_getExpression (&imm_expr, s);
547 return 0; /-* error; invalid operand *-/
550 /* If not a symbol, fall thru to IMMED */
552 if (*n
== '0' && *(n
+ 1) == 'x') /* hex begins 0x... */
555 value
= strtol (n
, 0, 16);
556 /* FIXME! could have "0xl"... then what?? */
560 value
= strtol (n
, 0, 10);
561 /* FIXME! could have "0l"... then what?? */
562 if (value
== 0 && *n
!= '0')
563 return 0; /* error; invalid operand */
567 return 0; /* error; invalid field spec */
569 opcode
|= apply_range (value
, f
->range
);
572 return 0; /* error - too many operands */
573 return opcode
; /* done! */
576 /* Disassemble instruction "insn".
578 * s - buffer to hold disassembled instruction
579 * returns - 1 if succeeded; 0 if failed
583 itbl_disassemble (char *s
, unsigned long insn
)
585 e_processor processor
;
586 struct itbl_entry
*e
;
587 struct itbl_field
*f
;
589 if (!ITBL_IS_INSN (insn
))
590 return 0; /* error */
591 processor
= get_processor (ITBL_DECODE_PNUM (insn
));
593 /* find entry in list */
594 e
= find_entry_byval (processor
, e_insn
, insn
, 0);
596 return 0; /* opcode not in table; invalid instruction */
599 /* Parse insn's args (if any). */
600 for (f
= e
->fields
; f
; f
= f
->next
) /* for each arg, ... */
602 struct itbl_entry
*r
;
605 if (f
== e
->fields
) /* First operand is preceded by tab. */
607 else /* ','s separate following operands. */
609 value
= extract_range (insn
, f
->range
);
610 /* n should be in form $n or 0xhhh (are symbol names valid?? */
616 /* Accept either a string name
617 or '$' followed by the register number. */
618 r
= find_entry_byval (e
->processor
, f
->type
, value
, &f
->range
);
622 sprintf (s
, "%s$%lu", s
, value
);
625 /* Use assembler's symbol table to find symbol. */
626 /* FIXME!! Do we need this? If so, what about relocs?? */
627 /* If not a symbol, fall through to IMMED. */
629 sprintf (s
, "%s0x%lx", s
, value
);
632 return 0; /* error; invalid field spec */
635 return 1; /* Done! */
638 /*======================================================================*/
640 * Local functions for manipulating private structures containing
641 * the names and format for the new instructions and registers
642 * for each processor.
645 /* Calculate instruction's opcode and function values from entry */
648 build_opcode (struct itbl_entry
*e
)
650 unsigned long opcode
;
652 opcode
= apply_range (e
->value
, e
->range
);
653 opcode
|= ITBL_ENCODE_PNUM (e
->processor
);
657 /* Calculate absolute value given the relative value and bit position range
658 * within the instruction.
659 * The range is inclusive where 0 is least significant bit.
660 * A range of { 24, 20 } will have a mask of
662 * pos: 1098 7654 3210 9876 5432 1098 7654 3210
663 * bin: 0000 0001 1111 0000 0000 0000 0000 0000
664 * hex: 0 1 f 0 0 0 0 0
669 apply_range (unsigned long rval
, struct itbl_range r
)
673 int len
= MAX_BITPOS
- r
.sbit
;
675 ASSERT (r
.sbit
>= r
.ebit
);
676 ASSERT (MAX_BITPOS
>= r
.sbit
);
677 ASSERT (r
.ebit
>= 0);
679 /* create mask by truncating 1s by shifting */
680 mask
= 0xffffffff << len
;
682 mask
= mask
>> r
.ebit
;
683 mask
= mask
<< r
.ebit
;
685 aval
= (rval
<< r
.ebit
) & mask
;
689 /* Calculate relative value given the absolute value and bit position range
690 * within the instruction. */
693 extract_range (unsigned long aval
, struct itbl_range r
)
697 int len
= MAX_BITPOS
- r
.sbit
;
699 /* create mask by truncating 1s by shifting */
700 mask
= 0xffffffff << len
;
702 mask
= mask
>> r
.ebit
;
703 mask
= mask
<< r
.ebit
;
705 rval
= (aval
& mask
) >> r
.ebit
;
709 /* Extract processor's assembly instruction field name from s;
710 * forms are "n args" "n,args" or "n" */
711 /* Return next argument from string pointer "s" and advance s.
712 * delimiters are " ,()" */
715 itbl_get_field (char **S
)
724 /* FIXME: This is a weird set of delimiters. */
725 len
= strcspn (s
, " \t,()");
726 ASSERT (128 > len
+ 1);
730 s
= 0; /* no more args */
732 s
+= len
+ 1; /* advance to next arg */
738 /* Search entries for a given processor and type
739 * to find one matching the name "n".
740 * Return a pointer to the entry */
742 static struct itbl_entry
*
743 find_entry_byname (e_processor processor
,
744 e_type type
, char *n
)
746 struct itbl_entry
*e
, **es
;
748 es
= get_entries (processor
, type
);
749 for (e
= *es
; e
; e
= e
->next
) /* for each entry, ... */
751 if (!strcmp (e
->name
, n
))
757 /* Search entries for a given processor and type
758 * to find one matching the value "val" for the range "r".
759 * Return a pointer to the entry.
760 * This function is used for disassembling fields of an instruction.
763 static struct itbl_entry
*
764 find_entry_byval (e_processor processor
, e_type type
,
765 unsigned long val
, struct itbl_range
*r
)
767 struct itbl_entry
*e
, **es
;
770 es
= get_entries (processor
, type
);
771 for (e
= *es
; e
; e
= e
->next
) /* for each entry, ... */
773 if (processor
!= e
->processor
)
775 /* For insns, we might not know the range of the opcode,
776 * so a range of 0 will allow this routine to match against
777 * the range of the entry to be compared with.
778 * This could cause ambiguities.
779 * For operands, we get an extracted value and a range.
781 /* if range is 0, mask val against the range of the compared entry. */
782 if (r
== 0) /* if no range passed, must be whole 32-bits
783 * so create 32-bit value from entry's range */
785 eval
= apply_range (e
->value
, e
->range
);
786 val
&= apply_range (0xffffffff, e
->range
);
788 else if ((r
->sbit
== e
->range
.sbit
&& r
->ebit
== e
->range
.ebit
)
789 || (e
->range
.sbit
== 0 && e
->range
.ebit
== 0))
791 eval
= apply_range (e
->value
, *r
);
792 val
= apply_range (val
, *r
);
802 /* Return a pointer to the list of entries for a given processor and type. */
804 static struct itbl_entry
**
805 get_entries (e_processor processor
, e_type type
)
807 return &entries
[processor
][type
];
810 /* Return an integral value for the processor passed from yyparse. */
813 get_processor (int yyproc
)
815 /* translate from yacc's processor to enum */
816 if (yyproc
>= e_p0
&& yyproc
< e_nprocs
)
817 return (e_processor
) yyproc
;
818 return e_invproc
; /* error; invalid processor */
821 /* Return an integral value for the entry type passed from yyparse. */
824 get_type (int yytype
)
828 /* translate from yacc's type to enum */
842 return e_invtype
; /* error; invalid type */
846 /* Allocate and initialize an entry */
848 static struct itbl_entry
*
849 alloc_entry (e_processor processor
, e_type type
,
850 char *name
, unsigned long value
)
852 struct itbl_entry
*e
, **es
;
855 e
= (struct itbl_entry
*) malloc (sizeof (struct itbl_entry
));
858 memset (e
, 0, sizeof (struct itbl_entry
));
859 e
->name
= (char *) malloc (sizeof (strlen (name
)) + 1);
861 strcpy (e
->name
, name
);
862 e
->processor
= processor
;
865 es
= get_entries (e
->processor
, e
->type
);
872 /* Allocate and initialize an entry's field */
874 static struct itbl_field
*
875 alloc_field (e_type type
, int sbit
, int ebit
,
878 struct itbl_field
*f
;
879 f
= (struct itbl_field
*) malloc (sizeof (struct itbl_field
));
882 memset (f
, 0, sizeof (struct itbl_field
));
884 f
->range
.sbit
= sbit
;
885 f
->range
.ebit
= ebit
;
This page took 0.060187 seconds and 4 git commands to generate.