2 Copyright 1997, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007,
3 2009, 2010 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 /*======================================================================*/
24 * Herein lies the support for dynamic specification of processor
25 * instructions and registers. Mnemonics, values, and formats for each
26 * instruction and register are specified in an ascii file consisting of
27 * table entries. The grammar for the table is defined in the document
28 * "Processor instruction table specification".
30 * Instructions use the gnu assembler syntax, with the addition of
31 * allowing mnemonics for register.
32 * Eg. "func $2,reg3,0x100,symbol ; comment"
35 * reg3 - mnemonic for processor's register defined in table
36 * 0xddd..d - immediate value
37 * symbol - address of label or external symbol
39 * First, itbl_parse reads in the table of register and instruction
40 * names and formats, and builds a list of entries for each
41 * processor/type combination. lex and yacc are used to parse
42 * the entries in the table and call functions defined here to
43 * add each entry to our list.
45 * Then, when assembling or disassembling, these functions are called to
46 * 1) get information on a processor's registers and
47 * 2) assemble/disassemble an instruction.
48 * To assemble(disassemble) an instruction, the function
49 * itbl_assemble(itbl_disassemble) is called to search the list of
50 * instruction entries, and if a match is found, uses the format
51 * described in the instruction entry structure to complete the action.
53 * Eg. Suppose we have a Mips coprocessor "cop3" with data register "d2"
54 * and we want to define function "pig" which takes two operands.
56 * Given the table entries:
57 * "p3 insn pig 0x1:24-21 dreg:20-16 immed:15-0"
59 * and that the instruction encoding for coprocessor pz has encoding:
60 * #define MIPS_ENCODE_COP_NUM(z) ((0x21|(z<<1))<<25)
61 * #define ITBL_ENCODE_PNUM(pnum) MIPS_ENCODE_COP_NUM(pnum)
63 * a structure to describe the instruction might look something like:
64 * struct itbl_entry = {
65 * e_processor processor = e_p3
66 * e_type type = e_insn
70 * struct itbl_range range = 24-21
71 * struct itbl_field *field = {
72 * e_type type = e_dreg
73 * struct itbl_range range = 20-16
74 * struct itbl_field *next = {
75 * e_type type = e_immed
76 * struct itbl_range range = 15-0
77 * struct itbl_field *next = 0
80 * struct itbl_entry *next = 0
83 * And the assembler instructions:
87 * would both assemble to the hex value:
94 #include <itbl-parse.h>
100 #define ASSERT(x) gas_assert (x)
101 #define DBG(x) printf x
108 #define min(a,b) (a<b?a:b)
111 int itbl_have_entries
= 0;
113 /*======================================================================*/
114 /* structures for keeping itbl format entries */
117 int sbit
; /* mask starting bit position */
118 int ebit
; /* mask ending bit position */
122 e_type type
; /* dreg/creg/greg/immed/symb */
123 struct itbl_range range
; /* field's bitfield range within instruction */
124 unsigned long flags
; /* field flags */
125 struct itbl_field
*next
; /* next field in list */
128 /* These structures define the instructions and registers for a processor.
129 * If the type is an instruction, the structure defines the format of an
130 * instruction where the fields are the list of operands.
131 * The flags field below uses the same values as those defined in the
132 * gnu assembler and are machine specific. */
134 e_processor processor
; /* processor number */
135 e_type type
; /* dreg/creg/greg/insn */
136 char *name
; /* mnemionic name for insn/register */
137 unsigned long value
; /* opcode/instruction mask/register number */
138 unsigned long flags
; /* effects of the instruction */
139 struct itbl_range range
; /* bit range within instruction for value */
140 struct itbl_field
*fields
; /* list of operand definitions (if any) */
141 struct itbl_entry
*next
; /* next entry */
144 /* local data and structures */
146 static int itbl_num_opcodes
= 0;
147 /* Array of entries for each processor and entry type */
148 static struct itbl_entry
*entries
[e_nprocs
][e_ntypes
];
150 /* local prototypes */
151 static unsigned long build_opcode (struct itbl_entry
*e
);
152 static e_type
get_type (int yytype
);
153 static e_processor
get_processor (int yyproc
);
154 static struct itbl_entry
**get_entries (e_processor processor
,
156 static struct itbl_entry
*find_entry_byname (e_processor processor
,
157 e_type type
, char *name
);
158 static struct itbl_entry
*find_entry_byval (e_processor processor
,
159 e_type type
, unsigned long val
, struct itbl_range
*r
);
160 static struct itbl_entry
*alloc_entry (e_processor processor
,
161 e_type type
, char *name
, unsigned long value
);
162 static unsigned long apply_range (unsigned long value
, struct itbl_range r
);
163 static unsigned long extract_range (unsigned long value
, struct itbl_range r
);
164 static struct itbl_field
*alloc_field (e_type type
, int sbit
,
165 int ebit
, unsigned long flags
);
167 /*======================================================================*/
168 /* Interfaces to the parser */
170 /* Open the table and use lex and yacc to parse the entries.
171 * Return 1 for failure; 0 for success. */
174 itbl_parse (char *insntbl
)
177 extern int yyparse (void);
179 yyin
= fopen (insntbl
, FOPEN_RT
);
182 printf ("Can't open processor instruction specification file \"%s\"\n",
191 itbl_have_entries
= 1;
195 /* Add a register entry */
198 itbl_add_reg (int yyprocessor
, int yytype
, char *regname
,
201 return alloc_entry (get_processor (yyprocessor
), get_type (yytype
), regname
,
202 (unsigned long) regnum
);
205 /* Add an instruction entry */
208 itbl_add_insn (int yyprocessor
, char *name
, unsigned long value
,
209 int sbit
, int ebit
, unsigned long flags
)
211 struct itbl_entry
*e
;
212 e
= alloc_entry (get_processor (yyprocessor
), e_insn
, name
, value
);
215 e
->range
.sbit
= sbit
;
216 e
->range
.ebit
= ebit
;
223 /* Add an operand to an instruction entry */
226 itbl_add_operand (struct itbl_entry
*e
, int yytype
, int sbit
,
227 int ebit
, unsigned long flags
)
229 struct itbl_field
*f
, **last_f
;
232 /* Add to end of fields' list. */
233 f
= alloc_field (get_type (yytype
), sbit
, ebit
, flags
);
238 last_f
= &(*last_f
)->next
;
245 /*======================================================================*/
246 /* Interfaces for assembler and disassembler */
249 static void append_insns_as_macros (void);
251 /* Initialize for gas. */
256 struct itbl_entry
*e
, **es
;
260 if (!itbl_have_entries
)
263 /* Since register names don't have a prefix, put them in the symbol table so
264 they can't be used as symbols. This simplifies argument parsing as
265 we can let gas parse registers for us. */
266 /* Use symbol_create instead of symbol_new so we don't try to
267 output registers into the object file's symbol table. */
269 for (type
= e_regtype0
; type
< e_nregtypes
; type
++)
270 for (procn
= e_p0
; procn
< e_nprocs
; procn
++)
272 es
= get_entries (procn
, type
);
273 for (e
= *es
; e
; e
= e
->next
)
275 symbol_table_insert (symbol_create (e
->name
, reg_section
,
276 e
->value
, &zero_address_frag
));
279 append_insns_as_macros ();
282 /* Append insns to opcodes table and increase number of opcodes
283 * Structure of opcodes table:
287 * const char *args; - string describing the arguments.
288 * unsigned long match; - opcode, or ISA level if pinfo=INSN_MACRO
289 * unsigned long mask; - opcode mask, or macro id if pinfo=INSN_MACRO
290 * unsigned long pinfo; - insn flags, or INSN_MACRO
293 * {"li", "t,i", 0x34000000, 0xffe00000, WR_t },
294 * {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
297 static char *form_args (struct itbl_entry
*e
);
299 append_insns_as_macros (void)
301 struct ITBL_OPCODE_STRUCT
*new_opcodes
, *o
;
302 struct itbl_entry
*e
, **es
;
303 int n
, size
, new_size
, new_num_opcodes
;
308 if (!itbl_have_entries
)
311 if (!itbl_num_opcodes
) /* no new instructions to add! */
315 DBG (("previous num_opcodes=%d\n", ITBL_NUM_OPCODES
));
317 new_num_opcodes
= ITBL_NUM_OPCODES
+ itbl_num_opcodes
;
318 ASSERT (new_num_opcodes
>= itbl_num_opcodes
);
320 size
= sizeof (struct ITBL_OPCODE_STRUCT
) * ITBL_NUM_OPCODES
;
322 DBG (("I get=%d\n", size
/ sizeof (ITBL_OPCODES
[0])));
324 new_size
= sizeof (struct ITBL_OPCODE_STRUCT
) * new_num_opcodes
;
325 ASSERT (new_size
> size
);
327 /* FIXME since ITBL_OPCODES culd be a static table,
328 we can't realloc or delete the old memory. */
329 new_opcodes
= (struct ITBL_OPCODE_STRUCT
*) malloc (new_size
);
332 printf (_("Unable to allocate memory for new instructions\n"));
335 if (size
) /* copy preexisting opcodes table */
336 memcpy (new_opcodes
, ITBL_OPCODES
, size
);
338 /* FIXME! some NUMOPCODES are calculated expressions.
339 These need to be changed before itbls can be supported. */
342 id
= ITBL_NUM_MACROS
; /* begin the next macro id after the last */
344 o
= &new_opcodes
[ITBL_NUM_OPCODES
]; /* append macro to opcodes list */
345 for (n
= e_p0
; n
< e_nprocs
; n
++)
347 es
= get_entries (n
, e_insn
);
348 for (e
= *es
; e
; e
= e
->next
)
350 /* name, args, mask, match, pinfo
351 * {"li", "t,i", 0x34000000, 0xffe00000, WR_t },
352 * {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
353 * Construct args from itbl_fields.
356 o
->args
= strdup (form_args (e
));
357 o
->mask
= apply_range (e
->value
, e
->range
);
358 /* FIXME how to catch during assembly? */
359 /* mask to identify this insn */
360 o
->match
= apply_range (e
->value
, e
->range
);
364 o
->mask
= id
++; /* FIXME how to catch during assembly? */
365 o
->match
= 0; /* for macros, the insn_isa number */
366 o
->pinfo
= INSN_MACRO
;
369 /* Don't add instructions which caused an error */
376 ITBL_OPCODES
= new_opcodes
;
377 ITBL_NUM_OPCODES
= new_num_opcodes
;
380 At this point, we can free the entries, as they should have
381 been added to the assembler's tables.
382 Don't free name though, since name is being used by the new
385 Eventually, we should also free the new opcodes table itself
391 form_args (struct itbl_entry
*e
)
395 struct itbl_field
*f
;
398 for (f
= e
->fields
; f
; f
= f
->next
)
418 c
= 0; /* ignore; unknown field type */
430 #endif /* !STAND_ALONE */
432 /* Get processor's register name from val */
435 itbl_get_reg_val (char *name
, unsigned long *pval
)
440 for (p
= e_p0
; p
< e_nprocs
; p
++)
442 for (t
= e_regtype0
; t
< e_nregtypes
; t
++)
444 if (itbl_get_val (p
, t
, name
, pval
))
452 itbl_get_name (e_processor processor
, e_type type
, unsigned long val
)
454 struct itbl_entry
*r
;
455 /* type depends on instruction passed */
456 r
= find_entry_byval (processor
, type
, val
, 0);
460 return 0; /* error; invalid operand */
463 /* Get processor's register value from name */
466 itbl_get_val (e_processor processor
, e_type type
, char *name
,
469 struct itbl_entry
*r
;
470 /* type depends on instruction passed */
471 r
= find_entry_byname (processor
, type
, name
);
478 /* Assemble instruction "name" with operands "s".
479 * name - name of instruction
481 * returns - long word for assembled instruction */
484 itbl_assemble (char *name
, char *s
)
486 unsigned long opcode
;
487 struct itbl_entry
*e
= NULL
;
488 struct itbl_field
*f
;
493 return 0; /* error! must have an opcode name/expr */
495 /* find entry in list of instructions for all processors */
496 for (processor
= 0; processor
< e_nprocs
; processor
++)
498 e
= find_entry_byname (processor
, e_insn
, name
);
503 return 0; /* opcode not in table; invalid instruction */
504 opcode
= build_opcode (e
);
506 /* parse opcode's args (if any) */
507 for (f
= e
->fields
; f
; f
= f
->next
) /* for each arg, ... */
509 struct itbl_entry
*r
;
512 return 0; /* error - not enough operands */
513 n
= itbl_get_field (&s
);
514 /* n should be in form $n or 0xhhh (are symbol names valid?? */
520 /* Accept either a string name
521 * or '$' followed by the register number */
525 value
= strtol (n
, 0, 10);
526 /* FIXME! could have "0l"... then what?? */
527 if (value
== 0 && *n
!= '0')
528 return 0; /* error; invalid operand */
532 r
= find_entry_byname (e
->processor
, f
->type
, n
);
536 return 0; /* error; invalid operand */
540 /* use assembler's symbol table to find symbol */
541 /* FIXME!! Do we need this?
542 if so, what about relocs??
543 my_getExpression (&imm_expr, s);
544 return 0; /-* error; invalid operand *-/
547 /* If not a symbol, fall thru to IMMED */
549 if (*n
== '0' && *(n
+ 1) == 'x') /* hex begins 0x... */
552 value
= strtol (n
, 0, 16);
553 /* FIXME! could have "0xl"... then what?? */
557 value
= strtol (n
, 0, 10);
558 /* FIXME! could have "0l"... then what?? */
559 if (value
== 0 && *n
!= '0')
560 return 0; /* error; invalid operand */
564 return 0; /* error; invalid field spec */
566 opcode
|= apply_range (value
, f
->range
);
569 return 0; /* error - too many operands */
570 return opcode
; /* done! */
573 /* Disassemble instruction "insn".
575 * s - buffer to hold disassembled instruction
576 * returns - 1 if succeeded; 0 if failed
580 itbl_disassemble (char *s
, unsigned long insn
)
582 e_processor processor
;
583 struct itbl_entry
*e
;
584 struct itbl_field
*f
;
586 if (!ITBL_IS_INSN (insn
))
587 return 0; /* error */
588 processor
= get_processor (ITBL_DECODE_PNUM (insn
));
590 /* find entry in list */
591 e
= find_entry_byval (processor
, e_insn
, insn
, 0);
593 return 0; /* opcode not in table; invalid instruction */
596 /* Parse insn's args (if any). */
597 for (f
= e
->fields
; f
; f
= f
->next
) /* for each arg, ... */
599 struct itbl_entry
*r
;
603 if (f
== e
->fields
) /* First operand is preceded by tab. */
605 else /* ','s separate following operands. */
607 value
= extract_range (insn
, f
->range
);
608 /* n should be in form $n or 0xhhh (are symbol names valid?? */
614 /* Accept either a string name
615 or '$' followed by the register number. */
616 r
= find_entry_byval (e
->processor
, f
->type
, value
, &f
->range
);
621 sprintf (s_value
, "$%lu", value
);
626 /* Use assembler's symbol table to find symbol. */
627 /* FIXME!! Do we need this? If so, what about relocs?? */
628 /* If not a symbol, fall through to IMMED. */
630 sprintf (s_value
, "0x%lx", value
);
634 return 0; /* error; invalid field spec */
637 return 1; /* Done! */
640 /*======================================================================*/
642 * Local functions for manipulating private structures containing
643 * the names and format for the new instructions and registers
644 * for each processor.
647 /* Calculate instruction's opcode and function values from entry */
650 build_opcode (struct itbl_entry
*e
)
652 unsigned long opcode
;
654 opcode
= apply_range (e
->value
, e
->range
);
655 opcode
|= ITBL_ENCODE_PNUM (e
->processor
);
659 /* Calculate absolute value given the relative value and bit position range
660 * within the instruction.
661 * The range is inclusive where 0 is least significant bit.
662 * A range of { 24, 20 } will have a mask of
664 * pos: 1098 7654 3210 9876 5432 1098 7654 3210
665 * bin: 0000 0001 1111 0000 0000 0000 0000 0000
666 * hex: 0 1 f 0 0 0 0 0
671 apply_range (unsigned long rval
, struct itbl_range r
)
675 int len
= MAX_BITPOS
- r
.sbit
;
677 ASSERT (r
.sbit
>= r
.ebit
);
678 ASSERT (MAX_BITPOS
>= r
.sbit
);
679 ASSERT (r
.ebit
>= 0);
681 /* create mask by truncating 1s by shifting */
682 mask
= 0xffffffff << len
;
684 mask
= mask
>> r
.ebit
;
685 mask
= mask
<< r
.ebit
;
687 aval
= (rval
<< r
.ebit
) & mask
;
691 /* Calculate relative value given the absolute value and bit position range
692 * within the instruction. */
695 extract_range (unsigned long aval
, struct itbl_range r
)
699 int len
= MAX_BITPOS
- r
.sbit
;
701 /* create mask by truncating 1s by shifting */
702 mask
= 0xffffffff << len
;
704 mask
= mask
>> r
.ebit
;
705 mask
= mask
<< r
.ebit
;
707 rval
= (aval
& mask
) >> r
.ebit
;
711 /* Extract processor's assembly instruction field name from s;
712 * forms are "n args" "n,args" or "n" */
713 /* Return next argument from string pointer "s" and advance s.
714 * delimiters are " ,()" */
717 itbl_get_field (char **S
)
726 /* FIXME: This is a weird set of delimiters. */
727 len
= strcspn (s
, " \t,()");
728 ASSERT (128 > len
+ 1);
732 s
= 0; /* no more args */
734 s
+= len
+ 1; /* advance to next arg */
740 /* Search entries for a given processor and type
741 * to find one matching the name "n".
742 * Return a pointer to the entry */
744 static struct itbl_entry
*
745 find_entry_byname (e_processor processor
,
746 e_type type
, char *n
)
748 struct itbl_entry
*e
, **es
;
750 es
= get_entries (processor
, type
);
751 for (e
= *es
; e
; e
= e
->next
) /* for each entry, ... */
753 if (!strcmp (e
->name
, n
))
759 /* Search entries for a given processor and type
760 * to find one matching the value "val" for the range "r".
761 * Return a pointer to the entry.
762 * This function is used for disassembling fields of an instruction.
765 static struct itbl_entry
*
766 find_entry_byval (e_processor processor
, e_type type
,
767 unsigned long val
, struct itbl_range
*r
)
769 struct itbl_entry
*e
, **es
;
772 es
= get_entries (processor
, type
);
773 for (e
= *es
; e
; e
= e
->next
) /* for each entry, ... */
775 if (processor
!= e
->processor
)
777 /* For insns, we might not know the range of the opcode,
778 * so a range of 0 will allow this routine to match against
779 * the range of the entry to be compared with.
780 * This could cause ambiguities.
781 * For operands, we get an extracted value and a range.
783 /* if range is 0, mask val against the range of the compared entry. */
784 if (r
== 0) /* if no range passed, must be whole 32-bits
785 * so create 32-bit value from entry's range */
787 eval
= apply_range (e
->value
, e
->range
);
788 val
&= apply_range (0xffffffff, e
->range
);
790 else if ((r
->sbit
== e
->range
.sbit
&& r
->ebit
== e
->range
.ebit
)
791 || (e
->range
.sbit
== 0 && e
->range
.ebit
== 0))
793 eval
= apply_range (e
->value
, *r
);
794 val
= apply_range (val
, *r
);
804 /* Return a pointer to the list of entries for a given processor and type. */
806 static struct itbl_entry
**
807 get_entries (e_processor processor
, e_type type
)
809 return &entries
[processor
][type
];
812 /* Return an integral value for the processor passed from yyparse. */
815 get_processor (int yyproc
)
817 /* translate from yacc's processor to enum */
818 if (yyproc
>= e_p0
&& yyproc
< e_nprocs
)
819 return (e_processor
) yyproc
;
820 return e_invproc
; /* error; invalid processor */
823 /* Return an integral value for the entry type passed from yyparse. */
826 get_type (int yytype
)
830 /* translate from yacc's type to enum */
844 return e_invtype
; /* error; invalid type */
848 /* Allocate and initialize an entry */
850 static struct itbl_entry
*
851 alloc_entry (e_processor processor
, e_type type
,
852 char *name
, unsigned long value
)
854 struct itbl_entry
*e
, **es
;
857 e
= (struct itbl_entry
*) malloc (sizeof (struct itbl_entry
));
860 memset (e
, 0, sizeof (struct itbl_entry
));
861 e
->name
= (char *) malloc (sizeof (strlen (name
)) + 1);
863 strcpy (e
->name
, name
);
864 e
->processor
= processor
;
867 es
= get_entries (e
->processor
, e
->type
);
874 /* Allocate and initialize an entry's field */
876 static struct itbl_field
*
877 alloc_field (e_type type
, int sbit
, int ebit
,
880 struct itbl_field
*f
;
881 f
= (struct itbl_field
*) malloc (sizeof (struct itbl_field
));
884 memset (f
, 0, sizeof (struct itbl_field
));
886 f
->range
.sbit
= sbit
;
887 f
->range
.ebit
= ebit
;
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