gas/testsuite/gas/aarch64/illegal-sve2.l

   1 [^ :]+: Assembler messages:
   2 [^ :]+:[0-9]+: Error: operand mismatch -- `movprfx z0\.d,z1\.d'
   3 [^ :]+:[0-9]+: Info:    did you mean this\?
   4 [^ :]+:[0-9]+: Info:            movprfx z0, z1
   5 [^ :]+:[0-9]+: Warning: predicated instruction expected after `movprfx' -- `adclb z0\.d,z1\.d,z2\.d'
   6 [^ :]+:[0-9]+: Error: operand mismatch -- `adclb z0\.d,z0\.s,z0\.s'
   7 [^ :]+:[0-9]+: Info:    did you mean this\?
   8 [^ :]+:[0-9]+: Info:            adclb z0\.s, z0\.s, z0\.s
   9 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
  10 [^ :]+:[0-9]+: Info:            adclb z0\.d, z0\.d, z0\.d
  11 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclb z32\.d,z0\.d,z0\.d'
  12 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `adclb z0\.d,z32\.d,z0\.d'
  13 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclb z0\.d,z0\.d,z32\.d'
  14 [^ :]+:[0-9]+: Error: operand mismatch -- `adclt z0\.d,z0\.s,z0\.s'
  15 [^ :]+:[0-9]+: Info:    did you mean this\?
  16 [^ :]+:[0-9]+: Info:            adclt z0\.s, z0\.s, z0\.s
  17 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
  18 [^ :]+:[0-9]+: Info:            adclt z0\.d, z0\.d, z0\.d
  19 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclt z32\.s,z0\.s,z0\.s'
  20 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `adclt z0\.s,z32\.s,z0\.s'
  21 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclt z0\.s,z0\.s,z32\.s'
  22 [^ :]+:[0-9]+: Error: operand mismatch -- `addhnb z0\.b,z0\.h,z0\.b'
  23 [^ :]+:[0-9]+: Info:    did you mean this\?
  24 [^ :]+:[0-9]+: Info:            addhnb z0\.b, z0\.h, z0\.h
  25 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
  26 [^ :]+:[0-9]+: Info:            addhnb z0\.h, z0\.s, z0\.s
  27 [^ :]+:[0-9]+: Info:            addhnb z0\.s, z0\.d, z0\.d
  28 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnb z32\.b,z0\.h,z0\.h'
  29 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `addhnb z0\.b,z32\.h,z0\.h'
  30 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnb z0\.b,z0\.h,z32\.h'
  31 [^ :]+:[0-9]+: Error: operand mismatch -- `addhnt z0\.b,z0\.h,z0\.b'
  32 [^ :]+:[0-9]+: Info:    did you mean this\?
  33 [^ :]+:[0-9]+: Info:            addhnt z0\.b, z0\.h, z0\.h
  34 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
  35 [^ :]+:[0-9]+: Info:            addhnt z0\.h, z0\.s, z0\.s
  36 [^ :]+:[0-9]+: Info:            addhnt z0\.s, z0\.d, z0\.d
  37 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnt z32\.b,z0\.h,z0\.h'
  38 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `addhnt z0\.b,z32\.h,z0\.h'
  39 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnt z0\.b,z0\.h,z32\.h'
  40 [^ :]+:[0-9]+: Warning: register size not compatible with previous `movprfx' at operand 1 -- `addp z0\.b,p0/m,z0\.b,z1\.b'
  41 [^ :]+:[0-9]+: Warning: predicate register differs from that in preceding `movprfx' at operand 2 -- `addp z0\.d,p1/m,z0\.d,z1\.d'
  42 [^ :]+:[0-9]+: Error: operand mismatch -- `addp z0\.b,p0/z,z0\.b,z0\.b'
  43 [^ :]+:[0-9]+: Info:    did you mean this\?
  44 [^ :]+:[0-9]+: Info:            addp z0\.b, p0/m, z0\.b, z0\.b
  45 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
  46 [^ :]+:[0-9]+: Info:            addp z0\.h, p0/m, z0\.h, z0\.h
  47 [^ :]+:[0-9]+: Info:            addp z0\.s, p0/m, z0\.s, z0\.s
  48 [^ :]+:[0-9]+: Info:            addp z0\.d, p0/m, z0\.d, z0\.d
  49 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `addp z0\.h,p0/m,z1\.h,z0\.h'
  50 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `addp z32\.s,p0/m,z32\.s,z0\.s'
  51 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `addp z0\.s,p0/m,z0\.s,z32\.s'
  52 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `addp z0\.s,p8/m,z0\.s,z0\.s'
  53 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesd z0\.b,z0\.b,z0\.b'
  54 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesd z0\.b,z1\.b,z0\.b'
  55 [^ :]+:[0-9]+: Error: operand mismatch -- `aesd z0\.b,z0\.s,z0\.b'
  56 [^ :]+:[0-9]+: Info:    did you mean this\?
  57 [^ :]+:[0-9]+: Info:            aesd z0\.b, z0\.b, z0\.b
  58 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesd z32\.b,z0\.b,z0\.b'
  59 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `aesd z0\.b,z0\.b,z32\.b'
  60 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aese z0\.b,z0\.b,z0\.b'
  61 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aese z0\.b,z1\.b,z0\.b'
  62 [^ :]+:[0-9]+: Error: operand mismatch -- `aese z0\.b,z0\.s,z0\.b'
  63 [^ :]+:[0-9]+: Info:    did you mean this\?
  64 [^ :]+:[0-9]+: Info:            aese z0\.b, z0\.b, z0\.b
  65 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aese z32\.b,z0\.b,z0\.b'
  66 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `aese z0\.b,z0\.b,z32\.b'
  67 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesimc z0\.b,z0\.b'
  68 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesimc z0\.b,z1\.b'
  69 [^ :]+:[0-9]+: Error: operand mismatch -- `aesimc z0\.b,z0\.s'
  70 [^ :]+:[0-9]+: Info:    did you mean this\?
  71 [^ :]+:[0-9]+: Info:            aesimc z0\.b, z0\.b
  72 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesimc z32\.b,z0\.b'
  73 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesmc z0\.b,z0\.b'
  74 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesmc z0\.b,z1\.b'
  75 [^ :]+:[0-9]+: Error: operand mismatch -- `aesmc z0\.b,z0\.s'
  76 [^ :]+:[0-9]+: Info:    did you mean this\?
  77 [^ :]+:[0-9]+: Info:            aesmc z0\.b, z0\.b
  78 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesmc z32\.b,z0\.b'
  79 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bcax z0\.d,z1\.d,z0\.d,z0\.d'
  80 [^ :]+:[0-9]+: Error: operand mismatch -- `bcax z0\.d,z0\.d,z0\.h,z0\.d'
  81 [^ :]+:[0-9]+: Info:    did you mean this\?
  82 [^ :]+:[0-9]+: Info:            bcax z0\.d, z0\.d, z0\.d, z0\.d
  83 [^ :]+:[0-9]+: Error: operand mismatch -- `bcax z0\.d,z0\.h,z0\.d,z0\.d'
  84 [^ :]+:[0-9]+: Info:    did you mean this\?
  85 [^ :]+:[0-9]+: Info:            bcax z0\.d, z0\.d, z0\.d, z0\.d
  86 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `bcax z32\.d,z32\.d,z0\.d,z0\.d'
  87 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bcax z0\.d,z0\.d,z32\.d,z0\.d'
  88 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bcax z0\.d,z0\.d,z0\.d,z32\.d'
  89 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bsl z0\.d,z1\.d,z0\.d,z0\.d'
  90 [^ :]+:[0-9]+: Error: operand mismatch -- `bsl z0\.d,z0\.d,z0\.h,z0\.d'
  91 [^ :]+:[0-9]+: Info:    did you mean this\?
  92 [^ :]+:[0-9]+: Info:            bsl z0\.d, z0\.d, z0\.d, z0\.d
  93 [^ :]+:[0-9]+: Error: operand mismatch -- `bsl z0\.d,z0\.h,z0\.d,z0\.d'
  94 [^ :]+:[0-9]+: Info:    did you mean this\?
  95 [^ :]+:[0-9]+: Info:            bsl z0\.d, z0\.d, z0\.d, z0\.d
  96 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bsl z32\.d,z32\.d,z0\.d,z0\.d'
  97 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bsl z0\.d,z0\.d,z32\.d,z0\.d'
  98 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bsl z0\.d,z0\.d,z0\.d,z32\.d'
  99 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bsl1n z0\.d,z1\.d,z0\.d,z0\.d'
 100 [^ :]+:[0-9]+: Error: operand mismatch -- `bsl1n z0\.d,z0\.d,z0\.h,z0\.d'
 101 [^ :]+:[0-9]+: Info:    did you mean this\?
 102 [^ :]+:[0-9]+: Info:            bsl1n z0\.d, z0\.d, z0\.d, z0\.d
 103 [^ :]+:[0-9]+: Error: operand mismatch -- `bsl1n z0\.d,z0\.h,z0\.d,z0\.d'
 104 [^ :]+:[0-9]+: Info:    did you mean this\?
 105 [^ :]+:[0-9]+: Info:            bsl1n z0\.d, z0\.d, z0\.d, z0\.d
 106 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bsl1n z32\.d,z32\.d,z0\.d,z0\.d'
 107 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bsl1n z0\.d,z0\.d,z32\.d,z0\.d'
 108 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bsl1n z0\.d,z0\.d,z0\.d,z32\.d'
 109 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bsl2n z0\.d,z1\.d,z0\.d,z0\.d'
 110 [^ :]+:[0-9]+: Error: operand mismatch -- `bsl2n z0\.d,z0\.d,z0\.h,z0\.d'
 111 [^ :]+:[0-9]+: Info:    did you mean this\?
 112 [^ :]+:[0-9]+: Info:            bsl2n z0\.d, z0\.d, z0\.d, z0\.d
 113 [^ :]+:[0-9]+: Error: operand mismatch -- `bsl2n z0\.d,z0\.h,z0\.d,z0\.d'
 114 [^ :]+:[0-9]+: Info:    did you mean this\?
 115 [^ :]+:[0-9]+: Info:            bsl2n z0\.d, z0\.d, z0\.d, z0\.d
 116 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bsl2n z32\.d,z32\.d,z0\.d,z0\.d'
 117 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bsl2n z0\.d,z0\.d,z32\.d,z0\.d'
 118 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bsl2n z0\.d,z0\.d,z0\.d,z32\.d'
 119 [^ :]+:[0-9]+: Error: operand mismatch -- `bdep z0\.b,z0\.h,z0\.b'
 120 [^ :]+:[0-9]+: Info:    did you mean this\?
 121 [^ :]+:[0-9]+: Info:            bdep z0\.b, z0\.b, z0\.b
 122 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 123 [^ :]+:[0-9]+: Info:            bdep z0\.h, z0\.h, z0\.h
 124 [^ :]+:[0-9]+: Info:            bdep z0\.s, z0\.s, z0\.s
 125 [^ :]+:[0-9]+: Info:            bdep z0\.d, z0\.d, z0\.d
 126 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bdep z32\.h,z0\.h,z0\.h'
 127 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bdep z0\.s,z32\.s,z0\.s'
 128 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bdep z0\.d,z0\.d,z32\.d'
 129 [^ :]+:[0-9]+: Error: operand mismatch -- `bext z0\.b,z0\.h,z0\.b'
 130 [^ :]+:[0-9]+: Info:    did you mean this\?
 131 [^ :]+:[0-9]+: Info:            bext z0\.b, z0\.b, z0\.b
 132 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 133 [^ :]+:[0-9]+: Info:            bext z0\.h, z0\.h, z0\.h
 134 [^ :]+:[0-9]+: Info:            bext z0\.s, z0\.s, z0\.s
 135 [^ :]+:[0-9]+: Info:            bext z0\.d, z0\.d, z0\.d
 136 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bext z32\.h,z0\.h,z0\.h'
 137 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bext z0\.s,z32\.s,z0\.s'
 138 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bext z0\.d,z0\.d,z32\.d'
 139 [^ :]+:[0-9]+: Error: operand mismatch -- `bgrp z0\.b,z0\.h,z0\.b'
 140 [^ :]+:[0-9]+: Info:    did you mean this\?
 141 [^ :]+:[0-9]+: Info:            bgrp z0\.b, z0\.b, z0\.b
 142 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 143 [^ :]+:[0-9]+: Info:            bgrp z0\.h, z0\.h, z0\.h
 144 [^ :]+:[0-9]+: Info:            bgrp z0\.s, z0\.s, z0\.s
 145 [^ :]+:[0-9]+: Info:            bgrp z0\.d, z0\.d, z0\.d
 146 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bgrp z32\.h,z0\.h,z0\.h'
 147 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bgrp z0\.s,z32\.s,z0\.s'
 148 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bgrp z0\.d,z0\.d,z32\.d'
 149 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `cadd z18\.b,z17\.b,z21\.b,#90'
 150 [^ :]+:[0-9]+: Error: rotate expected to be 90 or 270 at operand 4 -- `cadd z0\.b,z0\.b,z0\.b,#91'
 151 [^ :]+:[0-9]+: Error: operand mismatch -- `cadd z0\.b,z0\.h,z0\.h,#90'
 152 [^ :]+:[0-9]+: Info:    did you mean this\?
 153 [^ :]+:[0-9]+: Info:            cadd z0\.h, z0\.h, z0\.h, #90
 154 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 155 [^ :]+:[0-9]+: Info:            cadd z0\.b, z0\.b, z0\.b, #90
 156 [^ :]+:[0-9]+: Info:            cadd z0\.s, z0\.s, z0\.s, #90
 157 [^ :]+:[0-9]+: Info:            cadd z0\.d, z0\.d, z0\.d, #90
 158 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cdot z0\.s,z0\.b,z0\.b\[0\],#1'
 159 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `cdot z0\.s,z0\.b,z0\.b\[4\],#0'
 160 [^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.s,z0\.d,z0\.b\[0\],#0'
 161 [^ :]+:[0-9]+: Info:    did you mean this\?
 162 [^ :]+:[0-9]+: Info:            cdot z0\.d, z0\.h, z0\.h\[0\], #0
 163 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cdot z32\.s,z0\.b,z0\.b\[0\],#0'
 164 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cdot z0\.s,z32\.b,z0\.b\[0\],#0'
 165 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `cdot z0\.s,z0\.b,z8\.b\[0\],#0'
 166 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cdot z0\.d,z0\.h,z0\.h\[0\],#1'
 167 [^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.d,z0\.d,z0\.h\[0\],#0'
 168 [^ :]+:[0-9]+: Info:    did you mean this\?
 169 [^ :]+:[0-9]+: Info:            cdot z0\.d, z0\.h, z0\.h\[0\], #0
 170 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cdot z32\.d,z0\.h,z0\.h\[0\],#0'
 171 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cdot z0\.d,z32\.h,z0\.h\[0\],#0'
 172 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `cdot z0\.d,z0\.h,z16\.h\[0\],#0'
 173 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cdot z32\.s,z0\.b,z0\.b,#0'
 174 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cdot z0\.s,z32\.b,z0\.b,#0'
 175 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `cdot z0\.s,z0\.b,z32\.b,#0'
 176 [^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.s,z0\.b,z0\.s,#0'
 177 [^ :]+:[0-9]+: Info:    did you mean this\?
 178 [^ :]+:[0-9]+: Info:            cdot z0\.s, z0\.b, z0\.b, #0
 179 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 180 [^ :]+:[0-9]+: Info:            cdot z0\.d, z0\.h, z0\.h, #0
 181 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cdot z0\.s,z0\.b,z0\.b,#1'
 182 [^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.d,z0\.h,z0\.b,#0'
 183 [^ :]+:[0-9]+: Info:    did you mean this\?
 184 [^ :]+:[0-9]+: Info:            cdot z0\.d, z0\.h, z0\.h, #0
 185 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 186 [^ :]+:[0-9]+: Info:            cdot z0\.s, z0\.b, z0\.b, #0
 187 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cmla z32\.h,z0\.h,z0\.h\[0\],#0'
 188 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cmla z0\.h,z32\.h,z0\.h\[0\],#0'
 189 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `cmla z0\.h,z0\.h,z8\.h\[0\],#0'
 190 [^ :]+:[0-9]+: Error: operand mismatch -- `cmla z0\.h,z0\.h,z0\.d\[0\],#0'
 191 [^ :]+:[0-9]+: Info:    did you mean this\?
 192 [^ :]+:[0-9]+: Info:            cmla z0\.h, z0\.h, z0\.h\[0\], #0
 193 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `cmla z0\.h,z0\.h,z0\.h\[4\],#0'
 194 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cmla z0\.h,z0\.h,z0\.h\[0\],#1'
 195 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cmla z32\.s,z0\.s,z0\.s\[0\],#0'
 196 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cmla z0\.s,z32\.s,z0\.s\[0\],#0'
 197 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `cmla z0\.s,z0\.s,z16\.s\[0\],#0'
 198 [^ :]+:[0-9]+: Error: operand mismatch -- `cmla z0\.s,z0\.s,z0\.d\[0\],#0'
 199 [^ :]+:[0-9]+: Info:    did you mean this\?
 200 [^ :]+:[0-9]+: Info:            cmla z0\.h, z0\.h, z0\.h\[0\], #0
 201 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `cmla z0\.s,z0\.s,z0\.s\[2\],#0'
 202 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cmla z0\.s,z0\.s,z0\.s\[0\],#1'
 203 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cmla z32\.b,z0\.b,z0\.b,#0'
 204 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cmla z0\.b,z32\.b,z0\.b,#0'
 205 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `cmla z0\.b,z0\.b,z32\.b,#0'
 206 [^ :]+:[0-9]+: Error: operand mismatch -- `cmla z0\.b,z0\.b,z0\.h,#0'
 207 [^ :]+:[0-9]+: Info:    did you mean this\?
 208 [^ :]+:[0-9]+: Info:            cmla z0\.b, z0\.b, z0\.b, #0
 209 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 210 [^ :]+:[0-9]+: Info:            cmla z0\.h, z0\.h, z0\.h, #0
 211 [^ :]+:[0-9]+: Info:            cmla z0\.s, z0\.s, z0\.s, #0
 212 [^ :]+:[0-9]+: Info:            cmla z0\.d, z0\.d, z0\.d, #0
 213 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cmla z0\.b,z0\.b,z0\.b,#1'
 214 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `eor3 z0\.d,z1\.d,z0\.d,z0\.d'
 215 [^ :]+:[0-9]+: Error: operand mismatch -- `eor3 z0\.d,z0\.d,z0\.h,z0\.d'
 216 [^ :]+:[0-9]+: Info:    did you mean this\?
 217 [^ :]+:[0-9]+: Info:            eor3 z0\.d, z0\.d, z0\.d, z0\.d
 218 [^ :]+:[0-9]+: Error: operand mismatch -- `eor3 z0\.d,z0\.h,z0\.d,z0\.d'
 219 [^ :]+:[0-9]+: Info:    did you mean this\?
 220 [^ :]+:[0-9]+: Info:            eor3 z0\.d, z0\.d, z0\.d, z0\.d
 221 [^ :]+:[0-9]+: Error: operand mismatch -- `eorbt z0\.b,z0\.h,z0\.b'
 222 [^ :]+:[0-9]+: Info:    did you mean this\?
 223 [^ :]+:[0-9]+: Info:            eorbt z0\.b, z0\.b, z0\.b
 224 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 225 [^ :]+:[0-9]+: Info:            eorbt z0\.h, z0\.h, z0\.h
 226 [^ :]+:[0-9]+: Info:            eorbt z0\.s, z0\.s, z0\.s
 227 [^ :]+:[0-9]+: Info:            eorbt z0\.d, z0\.d, z0\.d
 228 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `eorbt z32\.h,z0\.h,z0\.h'
 229 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `eorbt z0\.s,z32\.s,z0\.s'
 230 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `eorbt z0\.s,z0\.s,z32\.s'
 231 [^ :]+:[0-9]+: Error: operand mismatch -- `eortb z0\.b,z0\.h,z0\.b'
 232 [^ :]+:[0-9]+: Info:    did you mean this\?
 233 [^ :]+:[0-9]+: Info:            eortb z0\.b, z0\.b, z0\.b
 234 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 235 [^ :]+:[0-9]+: Info:            eortb z0\.h, z0\.h, z0\.h
 236 [^ :]+:[0-9]+: Info:            eortb z0\.s, z0\.s, z0\.s
 237 [^ :]+:[0-9]+: Info:            eortb z0\.d, z0\.d, z0\.d
 238 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `eortb z32\.h,z0\.h,z0\.h'
 239 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `eortb z0\.s,z32\.s,z0\.s'
 240 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `eortb z0\.s,z0\.s,z32\.s'
 241 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z2\.b},#0'
 242 [^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.h,{z0\.b,z1\.b},#0'
 243 [^ :]+:[0-9]+: Info:    did you mean this\?
 244 [^ :]+:[0-9]+: Info:            ext z0\.b, {z0\.b, z1\.b}, #0
 245 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `ext z0\.b,{z0\.h,z1\.b},#0'
 246 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `ext z0\.b,{z0\.b,z1\.h},#0'
 247 [^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.b,{z0\.h,z1\.h},#0'
 248 [^ :]+:[0-9]+: Info:    did you mean this\?
 249 [^ :]+:[0-9]+: Info:            ext z0\.b, {z0\.b, z1\.b}, #0
 250 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z1\.b,z2\.b},#0'
 251 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b},#0'
 252 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ext z0\.b,z0\.b,#0'
 253 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z31\.b,z1\.b},#0'
 254 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z31\.b},#0'
 255 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 255 at operand 3 -- `ext z0\.b,{z0\.b,z1\.b},#256'
 256 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ext z32\.b,{z0\.b,z1\.b},#0'
 257 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ext z0\.b,{z31\.b,z32\.b},#0'
 258 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ext z0\.b,{z32\.b,z33\.b},#0'
 259 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `faddp z32\.h,p0/m,z32\.h,z0\.h'
 260 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `faddp z0\.h,p8/m,z0\.h,z0\.h'
 261 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `faddp z0\.h,p0/m,z0\.h,z32\.h'
 262 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `faddp z0\.h,p0/m,z1\.h,z0\.h'
 263 [^ :]+:[0-9]+: Error: operand mismatch -- `faddp z0\.h,p0/z,z0\.h,z0\.h'
 264 [^ :]+:[0-9]+: Info:    did you mean this\?
 265 [^ :]+:[0-9]+: Info:            faddp z0\.h, p0/m, z0\.h, z0\.h
 266 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 267 [^ :]+:[0-9]+: Info:            faddp z0\.s, p0/m, z0\.s, z0\.s
 268 [^ :]+:[0-9]+: Info:            faddp z0\.d, p0/m, z0\.d, z0\.d
 269 [^ :]+:[0-9]+: Error: operand mismatch -- `faddp z0\.h,p0/m,z0\.b,z0\.h'
 270 [^ :]+:[0-9]+: Info:    did you mean this\?
 271 [^ :]+:[0-9]+: Info:            faddp z0\.h, p0/m, z0\.h, z0\.h
 272 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 273 [^ :]+:[0-9]+: Info:            faddp z0\.s, p0/m, z0\.s, z0\.s
 274 [^ :]+:[0-9]+: Info:            faddp z0\.d, p0/m, z0\.d, z0\.d
 275 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `fcvtlt z0\.s,p0/m,z0\.h'
 276 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtlt z32\.s,p0/m,z0\.h'
 277 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtlt z0\.s,p8/m,z0\.h'
 278 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtlt z0\.s,p0/m,z32\.h'
 279 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.s,p0/m,z0\.s'
 280 [^ :]+:[0-9]+: Info:    did you mean this\?
 281 [^ :]+:[0-9]+: Info:            fcvtlt z0\.d, p0/m, z0\.s
 282 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.s,p0/z,z0\.h'
 283 [^ :]+:[0-9]+: Info:    did you mean this\?
 284 [^ :]+:[0-9]+: Info:            fcvtlt z0\.d, p0/m, z0\.s
 285 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtlt z32\.d,p0/m,z0\.s'
 286 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtlt z0\.d,p8/m,z0\.s'
 287 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtlt z0\.d,p0/m,z32\.s'
 288 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.d,p0/m,z0\.d'
 289 [^ :]+:[0-9]+: Info:    did you mean this\?
 290 [^ :]+:[0-9]+: Info:            fcvtlt z0\.d, p0/m, z0\.s
 291 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.d,p0/z,z0\.s'
 292 [^ :]+:[0-9]+: Info:    did you mean this\?
 293 [^ :]+:[0-9]+: Info:            fcvtlt z0\.d, p0/m, z0\.s
 294 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `fcvtnt z0\.h,p0/m,z0\.s'
 295 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtnt z32\.h,p0/m,z0\.s'
 296 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtnt z0\.h,p8/m,z0\.s'
 297 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtnt z0\.h,p0/m,z32\.s'
 298 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.h,p0/m,z0\.h'
 299 [^ :]+:[0-9]+: Info:    did you mean this\?
 300 [^ :]+:[0-9]+: Info:            fcvtnt z0\.s, p0/m, z0\.d
 301 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.h,p0/z,z0\.s'
 302 [^ :]+:[0-9]+: Info:    did you mean this\?
 303 [^ :]+:[0-9]+: Info:            fcvtnt z0\.s, p0/m, z0\.d
 304 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtnt z32\.s,p0/m,z0\.d'
 305 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtnt z0\.s,p8/m,z0\.d'
 306 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtnt z0\.s,p0/m,z32\.d'
 307 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.s,p0/m,z0\.s'
 308 [^ :]+:[0-9]+: Info:    did you mean this\?
 309 [^ :]+:[0-9]+: Info:            fcvtnt z0\.s, p0/m, z0\.d
 310 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.s,p0/z,z0\.d'
 311 [^ :]+:[0-9]+: Info:    did you mean this\?
 312 [^ :]+:[0-9]+: Info:            fcvtnt z0\.s, p0/m, z0\.d
 313 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtx z32\.s,p0/m,z0\.d'
 314 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtx z0\.s,p8/m,z0\.d'
 315 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtx z0\.s,p0/m,z32\.d'
 316 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtx z0\.s,p0/m,z0\.s'
 317 [^ :]+:[0-9]+: Info:    did you mean this\?
 318 [^ :]+:[0-9]+: Info:            fcvtx z0\.s, p0/m, z0\.d
 319 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtx z0\.s,p0/z,z0\.d'
 320 [^ :]+:[0-9]+: Info:    did you mean this\?
 321 [^ :]+:[0-9]+: Info:            fcvtx z0\.s, p0/m, z0\.d
 322 [^ :]+:[0-9]+: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtx z0\.s,p0/m,z2\.d'
 323 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `fcvtxnt z0\.s,p0/m,z0\.d'
 324 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtxnt z32\.s,p0/m,z0\.d'
 325 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtxnt z0\.s,p8/m,z0\.d'
 326 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtxnt z0\.s,p0/m,z32\.d'
 327 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtxnt z0\.s,p0/m,z0\.s'
 328 [^ :]+:[0-9]+: Info:    did you mean this\?
 329 [^ :]+:[0-9]+: Info:            fcvtxnt z0\.s, p0/m, z0\.d
 330 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtxnt z0\.s,p0/z,z0\.d'
 331 [^ :]+:[0-9]+: Info:    did you mean this\?
 332 [^ :]+:[0-9]+: Info:            fcvtxnt z0\.s, p0/m, z0\.d
 333 [^ :]+:[0-9]+: Error: operand mismatch -- `flogb z0\.b,p0/m,z0\.b'
 334 [^ :]+:[0-9]+: Info:    did you mean this\?
 335 [^ :]+:[0-9]+: Info:            flogb z0\.h, p0/m, z0\.h
 336 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 337 [^ :]+:[0-9]+: Info:            flogb z0\.s, p0/m, z0\.s
 338 [^ :]+:[0-9]+: Info:            flogb z0\.d, p0/m, z0\.d
 339 [^ :]+:[0-9]+: Error: operand mismatch -- `flogb z0\.b,p0/m,z0\.h'
 340 [^ :]+:[0-9]+: Info:    did you mean this\?
 341 [^ :]+:[0-9]+: Info:            flogb z0\.h, p0/m, z0\.h
 342 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 343 [^ :]+:[0-9]+: Info:            flogb z0\.s, p0/m, z0\.s
 344 [^ :]+:[0-9]+: Info:            flogb z0\.d, p0/m, z0\.d
 345 [^ :]+:[0-9]+: Error: operand mismatch -- `flogb z0\.h,p0/z,z0\.h'
 346 [^ :]+:[0-9]+: Info:    did you mean this\?
 347 [^ :]+:[0-9]+: Info:            flogb z0\.h, p0/m, z0\.h
 348 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 349 [^ :]+:[0-9]+: Info:            flogb z0\.s, p0/m, z0\.s
 350 [^ :]+:[0-9]+: Info:            flogb z0\.d, p0/m, z0\.d
 351 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `flogb z32\.h,p0/m,z0\.h'
 352 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `flogb z0\.h,p8/m,z0\.h'
 353 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `flogb z0\.h,p0/m,z32\.h'
 354 [^ :]+:[0-9]+: Error: operand mismatch -- `fmaxnmp z0\.b,p0/m,z0\.h,z0\.h'
 355 [^ :]+:[0-9]+: Info:    did you mean this\?
 356 [^ :]+:[0-9]+: Info:            fmaxnmp z0\.h, p0/m, z0\.h, z0\.h
 357 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 358 [^ :]+:[0-9]+: Info:            fmaxnmp z0\.s, p0/m, z0\.s, z0\.s
 359 [^ :]+:[0-9]+: Info:            fmaxnmp z0\.d, p0/m, z0\.d, z0\.d
 360 [^ :]+:[0-9]+: Error: operand mismatch -- `fmaxnmp z0\.h,p0/z,z0\.h,z0\.h'
 361 [^ :]+:[0-9]+: Info:    did you mean this\?
 362 [^ :]+:[0-9]+: Info:            fmaxnmp z0\.h, p0/m, z0\.h, z0\.h
 363 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 364 [^ :]+:[0-9]+: Info:            fmaxnmp z0\.s, p0/m, z0\.s, z0\.s
 365 [^ :]+:[0-9]+: Info:            fmaxnmp z0\.d, p0/m, z0\.d, z0\.d
 366 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fmaxnmp z1\.h,p0/m,z0\.h,z0\.h'
 367 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fmaxnmp z32\.h,p0/m,z32\.h,z0\.h'
 368 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fmaxnmp z0\.h,p8/m,z0\.h,z0\.h'
 369 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fmaxnmp z0\.h,p0/m,z0\.h,z32\.h'
 370 [^ :]+:[0-9]+: Error: operand mismatch -- `fmaxp z0\.b,p0/m,z0\.h,z0\.h'
 371 [^ :]+:[0-9]+: Info:    did you mean this\?
 372 [^ :]+:[0-9]+: Info:            fmaxp z0\.h, p0/m, z0\.h, z0\.h
 373 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 374 [^ :]+:[0-9]+: Info:            fmaxp z0\.s, p0/m, z0\.s, z0\.s
 375 [^ :]+:[0-9]+: Info:            fmaxp z0\.d, p0/m, z0\.d, z0\.d
 376 [^ :]+:[0-9]+: Error: operand mismatch -- `fmaxp z0\.h,p0/z,z0\.h,z0\.h'
 377 [^ :]+:[0-9]+: Info:    did you mean this\?
 378 [^ :]+:[0-9]+: Info:            fmaxp z0\.h, p0/m, z0\.h, z0\.h
 379 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 380 [^ :]+:[0-9]+: Info:            fmaxp z0\.s, p0/m, z0\.s, z0\.s
 381 [^ :]+:[0-9]+: Info:            fmaxp z0\.d, p0/m, z0\.d, z0\.d
 382 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fmaxp z1\.h,p0/m,z0\.h,z0\.h'
 383 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fmaxp z32\.h,p0/m,z32\.h,z0\.h'
 384 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fmaxp z0\.h,p8/m,z0\.h,z0\.h'
 385 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fmaxp z0\.h,p0/m,z0\.h,z32\.h'
 386 [^ :]+:[0-9]+: Error: operand mismatch -- `fminnmp z0\.b,p0/m,z0\.h,z0\.h'
 387 [^ :]+:[0-9]+: Info:    did you mean this\?
 388 [^ :]+:[0-9]+: Info:            fminnmp z0\.h, p0/m, z0\.h, z0\.h
 389 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 390 [^ :]+:[0-9]+: Info:            fminnmp z0\.s, p0/m, z0\.s, z0\.s
 391 [^ :]+:[0-9]+: Info:            fminnmp z0\.d, p0/m, z0\.d, z0\.d
 392 [^ :]+:[0-9]+: Error: operand mismatch -- `fminnmp z0\.h,p0/z,z0\.h,z0\.h'
 393 [^ :]+:[0-9]+: Info:    did you mean this\?
 394 [^ :]+:[0-9]+: Info:            fminnmp z0\.h, p0/m, z0\.h, z0\.h
 395 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 396 [^ :]+:[0-9]+: Info:            fminnmp z0\.s, p0/m, z0\.s, z0\.s
 397 [^ :]+:[0-9]+: Info:            fminnmp z0\.d, p0/m, z0\.d, z0\.d
 398 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fminnmp z1\.h,p0/m,z0\.h,z0\.h'
 399 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fminnmp z32\.h,p0/m,z32\.h,z0\.h'
 400 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fminnmp z0\.h,p8/m,z0\.h,z0\.h'
 401 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fminnmp z0\.h,p0/m,z0\.h,z32\.h'
 402 [^ :]+:[0-9]+: Error: operand mismatch -- `fminp z0\.b,p0/m,z0\.h,z0\.h'
 403 [^ :]+:[0-9]+: Info:    did you mean this\?
 404 [^ :]+:[0-9]+: Info:            fminp z0\.h, p0/m, z0\.h, z0\.h
 405 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 406 [^ :]+:[0-9]+: Info:            fminp z0\.s, p0/m, z0\.s, z0\.s
 407 [^ :]+:[0-9]+: Info:            fminp z0\.d, p0/m, z0\.d, z0\.d
 408 [^ :]+:[0-9]+: Error: operand mismatch -- `fminp z0\.h,p0/z,z0\.h,z0\.h'
 409 [^ :]+:[0-9]+: Info:    did you mean this\?
 410 [^ :]+:[0-9]+: Info:            fminp z0\.h, p0/m, z0\.h, z0\.h
 411 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 412 [^ :]+:[0-9]+: Info:            fminp z0\.s, p0/m, z0\.s, z0\.s
 413 [^ :]+:[0-9]+: Info:            fminp z0\.d, p0/m, z0\.d, z0\.d
 414 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fminp z1\.h,p0/m,z0\.h,z0\.h'
 415 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fminp z32\.h,p0/m,z32\.h,z0\.h'
 416 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fminp z0\.h,p8/m,z0\.h,z0\.h'
 417 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fminp z0\.h,p0/m,z0\.h,z32\.h'
 418 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalb z0\.s,z0\.h,z0\.h\[8\]'
 419 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalb z0\.s,z0\.h,z8\.h\[0\]'
 420 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalb z0\.s,z32\.h,z0\.h\[0\]'
 421 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]'
 422 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.h,z0\.h,z0\.h\[0\]'
 423 [^ :]+:[0-9]+: Info:    did you mean this\?
 424 [^ :]+:[0-9]+: Info:            fmlalb z0\.s, z0\.h, z0\.h\[0\]
 425 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalb z32\.s,z0\.h,z0\.h'
 426 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalb z0\.s,z32\.h,z0\.h'
 427 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlalb z0\.s,z0\.h,z32\.h'
 428 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.s,z0\.h,z0\.d'
 429 [^ :]+:[0-9]+: Info:    did you mean this\?
 430 [^ :]+:[0-9]+: Info:            fmlalb z0\.s, z0\.h, z0\.h
 431 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalt z0\.s,z0\.h,z0\.h\[8\]'
 432 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalt z0\.s,z0\.h,z8\.h\[0\]'
 433 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalt z0\.s,z32\.h,z0\.h\[0\]'
 434 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]'
 435 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.h,z0\.h,z0\.h\[0\]'
 436 [^ :]+:[0-9]+: Info:    did you mean this\?
 437 [^ :]+:[0-9]+: Info:            fmlalt z0\.s, z0\.h, z0\.h\[0\]
 438 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalt z32\.s,z0\.h,z0\.h'
 439 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalt z0\.s,z32\.h,z0\.h'
 440 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlalt z0\.s,z0\.h,z32\.h'
 441 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.s,z0\.h,z0\.d'
 442 [^ :]+:[0-9]+: Info:    did you mean this\?
 443 [^ :]+:[0-9]+: Info:            fmlalt z0\.s, z0\.h, z0\.h
 444 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlslb z0\.s,z0\.h,z0\.h\[8\]'
 445 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlslb z0\.s,z0\.h,z8\.h\[0\]'
 446 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslb z0\.s,z32\.h,z0\.h\[0\]'
 447 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslb z32\.s,z0\.h,z0\.h\[0\]'
 448 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlslb z0\.h,z0\.h,z0\.h\[0\]'
 449 [^ :]+:[0-9]+: Info:    did you mean this\?
 450 [^ :]+:[0-9]+: Info:            fmlslb z0\.s, z0\.h, z0\.h\[0\]
 451 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslb z32\.s,z0\.h,z0\.h'
 452 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslb z0\.s,z32\.h,z0\.h'
 453 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlslb z0\.s,z0\.h,z32\.h'
 454 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlslb z0\.s,z0\.h,z0\.d'
 455 [^ :]+:[0-9]+: Info:    did you mean this\?
 456 [^ :]+:[0-9]+: Info:            fmlslb z0\.s, z0\.h, z0\.h
 457 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlslt z0\.s,z0\.h,z0\.h\[8\]'
 458 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlslt z0\.s,z0\.h,z8\.h\[0\]'
 459 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslt z0\.s,z32\.h,z0\.h\[0\]'
 460 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslt z32\.s,z0\.h,z0\.h\[0\]'
 461 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlslt z0\.h,z0\.h,z0\.h\[0\]'
 462 [^ :]+:[0-9]+: Info:    did you mean this\?
 463 [^ :]+:[0-9]+: Info:            fmlslt z0\.s, z0\.h, z0\.h\[0\]
 464 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslt z32\.s,z0\.h,z0\.h'
 465 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslt z0\.s,z32\.h,z0\.h'
 466 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlslt z0\.s,z0\.h,z32\.h'
 467 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlslt z0\.s,z0\.h,z0\.d'
 468 [^ :]+:[0-9]+: Info:    did you mean this\?
 469 [^ :]+:[0-9]+: Info:            fmlslt z0\.s, z0\.h, z0\.h
 470 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `histcnt z32\.s,p0/z,z0\.s,z0\.s'
 471 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `histcnt z0\.s,p8/z,z0\.s,z0\.s'
 472 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `histcnt z0\.s,p0/z,z32\.s,z0\.s'
 473 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `histcnt z0\.s,p0/z,z0\.s,z32\.s'
 474 [^ :]+:[0-9]+: Error: operand mismatch -- `histcnt z0\.s,p0/m,z0\.s,z0\.s'
 475 [^ :]+:[0-9]+: Info:    did you mean this\?
 476 [^ :]+:[0-9]+: Info:            histcnt z0\.s, p0/z, z0\.s, z0\.s
 477 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 478 [^ :]+:[0-9]+: Info:            histcnt z0\.d, p0/z, z0\.d, z0\.d
 479 [^ :]+:[0-9]+: Error: operand mismatch -- `histcnt z0\.d,p0/z,z0\.s,z0\.s'
 480 [^ :]+:[0-9]+: Info:    did you mean this\?
 481 [^ :]+:[0-9]+: Info:            histcnt z0\.s, p0/z, z0\.s, z0\.s
 482 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 483 [^ :]+:[0-9]+: Info:            histcnt z0\.d, p0/z, z0\.d, z0\.d
 484 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `histseg z32\.b,z0\.b,z0\.b'
 485 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `histseg z0\.b,z32\.b,z0\.b'
 486 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `histseg z0\.b,z0\.b,z32\.b'
 487 [^ :]+:[0-9]+: Error: operand mismatch -- `histseg z0\.b,z0\.b,z0\.h'
 488 [^ :]+:[0-9]+: Info:    did you mean this\?
 489 [^ :]+:[0-9]+: Info:            histseg z0\.b, z0\.b, z0\.b
 490 [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1b {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
 491 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.d},p0/m,\[z0\.d\]'
 492 [^ :]+:[0-9]+: Info:    did you mean this\?
 493 [^ :]+:[0-9]+: Info:            ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
 494 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1b {z32\.d},p0/z,\[z0\.d\]'
 495 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.d},p8/z,\[z0\.d\]'
 496 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z32\.d\]'
 497 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,sp\]'
 498 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,x32\]'
 499 [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,w16\]'
 500 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,z0\.d\]'
 501 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.s},p0/z,\[z0\.d\]'
 502 [^ :]+:[0-9]+: Info:    did you mean this\?
 503 [^ :]+:[0-9]+: Info:            ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
 504 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.d},p0/z,\[z0\.s\]'
 505 [^ :]+:[0-9]+: Info:    did you mean this\?
 506 [^ :]+:[0-9]+: Info:            ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
 507 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1b {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]'
 508 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.s},p0/m,\[z0\.s\]'
 509 [^ :]+:[0-9]+: Info:    did you mean this\?
 510 [^ :]+:[0-9]+: Info:            ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
 511 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1b {z32\.s},p0/z,\[z0\.s\]'
 512 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.s},p8/z,\[z0\.s\]'
 513 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z32\.s\]'
 514 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,sp\]'
 515 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,x32\]'
 516 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,z0\.s\]'
 517 [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1d {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
 518 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]'
 519 [^ :]+:[0-9]+: Info:    did you mean this\?
 520 [^ :]+:[0-9]+: Info:            ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
 521 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1d {z32\.d},p0/z,\[z0\.d\]'
 522 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1d {z0\.d},p8/z,\[z0\.d\]'
 523 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z32\.d\]'
 524 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,sp\]'
 525 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,x32\]'
 526 [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,w16\]'
 527 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,z0\.d\]'
 528 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.s},p0/z,\[z0\.d\]'
 529 [^ :]+:[0-9]+: Info:    did you mean this\?
 530 [^ :]+:[0-9]+: Info:            ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
 531 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/z,\[z0\.s\]'
 532 [^ :]+:[0-9]+: Info:    did you mean this\?
 533 [^ :]+:[0-9]+: Info:            ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
 534 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]'
 535 [^ :]+:[0-9]+: Info:    did you mean this\?
 536 [^ :]+:[0-9]+: Info:            ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
 537 [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1h {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
 538 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1h {z0\.d},p0/m,\[z0\.d\]'
 539 [^ :]+:[0-9]+: Info:    did you mean this\?
 540 [^ :]+:[0-9]+: Info:            ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\]
 541 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1h {z32\.d},p0/z,\[z0\.d\]'
 542 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.d},p8/z,\[z0\.d\]'
 543 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z32\.d\]'
 544 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,sp\]'
 545 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,x32\]'
 546 [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,w16\]'
 547 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,z0\.d\]'
 548 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1h {z0\.s},p0/z,\[z0\.d\]'
 549 [^ :]+:[0-9]+: Info:    did you mean this\?
 550 [^ :]+:[0-9]+: Info:            ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\]
 551 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1h {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]'
 552 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1h {z32\.s},p0/z,\[z0\.s\]'
 553 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.s},p8/z,\[z0\.s\]'
 554 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z32\.s\]'
 555 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,sp\]'
 556 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,x32\]'
 557 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,z0\.s\]'
 558 [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1sb {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
 559 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sb {z0\.d},p0/m,\[z0\.d\]'
 560 [^ :]+:[0-9]+: Info:    did you mean this\?
 561 [^ :]+:[0-9]+: Info:            ldnt1sb {z0\.d}, p0/z, \[z0\.d, xzr\]
 562 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 563 [^ :]+:[0-9]+: Info:            ldnt1sb {z0\.s}, p0/z, \[z0\.s, xzr\]
 564 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sb {z32\.d},p0/z,\[z0\.d\]'
 565 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sb {z0\.d},p8/z,\[z0\.d\]'
 566 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z32\.d\]'
 567 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,sp\]'
 568 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,x32\]'
 569 [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,w16\]'
 570 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,z0\.d\]'
 571 [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
 572 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sh {z0\.d},p0/m,\[z0\.d\]'
 573 [^ :]+:[0-9]+: Info:    did you mean this\?
 574 [^ :]+:[0-9]+: Info:            ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\]
 575 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 576 [^ :]+:[0-9]+: Info:            ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\]
 577 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
 578 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]'
 579 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
 580 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
 581 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]'
 582 [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]'
 583 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]'
 584 [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
 585 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sh {z0\.d},p0/m,\[z0\.d\]'
 586 [^ :]+:[0-9]+: Info:    did you mean this\?
 587 [^ :]+:[0-9]+: Info:            ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\]
 588 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 589 [^ :]+:[0-9]+: Info:            ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\]
 590 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
 591 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]'
 592 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
 593 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
 594 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]'
 595 [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]'
 596 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]'
 597 [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1w {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
 598 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1w {z0\.d},p0/m,\[z0\.d\]'
 599 [^ :]+:[0-9]+: Info:    did you mean this\?
 600 [^ :]+:[0-9]+: Info:            ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\]
 601 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1w {z32\.d},p0/z,\[z0\.d\]'
 602 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.d},p8/z,\[z0\.d\]'
 603 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z32\.d\]'
 604 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,sp\]'
 605 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,x32\]'
 606 [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,w16\]'
 607 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,z0\.d\]'
 608 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1w {z0\.s},p0/z,\[z0\.d\]'
 609 [^ :]+:[0-9]+: Info:    did you mean this\?
 610 [^ :]+:[0-9]+: Info:            ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\]
 611 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1w {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]'
 612 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1w {z32\.s},p0/z,\[z0\.s\]'
 613 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.s},p8/z,\[z0\.s\]'
 614 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z32\.s\]'
 615 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,sp\]'
 616 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,x32\]'
 617 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,z0\.s\]'
 618 [^ :]+:[0-9]+: Error: operand mismatch -- `match p0\.h,p0/z,z0\.b,z0\.b'
 619 [^ :]+:[0-9]+: Info:    did you mean this\?
 620 [^ :]+:[0-9]+: Info:            match p0\.b, p0/z, z0\.b, z0\.b
 621 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 622 [^ :]+:[0-9]+: Info:            match p0\.h, p0/z, z0\.h, z0\.h
 623 [^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `match p16\.b,p0/z,z0\.b,z0\.b'
 624 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `match p0\.b,p8/z,z0\.b,z0\.b'
 625 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `match p0\.b,p0/z,z32\.b,z0\.b'
 626 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `match p0\.b,p0/z,z0\.b,z32\.b'
 627 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `mla z0\.h,z0\.h,z0\.h\[8\]'
 628 [^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.s,z0\.h,z0\.h\[0\]'
 629 [^ :]+:[0-9]+: Info:    did you mean this\?
 630 [^ :]+:[0-9]+: Info:            mla z0\.h, z0\.h, z0\.h\[0\]
 631 [^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.h,z0\.h,z0\.s\[0\]'
 632 [^ :]+:[0-9]+: Info:    did you mean this\?
 633 [^ :]+:[0-9]+: Info:            mla z0\.h, z0\.h, z0\.h\[0\]
 634 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mla z32\.h,z0\.h,z0\.h\[0\]'
 635 [^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mla z0\.h,z32\.h,z0\.h\[0\]'
 636 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mla z0\.h,z0\.h,z8\.h\[0\]'
 637 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mla z0\.s,z0\.s,z0\.s\[4\]'
 638 [^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.h,z0\.s,z0\.s\[0\]'
 639 [^ :]+:[0-9]+: Info:    did you mean this\?
 640 [^ :]+:[0-9]+: Info:            mla z0\.h, z0\.h, z0\.h\[0\]
 641 [^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.s,z0\.s,z0\.h\[0\]'
 642 [^ :]+:[0-9]+: Info:    did you mean this\?
 643 [^ :]+:[0-9]+: Info:            mla z0\.h, z0\.h, z0\.h\[0\]
 644 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mla z32\.s,z0\.s,z0\.s\[0\]'
 645 [^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mla z0\.s,z32\.s,z0\.s\[0\]'
 646 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mla z0\.s,z0\.s,z8\.s\[0\]'
 647 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mla z0\.d,z0\.d,z0\.d\[2\]'
 648 [^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.h,z0\.d,z0\.d\[0\]'
 649 [^ :]+:[0-9]+: Info:    did you mean this\?
 650 [^ :]+:[0-9]+: Info:            mla z0\.h, z0\.h, z0\.h\[0\]
 651 [^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.d,z0\.d,z0\.h\[0\]'
 652 [^ :]+:[0-9]+: Info:    did you mean this\?
 653 [^ :]+:[0-9]+: Info:            mla z0\.h, z0\.h, z0\.h\[0\]
 654 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mla z32\.d,z0\.d,z0\.d\[0\]'
 655 [^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mla z0\.d,z32\.d,z0\.d\[0\]'
 656 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mla z0\.d,z0\.d,z16\.d\[0\]'
 657 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `mls z0\.h,z0\.h,z0\.h\[8\]'
 658 [^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.s,z0\.h,z0\.h\[0\]'
 659 [^ :]+:[0-9]+: Info:    did you mean this\?
 660 [^ :]+:[0-9]+: Info:            mls z0\.h, z0\.h, z0\.h\[0\]
 661 [^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.h,z0\.h,z0\.s\[0\]'
 662 [^ :]+:[0-9]+: Info:    did you mean this\?
 663 [^ :]+:[0-9]+: Info:            mls z0\.h, z0\.h, z0\.h\[0\]
 664 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mls z32\.h,z0\.h,z0\.h\[0\]'
 665 [^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mls z0\.h,z32\.h,z0\.h\[0\]'
 666 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mls z0\.h,z0\.h,z8\.h\[0\]'
 667 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mls z0\.s,z0\.s,z0\.s\[4\]'
 668 [^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.h,z0\.s,z0\.s\[0\]'
 669 [^ :]+:[0-9]+: Info:    did you mean this\?
 670 [^ :]+:[0-9]+: Info:            mls z0\.h, z0\.h, z0\.h\[0\]
 671 [^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.s,z0\.s,z0\.h\[0\]'
 672 [^ :]+:[0-9]+: Info:    did you mean this\?
 673 [^ :]+:[0-9]+: Info:            mls z0\.h, z0\.h, z0\.h\[0\]
 674 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mls z32\.s,z0\.s,z0\.s\[0\]'
 675 [^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mls z0\.s,z32\.s,z0\.s\[0\]'
 676 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mls z0\.s,z0\.s,z8\.s\[0\]'
 677 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mls z0\.d,z0\.d,z0\.d\[2\]'
 678 [^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.h,z0\.d,z0\.d\[0\]'
 679 [^ :]+:[0-9]+: Info:    did you mean this\?
 680 [^ :]+:[0-9]+: Info:            mls z0\.h, z0\.h, z0\.h\[0\]
 681 [^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.d,z0\.d,z0\.h\[0\]'
 682 [^ :]+:[0-9]+: Info:    did you mean this\?
 683 [^ :]+:[0-9]+: Info:            mls z0\.h, z0\.h, z0\.h\[0\]
 684 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mls z32\.d,z0\.d,z0\.d\[0\]'
 685 [^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mls z0\.d,z32\.d,z0\.d\[0\]'
 686 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mls z0\.d,z0\.d,z16\.d\[0\]'
 687 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `mul z0\.h,z0\.h,z0\.h\[8\]'
 688 [^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.s,z0\.h,z0\.h\[0\]'
 689 [^ :]+:[0-9]+: Info:    did you mean this\?
 690 [^ :]+:[0-9]+: Info:            mul z0\.h, z0\.h, z0\.h\[0\]
 691 [^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.h,z0\.s\[0\]'
 692 [^ :]+:[0-9]+: Info:    did you mean this\?
 693 [^ :]+:[0-9]+: Info:            mul z0\.h, z0\.h, z0\.h\[0\]
 694 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.h,z0\.h,z0\.h\[0\]'
 695 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.h,z32\.h,z0\.h\[0\]'
 696 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mul z0\.h,z0\.h,z8\.h\[0\]'
 697 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mul z0\.s,z0\.s,z0\.s\[4\]'
 698 [^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.s,z0\.s\[0\]'
 699 [^ :]+:[0-9]+: Info:    did you mean this\?
 700 [^ :]+:[0-9]+: Info:            mul z0\.h, z0\.h, z0\.h\[0\]
 701 [^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.s,z0\.s,z0\.h\[0\]'
 702 [^ :]+:[0-9]+: Info:    did you mean this\?
 703 [^ :]+:[0-9]+: Info:            mul z0\.h, z0\.h, z0\.h\[0\]
 704 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.s,z0\.s,z0\.s\[0\]'
 705 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.s,z32\.s,z0\.s\[0\]'
 706 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mul z0\.s,z0\.s,z8\.s\[0\]'
 707 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mul z0\.d,z0\.d,z0\.d\[2\]'
 708 [^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.d,z0\.d\[0\]'
 709 [^ :]+:[0-9]+: Info:    did you mean this\?
 710 [^ :]+:[0-9]+: Info:            mul z0\.h, z0\.h, z0\.h\[0\]
 711 [^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.d,z0\.d,z0\.h\[0\]'
 712 [^ :]+:[0-9]+: Info:    did you mean this\?
 713 [^ :]+:[0-9]+: Info:            mul z0\.h, z0\.h, z0\.h\[0\]
 714 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.d,z0\.d,z0\.d\[0\]'
 715 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.d,z32\.d,z0\.d\[0\]'
 716 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mul z0\.d,z0\.d,z16\.d\[0\]'
 717 [^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.b,z0\.b'
 718 [^ :]+:[0-9]+: Info:    did you mean this\?
 719 [^ :]+:[0-9]+: Info:            mul z0\.b, z0\.b, z0\.b
 720 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 721 [^ :]+:[0-9]+: Info:            mul z0\.h, z0\.h, z0\.h
 722 [^ :]+:[0-9]+: Info:            mul z0\.s, z0\.s, z0\.s
 723 [^ :]+:[0-9]+: Info:            mul z0\.d, z0\.d, z0\.d
 724 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.b,z0\.b,z0\.b'
 725 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.b,z32\.b,z0\.b'
 726 [^ :]+:[0-9]+: Error: operand mismatch -- `nmatch p0\.h,p0/z,z0\.b,z0\.b'
 727 [^ :]+:[0-9]+: Info:    did you mean this\?
 728 [^ :]+:[0-9]+: Info:            nmatch p0\.b, p0/z, z0\.b, z0\.b
 729 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 730 [^ :]+:[0-9]+: Info:            nmatch p0\.h, p0/z, z0\.h, z0\.h
 731 [^ :]+:[0-9]+: Error: operand mismatch -- `nmatch p0\.b,p0/m,z0\.b,z0\.b'
 732 [^ :]+:[0-9]+: Info:    did you mean this\?
 733 [^ :]+:[0-9]+: Info:            nmatch p0\.b, p0/z, z0\.b, z0\.b
 734 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 735 [^ :]+:[0-9]+: Info:            nmatch p0\.h, p0/z, z0\.h, z0\.h
 736 [^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `nmatch p16\.b,p0/z,z0\.b,z0\.b'
 737 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `nmatch p0\.b,p8/z,z0\.b,z0\.b'
 738 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `nmatch p0\.b,p0/z,z32\.b,z0\.b'
 739 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `nmatch p0\.b,p0/z,z0\.b,z32\.b'
 740 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `nbsl z0\.d,z1\.d,z0\.d,z0\.d'
 741 [^ :]+:[0-9]+: Error: operand mismatch -- `nbsl z0\.d,z0\.d,z0\.h,z0\.d'
 742 [^ :]+:[0-9]+: Info:    did you mean this\?
 743 [^ :]+:[0-9]+: Info:            nbsl z0\.d, z0\.d, z0\.d, z0\.d
 744 [^ :]+:[0-9]+: Error: operand mismatch -- `nbsl z0\.d,z0\.h,z0\.d,z0\.d'
 745 [^ :]+:[0-9]+: Info:    did you mean this\?
 746 [^ :]+:[0-9]+: Info:            nbsl z0\.d, z0\.d, z0\.d, z0\.d
 747 [^ :]+:[0-9]+: Error: operand mismatch -- `pmul z0\.h,z0\.b,z0\.b'
 748 [^ :]+:[0-9]+: Info:    did you mean this\?
 749 [^ :]+:[0-9]+: Info:            pmul z0\.b, z0\.b, z0\.b
 750 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmul z32\.b,z0\.b,z0\.b'
 751 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmul z0\.b,z32\.b,z0\.b'
 752 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmul z0\.b,z0\.b,z32\.b'
 753 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullb z32\.q,z0\.d,z0\.d'
 754 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullb z0\.q,z32\.d,z0\.d'
 755 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullb z0\.q,z0\.d,z32\.d'
 756 [^ :]+:[0-9]+: Error: operand mismatch -- `pmullb z0\.d,z0\.d,z0\.d'
 757 [^ :]+:[0-9]+: Info:    did you mean this\?
 758 [^ :]+:[0-9]+: Info:            pmullb z0\.q, z0\.d, z0\.d
 759 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullb z32\.h,z0\.b,z0\.b'
 760 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullb z0\.h,z32\.b,z0\.b'
 761 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullb z0\.h,z0\.b,z32\.b'
 762 [^ :]+:[0-9]+: Error: operand mismatch -- `pmullb z0\.b,z0\.b,z0\.b'
 763 [^ :]+:[0-9]+: Info:    did you mean this\?
 764 [^ :]+:[0-9]+: Info:            pmullb z0\.q, z0\.d, z0\.d
 765 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullt z32\.q,z0\.d,z0\.d'
 766 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullt z0\.q,z32\.d,z0\.d'
 767 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullt z0\.q,z0\.d,z32\.d'
 768 [^ :]+:[0-9]+: Error: operand mismatch -- `pmullt z0\.d,z0\.d,z0\.d'
 769 [^ :]+:[0-9]+: Info:    did you mean this\?
 770 [^ :]+:[0-9]+: Info:            pmullt z0\.q, z0\.d, z0\.d
 771 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullt z32\.h,z0\.b,z0\.b'
 772 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullt z0\.h,z32\.b,z0\.b'
 773 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullt z0\.h,z0\.b,z32\.b'
 774 [^ :]+:[0-9]+: Error: operand mismatch -- `pmullt z0\.b,z0\.b,z0\.b'
 775 [^ :]+:[0-9]+: Info:    did you mean this\?
 776 [^ :]+:[0-9]+: Info:            pmullt z0\.q, z0\.d, z0\.d
 777 [^ :]+:[0-9]+: Error: operand mismatch -- `raddhnb z0\.h,z0\.h,z0\.h'
 778 [^ :]+:[0-9]+: Info:    did you mean this\?
 779 [^ :]+:[0-9]+: Info:            raddhnb z0\.b, z0\.h, z0\.h
 780 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 781 [^ :]+:[0-9]+: Info:            raddhnb z0\.h, z0\.s, z0\.s
 782 [^ :]+:[0-9]+: Info:            raddhnb z0\.s, z0\.d, z0\.d
 783 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `raddhnb z32\.b,z0\.h,z0\.h'
 784 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `raddhnb z0\.b,z32\.h,z0\.h'
 785 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `raddhnb z0\.b,z0\.h,z32\.h'
 786 [^ :]+:[0-9]+: Error: operand mismatch -- `raddhnt z0\.h,z0\.h,z0\.h'
 787 [^ :]+:[0-9]+: Info:    did you mean this\?
 788 [^ :]+:[0-9]+: Info:            raddhnt z0\.b, z0\.h, z0\.h
 789 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 790 [^ :]+:[0-9]+: Info:            raddhnt z0\.h, z0\.s, z0\.s
 791 [^ :]+:[0-9]+: Info:            raddhnt z0\.s, z0\.d, z0\.d
 792 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `raddhnt z32\.b,z0\.h,z0\.h'
 793 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `raddhnt z0\.b,z32\.h,z0\.h'
 794 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `raddhnt z0\.b,z0\.h,z32\.h'
 795 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `rax1 z32\.d,z0\.d,z0\.d'
 796 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rax1 z0\.d,z32\.d,z0\.d'
 797 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `rax1 z0\.d,z0\.d,z32\.d'
 798 [^ :]+:[0-9]+: Error: operand mismatch -- `rax1 z0\.d,z0\.d,z0\.h'
 799 [^ :]+:[0-9]+: Info:    did you mean this\?
 800 [^ :]+:[0-9]+: Info:            rax1 z0\.d, z0\.d, z0\.d
 801 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rshrnb z32\.b,z0\.h,#8'
 802 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rshrnb z0\.b,z32\.h,#8'
 803 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnb z0\.b,z0\.h,#9'
 804 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnb z0\.b,z0\.h,#0'
 805 [^ :]+:[0-9]+: Error: operand mismatch -- `rshrnb z0\.h,z0\.h,#8'
 806 [^ :]+:[0-9]+: Info:    did you mean this\?
 807 [^ :]+:[0-9]+: Info:            rshrnb z0\.b, z0\.h, #8
 808 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 809 [^ :]+:[0-9]+: Info:            rshrnb z0\.h, z0\.s, #8
 810 [^ :]+:[0-9]+: Info:            rshrnb z0\.s, z0\.d, #8
 811 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `rshrnb z0\.h,z0\.s,#0'
 812 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `rshrnb z0\.h,z0\.s,#17'
 813 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `rshrnb z0\.s,z0\.d,#0'
 814 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `rshrnb z0\.s,z0\.d,#33'
 815 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `rshrnt z0\.b,z1\.h,#8'
 816 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rshrnt z32\.b,z0\.h,#8'
 817 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rshrnt z0\.b,z32\.h,#8'
 818 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnt z0\.b,z0\.h,#9'
 819 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnt z0\.b,z0\.h,#0'
 820 [^ :]+:[0-9]+: Error: operand mismatch -- `rshrnt z0\.h,z0\.h,#8'
 821 [^ :]+:[0-9]+: Info:    did you mean this\?
 822 [^ :]+:[0-9]+: Info:            rshrnt z0\.b, z0\.h, #8
 823 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 824 [^ :]+:[0-9]+: Info:            rshrnt z0\.h, z0\.s, #8
 825 [^ :]+:[0-9]+: Info:            rshrnt z0\.s, z0\.d, #8
 826 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `rshrnt z0\.h,z0\.s,#0'
 827 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `rshrnt z0\.h,z0\.s,#17'
 828 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `rshrnt z0\.s,z0\.d,#0'
 829 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `rshrnt z0\.s,z0\.d,#33'
 830 [^ :]+:[0-9]+: Error: operand mismatch -- `rsubhnb z0\.h,z0\.h,z0\.h'
 831 [^ :]+:[0-9]+: Info:    did you mean this\?
 832 [^ :]+:[0-9]+: Info:            rsubhnb z0\.b, z0\.h, z0\.h
 833 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 834 [^ :]+:[0-9]+: Info:            rsubhnb z0\.h, z0\.s, z0\.s
 835 [^ :]+:[0-9]+: Info:            rsubhnb z0\.s, z0\.d, z0\.d
 836 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rsubhnb z32\.b,z0\.h,z0\.h'
 837 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rsubhnb z0\.b,z32\.h,z0\.h'
 838 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `rsubhnb z0\.b,z0\.h,z32\.h'
 839 [^ :]+:[0-9]+: Error: operand mismatch -- `rsubhnt z0\.h,z0\.h,z0\.h'
 840 [^ :]+:[0-9]+: Info:    did you mean this\?
 841 [^ :]+:[0-9]+: Info:            rsubhnt z0\.b, z0\.h, z0\.h
 842 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 843 [^ :]+:[0-9]+: Info:            rsubhnt z0\.h, z0\.s, z0\.s
 844 [^ :]+:[0-9]+: Info:            rsubhnt z0\.s, z0\.d, z0\.d
 845 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rsubhnt z32\.b,z0\.h,z0\.h'
 846 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rsubhnt z0\.b,z32\.h,z0\.h'
 847 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `rsubhnt z0\.b,z0\.h,z32\.h'
 848 [^ :]+:[0-9]+: Error: operand mismatch -- `saba z0\.h,z0\.b,z0\.b'
 849 [^ :]+:[0-9]+: Info:    did you mean this\?
 850 [^ :]+:[0-9]+: Info:            saba z0\.b, z0\.b, z0\.b
 851 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 852 [^ :]+:[0-9]+: Info:            saba z0\.h, z0\.h, z0\.h
 853 [^ :]+:[0-9]+: Info:            saba z0\.s, z0\.s, z0\.s
 854 [^ :]+:[0-9]+: Info:            saba z0\.d, z0\.d, z0\.d
 855 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saba z32\.b,z0\.b,z0\.b'
 856 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saba z0\.b,z32\.b,z0\.b'
 857 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saba z0\.b,z0\.b,z32\.b'
 858 [^ :]+:[0-9]+: Error: operand mismatch -- `sabalb z0\.b,z0\.b,z0\.b'
 859 [^ :]+:[0-9]+: Info:    did you mean this\?
 860 [^ :]+:[0-9]+: Info:            sabalb z0\.h, z0\.b, z0\.b
 861 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 862 [^ :]+:[0-9]+: Info:            sabalb z0\.s, z0\.h, z0\.h
 863 [^ :]+:[0-9]+: Info:            sabalb z0\.d, z0\.s, z0\.s
 864 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabalb z32\.h,z0\.b,z0\.b'
 865 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabalb z0\.h,z32\.b,z0\.b'
 866 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabalb z0\.h,z0\.b,z32\.b'
 867 [^ :]+:[0-9]+: Error: operand mismatch -- `sabalt z0\.b,z0\.b,z0\.b'
 868 [^ :]+:[0-9]+: Info:    did you mean this\?
 869 [^ :]+:[0-9]+: Info:            sabalt z0\.h, z0\.b, z0\.b
 870 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 871 [^ :]+:[0-9]+: Info:            sabalt z0\.s, z0\.h, z0\.h
 872 [^ :]+:[0-9]+: Info:            sabalt z0\.d, z0\.s, z0\.s
 873 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabalt z32\.h,z0\.b,z0\.b'
 874 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabalt z0\.h,z32\.b,z0\.b'
 875 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabalt z0\.h,z0\.b,z32\.b'
 876 [^ :]+:[0-9]+: Error: operand mismatch -- `sabdlb z0\.b,z0\.b,z0\.b'
 877 [^ :]+:[0-9]+: Info:    did you mean this\?
 878 [^ :]+:[0-9]+: Info:            sabdlb z0\.h, z0\.b, z0\.b
 879 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 880 [^ :]+:[0-9]+: Info:            sabdlb z0\.s, z0\.h, z0\.h
 881 [^ :]+:[0-9]+: Info:            sabdlb z0\.d, z0\.s, z0\.s
 882 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabdlb z32\.h,z0\.b,z0\.b'
 883 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabdlb z0\.h,z32\.b,z0\.b'
 884 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabdlb z0\.h,z0\.b,z32\.b'
 885 [^ :]+:[0-9]+: Error: operand mismatch -- `sabdlt z0\.b,z0\.b,z0\.b'
 886 [^ :]+:[0-9]+: Info:    did you mean this\?
 887 [^ :]+:[0-9]+: Info:            sabdlt z0\.h, z0\.b, z0\.b
 888 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 889 [^ :]+:[0-9]+: Info:            sabdlt z0\.s, z0\.h, z0\.h
 890 [^ :]+:[0-9]+: Info:            sabdlt z0\.d, z0\.s, z0\.s
 891 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabdlt z32\.h,z0\.b,z0\.b'
 892 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabdlt z0\.h,z32\.b,z0\.b'
 893 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabdlt z0\.h,z0\.b,z32\.b'
 894 [^ :]+:[0-9]+: Error: operand mismatch -- `sadalp z0\.b,p0/m,z0\.b'
 895 [^ :]+:[0-9]+: Info:    did you mean this\?
 896 [^ :]+:[0-9]+: Info:            sadalp z0\.h, p0/m, z0\.b
 897 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 898 [^ :]+:[0-9]+: Info:            sadalp z0\.s, p0/m, z0\.h
 899 [^ :]+:[0-9]+: Info:            sadalp z0\.d, p0/m, z0\.s
 900 [^ :]+:[0-9]+: Error: operand mismatch -- `sadalp z0\.h,p0/z,z0\.b'
 901 [^ :]+:[0-9]+: Info:    did you mean this\?
 902 [^ :]+:[0-9]+: Info:            sadalp z0\.h, p0/m, z0\.b
 903 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 904 [^ :]+:[0-9]+: Info:            sadalp z0\.s, p0/m, z0\.h
 905 [^ :]+:[0-9]+: Info:            sadalp z0\.d, p0/m, z0\.s
 906 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sadalp z0\.h,p8/m,z0\.b'
 907 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sadalp z32\.h,p0/m,z0\.b'
 908 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sadalp z0\.h,p0/m,z32\.b'
 909 [^ :]+:[0-9]+: Error: operand mismatch -- `saddlb z0\.b,z0\.b,z0\.b'
 910 [^ :]+:[0-9]+: Info:    did you mean this\?
 911 [^ :]+:[0-9]+: Info:            saddlb z0\.h, z0\.b, z0\.b
 912 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 913 [^ :]+:[0-9]+: Info:            saddlb z0\.s, z0\.h, z0\.h
 914 [^ :]+:[0-9]+: Info:            saddlb z0\.d, z0\.s, z0\.s
 915 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddlb z32\.h,z0\.b,z0\.b'
 916 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddlb z0\.h,z32\.b,z0\.b'
 917 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddlb z0\.h,z0\.b,z32\.b'
 918 [^ :]+:[0-9]+: Error: operand mismatch -- `saddlbt z0\.b,z0\.b,z0\.b'
 919 [^ :]+:[0-9]+: Info:    did you mean this\?
 920 [^ :]+:[0-9]+: Info:            saddlbt z0\.h, z0\.b, z0\.b
 921 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 922 [^ :]+:[0-9]+: Info:            saddlbt z0\.s, z0\.h, z0\.h
 923 [^ :]+:[0-9]+: Info:            saddlbt z0\.d, z0\.s, z0\.s
 924 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddlbt z32\.h,z0\.b,z0\.b'
 925 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddlbt z0\.h,z32\.b,z0\.b'
 926 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddlbt z0\.h,z0\.b,z32\.b'
 927 [^ :]+:[0-9]+: Error: operand mismatch -- `saddlt z0\.b,z0\.b,z0\.b'
 928 [^ :]+:[0-9]+: Info:    did you mean this\?
 929 [^ :]+:[0-9]+: Info:            saddlt z0\.h, z0\.b, z0\.b
 930 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 931 [^ :]+:[0-9]+: Info:            saddlt z0\.s, z0\.h, z0\.h
 932 [^ :]+:[0-9]+: Info:            saddlt z0\.d, z0\.s, z0\.s
 933 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddlt z32\.h,z0\.b,z0\.b'
 934 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddlt z0\.h,z32\.b,z0\.b'
 935 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddlt z0\.h,z0\.b,z32\.b'
 936 [^ :]+:[0-9]+: Error: operand mismatch -- `saddwb z0\.b,z0\.h,z0\.b'
 937 [^ :]+:[0-9]+: Info:    did you mean this\?
 938 [^ :]+:[0-9]+: Info:            saddwb z0\.h, z0\.h, z0\.b
 939 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 940 [^ :]+:[0-9]+: Info:            saddwb z0\.s, z0\.s, z0\.h
 941 [^ :]+:[0-9]+: Info:            saddwb z0\.d, z0\.d, z0\.s
 942 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddwb z32\.h,z0\.h,z0\.b'
 943 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddwb z0\.h,z32\.h,z0\.b'
 944 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddwb z0\.h,z0\.h,z32\.b'
 945 [^ :]+:[0-9]+: Error: operand mismatch -- `saddwt z0\.b,z0\.h,z0\.b'
 946 [^ :]+:[0-9]+: Info:    did you mean this\?
 947 [^ :]+:[0-9]+: Info:            saddwt z0\.h, z0\.h, z0\.b
 948 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 949 [^ :]+:[0-9]+: Info:            saddwt z0\.s, z0\.s, z0\.h
 950 [^ :]+:[0-9]+: Info:            saddwt z0\.d, z0\.d, z0\.s
 951 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddwt z32\.h,z0\.h,z0\.b'
 952 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddwt z0\.h,z32\.h,z0\.b'
 953 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddwt z0\.h,z0\.h,z32\.b'
 954 [^ :]+:[0-9]+: Error: operand mismatch -- `sbclb z0\.d,z0\.s,z0\.s'
 955 [^ :]+:[0-9]+: Info:    did you mean this\?
 956 [^ :]+:[0-9]+: Info:            sbclb z0\.s, z0\.s, z0\.s
 957 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 958 [^ :]+:[0-9]+: Info:            sbclb z0\.d, z0\.d, z0\.d
 959 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sbclb z32\.s,z0\.s,z0\.s'
 960 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sbclb z0\.s,z32\.s,z0\.s'
 961 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sbclb z0\.s,z0\.s,z32\.s'
 962 [^ :]+:[0-9]+: Error: operand mismatch -- `sbclt z0\.d,z0\.s,z0\.s'
 963 [^ :]+:[0-9]+: Info:    did you mean this\?
 964 [^ :]+:[0-9]+: Info:            sbclt z0\.s, z0\.s, z0\.s
 965 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 966 [^ :]+:[0-9]+: Info:            sbclt z0\.d, z0\.d, z0\.d
 967 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sbclt z32\.s,z0\.s,z0\.s'
 968 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sbclt z0\.s,z32\.s,z0\.s'
 969 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sbclt z0\.s,z0\.s,z32\.s'
 970 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `shadd z0\.b,p0/m,z1\.b,z0\.b'
 971 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shadd z32\.b,p0/m,z0\.b,z0\.b'
 972 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `shadd z0\.b,p8/m,z0\.b,z0\.b'
 973 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `shadd z0\.b,p0/m,z32\.b,z0\.b'
 974 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `shadd z0\.b,p0/m,z0\.b,z32\.b'
 975 [^ :]+:[0-9]+: Error: operand mismatch -- `shadd z0\.h,p0/m,z0\.b,z0\.b'
 976 [^ :]+:[0-9]+: Info:    did you mean this\?
 977 [^ :]+:[0-9]+: Info:            shadd z0\.b, p0/m, z0\.b, z0\.b
 978 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 979 [^ :]+:[0-9]+: Info:            shadd z0\.h, p0/m, z0\.h, z0\.h
 980 [^ :]+:[0-9]+: Info:            shadd z0\.s, p0/m, z0\.s, z0\.s
 981 [^ :]+:[0-9]+: Info:            shadd z0\.d, p0/m, z0\.d, z0\.d
 982 [^ :]+:[0-9]+: Error: operand mismatch -- `shadd z0\.b,p0/z,z0\.b,z0\.b'
 983 [^ :]+:[0-9]+: Info:    did you mean this\?
 984 [^ :]+:[0-9]+: Info:            shadd z0\.b, p0/m, z0\.b, z0\.b
 985 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 986 [^ :]+:[0-9]+: Info:            shadd z0\.h, p0/m, z0\.h, z0\.h
 987 [^ :]+:[0-9]+: Info:            shadd z0\.s, p0/m, z0\.s, z0\.s
 988 [^ :]+:[0-9]+: Info:            shadd z0\.d, p0/m, z0\.d, z0\.d
 989 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shrnb z32\.b,z0\.h,#8'
 990 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `shrnb z0\.b,z32\.h,#8'
 991 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnb z0\.b,z0\.h,#9'
 992 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnb z0\.b,z0\.h,#0'
 993 [^ :]+:[0-9]+: Error: operand mismatch -- `shrnb z0\.h,z0\.h,#8'
 994 [^ :]+:[0-9]+: Info:    did you mean this\?
 995 [^ :]+:[0-9]+: Info:            shrnb z0\.b, z0\.h, #8
 996 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 997 [^ :]+:[0-9]+: Info:            shrnb z0\.h, z0\.s, #8
 998 [^ :]+:[0-9]+: Info:            shrnb z0\.s, z0\.d, #8
 999 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `shrnb z0\.h,z0\.s,#0'
1000 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `shrnb z0\.h,z0\.s,#17'
1001 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnb z0\.s,z0\.d,#0'
1002 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnb z0\.s,z0\.d,#33'
1003 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `shrnt z0\.b,z1\.h,#8'
1004 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shrnt z32\.b,z0\.h,#8'
1005 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `shrnt z0\.b,z32\.h,#8'
1006 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnt z0\.b,z0\.h,#9'
1007 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnt z0\.b,z0\.h,#0'
1008 [^ :]+:[0-9]+: Error: operand mismatch -- `shrnt z0\.h,z0\.h,#8'
1009 [^ :]+:[0-9]+: Info:    did you mean this\?
1010 [^ :]+:[0-9]+: Info:            shrnt z0\.b, z0\.h, #8
1011 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1012 [^ :]+:[0-9]+: Info:            shrnt z0\.h, z0\.s, #8
1013 [^ :]+:[0-9]+: Info:            shrnt z0\.s, z0\.d, #8
1014 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `shrnt z0\.h,z0\.s,#0'
1015 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `shrnt z0\.h,z0\.s,#17'
1016 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnt z0\.s,z0\.d,#0'
1017 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnt z0\.s,z0\.d,#33'
1018 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `shsub z0\.b,p0/m,z1\.b,z0\.b'
1019 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shsub z32\.b,p0/m,z0\.b,z0\.b'
1020 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `shsub z0\.b,p8/m,z0\.b,z0\.b'
1021 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `shsub z0\.b,p0/m,z32\.b,z0\.b'
1022 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `shsub z0\.b,p0/m,z0\.b,z32\.b'
1023 [^ :]+:[0-9]+: Error: operand mismatch -- `shsub z0\.h,p0/m,z0\.b,z0\.b'
1024 [^ :]+:[0-9]+: Info:    did you mean this\?
1025 [^ :]+:[0-9]+: Info:            shsub z0\.b, p0/m, z0\.b, z0\.b
1026 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1027 [^ :]+:[0-9]+: Info:            shsub z0\.h, p0/m, z0\.h, z0\.h
1028 [^ :]+:[0-9]+: Info:            shsub z0\.s, p0/m, z0\.s, z0\.s
1029 [^ :]+:[0-9]+: Info:            shsub z0\.d, p0/m, z0\.d, z0\.d
1030 [^ :]+:[0-9]+: Error: operand mismatch -- `shsub z0\.b,p0/z,z0\.b,z0\.b'
1031 [^ :]+:[0-9]+: Info:    did you mean this\?
1032 [^ :]+:[0-9]+: Info:            shsub z0\.b, p0/m, z0\.b, z0\.b
1033 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1034 [^ :]+:[0-9]+: Info:            shsub z0\.h, p0/m, z0\.h, z0\.h
1035 [^ :]+:[0-9]+: Info:            shsub z0\.s, p0/m, z0\.s, z0\.s
1036 [^ :]+:[0-9]+: Info:            shsub z0\.d, p0/m, z0\.d, z0\.d
1037 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `shsubr z0\.b,p0/m,z1\.b,z0\.b'
1038 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shsubr z32\.b,p0/m,z0\.b,z0\.b'
1039 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `shsubr z0\.b,p8/m,z0\.b,z0\.b'
1040 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `shsubr z0\.b,p0/m,z32\.b,z0\.b'
1041 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `shsubr z0\.b,p0/m,z0\.b,z32\.b'
1042 [^ :]+:[0-9]+: Error: operand mismatch -- `shsubr z0\.h,p0/m,z0\.b,z0\.b'
1043 [^ :]+:[0-9]+: Info:    did you mean this\?
1044 [^ :]+:[0-9]+: Info:            shsubr z0\.b, p0/m, z0\.b, z0\.b
1045 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1046 [^ :]+:[0-9]+: Info:            shsubr z0\.h, p0/m, z0\.h, z0\.h
1047 [^ :]+:[0-9]+: Info:            shsubr z0\.s, p0/m, z0\.s, z0\.s
1048 [^ :]+:[0-9]+: Info:            shsubr z0\.d, p0/m, z0\.d, z0\.d
1049 [^ :]+:[0-9]+: Error: operand mismatch -- `shsubr z0\.b,p0/z,z0\.b,z0\.b'
1050 [^ :]+:[0-9]+: Info:    did you mean this\?
1051 [^ :]+:[0-9]+: Info:            shsubr z0\.b, p0/m, z0\.b, z0\.b
1052 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1053 [^ :]+:[0-9]+: Info:            shsubr z0\.h, p0/m, z0\.h, z0\.h
1054 [^ :]+:[0-9]+: Info:            shsubr z0\.s, p0/m, z0\.s, z0\.s
1055 [^ :]+:[0-9]+: Info:            shsubr z0\.d, p0/m, z0\.d, z0\.d
1056 [^ :]+:[0-9]+: Error: operand mismatch -- `sli z0\.h,z0\.b,#0'
1057 [^ :]+:[0-9]+: Info:    did you mean this\?
1058 [^ :]+:[0-9]+: Info:            sli z0\.b, z0\.b, #0
1059 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1060 [^ :]+:[0-9]+: Info:            sli z0\.h, z0\.h, #0
1061 [^ :]+:[0-9]+: Info:            sli z0\.s, z0\.s, #0
1062 [^ :]+:[0-9]+: Info:            sli z0\.d, z0\.d, #0
1063 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sli z32\.b,z0\.b,#0'
1064 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sli z0\.b,z32\.b,#0'
1065 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `sli z0\.b,z0\.b,#8'
1066 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `sli z0\.h,z0\.h,#16'
1067 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `sli z0\.s,z0\.s,#32'
1068 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 3 -- `sli z0\.d,z0\.d,#64'
1069 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sm4e z0\.s,z0\.s,z1\.s'
1070 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `sm4e z1\.s,z0\.s,z0\.s'
1071 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sm4e z32\.s,z0\.s,z0\.s'
1072 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sm4e z0\.s,z32\.s,z0\.s'
1073 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sm4e z0\.s,z0\.s,z32\.s'
1074 [^ :]+:[0-9]+: Error: operand mismatch -- `sm4e z0\.s,z0\.s,z0\.d'
1075 [^ :]+:[0-9]+: Info:    did you mean this\?
1076 [^ :]+:[0-9]+: Info:            sm4e z0\.s, z0\.s, z0\.s
1077 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sm4ekey z32\.s,z0\.s,z0\.s'
1078 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sm4ekey z0\.s,z32\.s,z0\.s'
1079 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sm4ekey z0\.s,z0\.s,z32\.s'
1080 [^ :]+:[0-9]+: Error: operand mismatch -- `sm4ekey z0\.s,z0\.s,z0\.h'
1081 [^ :]+:[0-9]+: Info:    did you mean this\?
1082 [^ :]+:[0-9]+: Info:            sm4ekey z0\.s, z0\.s, z0\.s
1083 [^ :]+:[0-9]+: Error: operand mismatch -- `smaxp z0\.h,p0/m,z0\.b,z0\.b'
1084 [^ :]+:[0-9]+: Info:    did you mean this\?
1085 [^ :]+:[0-9]+: Info:            smaxp z0\.b, p0/m, z0\.b, z0\.b
1086 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1087 [^ :]+:[0-9]+: Info:            smaxp z0\.h, p0/m, z0\.h, z0\.h
1088 [^ :]+:[0-9]+: Info:            smaxp z0\.s, p0/m, z0\.s, z0\.s
1089 [^ :]+:[0-9]+: Info:            smaxp z0\.d, p0/m, z0\.d, z0\.d
1090 [^ :]+:[0-9]+: Error: operand mismatch -- `smaxp z0\.b,p0/z,z0\.b,z0\.b'
1091 [^ :]+:[0-9]+: Info:    did you mean this\?
1092 [^ :]+:[0-9]+: Info:            smaxp z0\.b, p0/m, z0\.b, z0\.b
1093 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1094 [^ :]+:[0-9]+: Info:            smaxp z0\.h, p0/m, z0\.h, z0\.h
1095 [^ :]+:[0-9]+: Info:            smaxp z0\.s, p0/m, z0\.s, z0\.s
1096 [^ :]+:[0-9]+: Info:            smaxp z0\.d, p0/m, z0\.d, z0\.d
1097 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `smaxp z1\.b,p0/m,z0\.b,z0\.b'
1098 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smaxp z32\.b,p0/m,z0\.b,z0\.b'
1099 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `smaxp z0\.b,p0/m,z32\.b,z0\.b'
1100 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `smaxp z0\.b,p0/m,z0\.b,z32\.b'
1101 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `smaxp z0\.b,p8/m,z0\.b,z0\.b'
1102 [^ :]+:[0-9]+: Error: operand mismatch -- `sminp z0\.h,p0/m,z0\.b,z0\.b'
1103 [^ :]+:[0-9]+: Info:    did you mean this\?
1104 [^ :]+:[0-9]+: Info:            sminp z0\.b, p0/m, z0\.b, z0\.b
1105 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1106 [^ :]+:[0-9]+: Info:            sminp z0\.h, p0/m, z0\.h, z0\.h
1107 [^ :]+:[0-9]+: Info:            sminp z0\.s, p0/m, z0\.s, z0\.s
1108 [^ :]+:[0-9]+: Info:            sminp z0\.d, p0/m, z0\.d, z0\.d
1109 [^ :]+:[0-9]+: Error: operand mismatch -- `sminp z0\.b,p0/z,z0\.b,z0\.b'
1110 [^ :]+:[0-9]+: Info:    did you mean this\?
1111 [^ :]+:[0-9]+: Info:            sminp z0\.b, p0/m, z0\.b, z0\.b
1112 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1113 [^ :]+:[0-9]+: Info:            sminp z0\.h, p0/m, z0\.h, z0\.h
1114 [^ :]+:[0-9]+: Info:            sminp z0\.s, p0/m, z0\.s, z0\.s
1115 [^ :]+:[0-9]+: Info:            sminp z0\.d, p0/m, z0\.d, z0\.d
1116 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sminp z1\.b,p0/m,z0\.b,z0\.b'
1117 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sminp z32\.b,p0/m,z0\.b,z0\.b'
1118 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sminp z0\.b,p0/m,z32\.b,z0\.b'
1119 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sminp z0\.b,p0/m,z0\.b,z32\.b'
1120 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sminp z0\.b,p8/m,z0\.b,z0\.b'
1121 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalb z32\.s,z0\.h,z0\.h\[0\]'
1122 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalb z0\.s,z32\.h,z0\.h\[0\]'
1123 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlalb z0\.s,z0\.h,z8\.h\[0\]'
1124 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlalb z0\.s,z0\.h,z0\.h\[8\]'
1125 [^ :]+:[0-9]+: Error: operand mismatch -- `smlalb z0\.h,z0\.h,z0\.h\[0\]'
1126 [^ :]+:[0-9]+: Info:    did you mean this\?
1127 [^ :]+:[0-9]+: Info:            smlalb z0\.d, z0\.s, z0\.s\[0\]
1128 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalb z32\.d,z0\.s,z0\.s\[0\]'
1129 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalb z0\.d,z32\.s,z0\.s\[0\]'
1130 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlalb z0\.d,z0\.s,z16\.s\[0\]'
1131 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlalb z0\.d,z0\.s,z0\.s\[4\]'
1132 [^ :]+:[0-9]+: Error: operand mismatch -- `smlalb z0\.s,z0\.s,z0\.s\[0\]'
1133 [^ :]+:[0-9]+: Info:    did you mean this\?
1134 [^ :]+:[0-9]+: Info:            smlalb z0\.d, z0\.s, z0\.s\[0\]
1135 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalb z32\.h,z0\.b,z0\.b'
1136 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalb z0\.h,z32\.b,z0\.b'
1137 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlalb z0\.h,z0\.b,z32\.b'
1138 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlalb z0\.s,z0\.h,z0\.x'
1139 [^ :]+:[0-9]+: Error: operand mismatch -- `smlalb z0\.h,z0\.b,z0\.h'
1140 [^ :]+:[0-9]+: Info:    did you mean this\?
1141 [^ :]+:[0-9]+: Info:            smlalb z0\.h, z0\.b, z0\.b
1142 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1143 [^ :]+:[0-9]+: Info:            smlalb z0\.s, z0\.h, z0\.h
1144 [^ :]+:[0-9]+: Info:            smlalb z0\.d, z0\.s, z0\.s
1145 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalt z32\.s,z0\.h,z0\.h\[0\]'
1146 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalt z0\.s,z32\.h,z0\.h\[0\]'
1147 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlalt z0\.s,z0\.h,z8\.h\[0\]'
1148 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlalt z0\.s,z0\.h,z0\.h\[8\]'
1149 [^ :]+:[0-9]+: Error: operand mismatch -- `smlalt z0\.h,z0\.h,z0\.h\[0\]'
1150 [^ :]+:[0-9]+: Info:    did you mean this\?
1151 [^ :]+:[0-9]+: Info:            smlalt z0\.d, z0\.s, z0\.s\[0\]
1152 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalt z32\.d,z0\.s,z0\.s\[0\]'
1153 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalt z0\.d,z32\.s,z0\.s\[0\]'
1154 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlalt z0\.d,z0\.s,z16\.s\[0\]'
1155 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlalt z0\.d,z0\.s,z0\.s\[4\]'
1156 [^ :]+:[0-9]+: Error: operand mismatch -- `smlalt z0\.s,z0\.s,z0\.s\[0\]'
1157 [^ :]+:[0-9]+: Info:    did you mean this\?
1158 [^ :]+:[0-9]+: Info:            smlalt z0\.d, z0\.s, z0\.s\[0\]
1159 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalt z32\.h,z0\.b,z0\.b'
1160 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalt z0\.h,z32\.b,z0\.b'
1161 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlalt z0\.h,z0\.b,z32\.b'
1162 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlalt z0\.s,z0\.h,z0\.x'
1163 [^ :]+:[0-9]+: Error: operand mismatch -- `smlalt z0\.h,z0\.b,z0\.h'
1164 [^ :]+:[0-9]+: Info:    did you mean this\?
1165 [^ :]+:[0-9]+: Info:            smlalt z0\.h, z0\.b, z0\.b
1166 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1167 [^ :]+:[0-9]+: Info:            smlalt z0\.s, z0\.h, z0\.h
1168 [^ :]+:[0-9]+: Info:            smlalt z0\.d, z0\.s, z0\.s
1169 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslb z32\.s,z0\.h,z0\.h\[0\]'
1170 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslb z0\.s,z32\.h,z0\.h\[0\]'
1171 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlslb z0\.s,z0\.h,z8\.h\[0\]'
1172 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlslb z0\.s,z0\.h,z0\.h\[8\]'
1173 [^ :]+:[0-9]+: Error: operand mismatch -- `smlslb z0\.h,z0\.h,z0\.h\[0\]'
1174 [^ :]+:[0-9]+: Info:    did you mean this\?
1175 [^ :]+:[0-9]+: Info:            smlslb z0\.d, z0\.s, z0\.s\[0\]
1176 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslb z32\.d,z0\.s,z0\.s\[0\]'
1177 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslb z0\.d,z32\.s,z0\.s\[0\]'
1178 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlslb z0\.d,z0\.s,z16\.s\[0\]'
1179 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlslb z0\.d,z0\.s,z0\.s\[4\]'
1180 [^ :]+:[0-9]+: Error: operand mismatch -- `smlslb z0\.s,z0\.s,z0\.s\[0\]'
1181 [^ :]+:[0-9]+: Info:    did you mean this\?
1182 [^ :]+:[0-9]+: Info:            smlslb z0\.d, z0\.s, z0\.s\[0\]
1183 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslb z32\.h,z0\.b,z0\.b'
1184 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslb z0\.h,z32\.b,z0\.b'
1185 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlslb z0\.h,z0\.b,z32\.b'
1186 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlslb z0\.s,z0\.h,z0\.x'
1187 [^ :]+:[0-9]+: Error: operand mismatch -- `smlslb z0\.h,z0\.b,z0\.h'
1188 [^ :]+:[0-9]+: Info:    did you mean this\?
1189 [^ :]+:[0-9]+: Info:            smlslb z0\.h, z0\.b, z0\.b
1190 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1191 [^ :]+:[0-9]+: Info:            smlslb z0\.s, z0\.h, z0\.h
1192 [^ :]+:[0-9]+: Info:            smlslb z0\.d, z0\.s, z0\.s
1193 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslt z32\.s,z0\.h,z0\.h\[0\]'
1194 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslt z0\.s,z32\.h,z0\.h\[0\]'
1195 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlslt z0\.s,z0\.h,z8\.h\[0\]'
1196 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlslt z0\.s,z0\.h,z0\.h\[8\]'
1197 [^ :]+:[0-9]+: Error: operand mismatch -- `smlslt z0\.h,z0\.h,z0\.h\[0\]'
1198 [^ :]+:[0-9]+: Info:    did you mean this\?
1199 [^ :]+:[0-9]+: Info:            smlslt z0\.d, z0\.s, z0\.s\[0\]
1200 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslt z32\.d,z0\.s,z0\.s\[0\]'
1201 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslt z0\.d,z32\.s,z0\.s\[0\]'
1202 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlslt z0\.d,z0\.s,z16\.s\[0\]'
1203 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlslt z0\.d,z0\.s,z0\.s\[4\]'
1204 [^ :]+:[0-9]+: Error: operand mismatch -- `smlslt z0\.s,z0\.s,z0\.s\[0\]'
1205 [^ :]+:[0-9]+: Info:    did you mean this\?
1206 [^ :]+:[0-9]+: Info:            smlslt z0\.d, z0\.s, z0\.s\[0\]
1207 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslt z32\.h,z0\.b,z0\.b'
1208 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslt z0\.h,z32\.b,z0\.b'
1209 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlslt z0\.h,z0\.b,z32\.b'
1210 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlslt z0\.s,z0\.h,z0\.x'
1211 [^ :]+:[0-9]+: Error: operand mismatch -- `smlslt z0\.h,z0\.b,z0\.h'
1212 [^ :]+:[0-9]+: Info:    did you mean this\?
1213 [^ :]+:[0-9]+: Info:            smlslt z0\.h, z0\.b, z0\.b
1214 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1215 [^ :]+:[0-9]+: Info:            smlslt z0\.s, z0\.h, z0\.h
1216 [^ :]+:[0-9]+: Info:            smlslt z0\.d, z0\.s, z0\.s
1217 [^ :]+:[0-9]+: Error: operand mismatch -- `smulh z0\.h,z0\.b,z0\.b'
1218 [^ :]+:[0-9]+: Info:    did you mean this\?
1219 [^ :]+:[0-9]+: Info:            smulh z0\.b, z0\.b, z0\.b
1220 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1221 [^ :]+:[0-9]+: Info:            smulh z0\.h, z0\.h, z0\.h
1222 [^ :]+:[0-9]+: Info:            smulh z0\.s, z0\.s, z0\.s
1223 [^ :]+:[0-9]+: Info:            smulh z0\.d, z0\.d, z0\.d
1224 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smulh z32\.b,z0\.b,z0\.b'
1225 [^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `smulh z0\.b,z32\.b,z0\.b'
1226 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `smulh z0\.b,z0\.b,z32\.b'
1227 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullb z32\.s,z0\.h,z0\.h\[0\]'
1228 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullb z0\.s,z32\.h,z0\.h\[0\]'
1229 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smullb z0\.s,z0\.h,z8\.h\[0\]'
1230 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smullb z0\.s,z0\.h,z0\.h\[8\]'
1231 [^ :]+:[0-9]+: Error: operand mismatch -- `smullb z0\.h,z0\.h,z0\.h\[0\]'
1232 [^ :]+:[0-9]+: Info:    did you mean this\?
1233 [^ :]+:[0-9]+: Info:            smullb z0\.d, z0\.s, z0\.s\[0\]
1234 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullb z32\.d,z0\.s,z0\.s\[0\]'
1235 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullb z0\.d,z32\.s,z0\.s\[0\]'
1236 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smullb z0\.d,z0\.s,z16\.s\[0\]'
1237 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smullb z0\.d,z0\.s,z0\.s\[4\]'
1238 [^ :]+:[0-9]+: Error: operand mismatch -- `smullb z0\.s,z0\.s,z0\.s\[0\]'
1239 [^ :]+:[0-9]+: Info:    did you mean this\?
1240 [^ :]+:[0-9]+: Info:            smullb z0\.d, z0\.s, z0\.s\[0\]
1241 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullb z32\.h,z0\.b,z0\.b'
1242 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullb z0\.h,z32\.b,z0\.b'
1243 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smullb z0\.h,z0\.b,z32\.b'
1244 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smullb z0\.s,z0\.h,z0\.x'
1245 [^ :]+:[0-9]+: Error: operand mismatch -- `smullb z0\.h,z0\.b,z0\.h'
1246 [^ :]+:[0-9]+: Info:    did you mean this\?
1247 [^ :]+:[0-9]+: Info:            smullb z0\.h, z0\.b, z0\.b
1248 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1249 [^ :]+:[0-9]+: Info:            smullb z0\.s, z0\.h, z0\.h
1250 [^ :]+:[0-9]+: Info:            smullb z0\.d, z0\.s, z0\.s
1251 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullt z32\.s,z0\.h,z0\.h\[0\]'
1252 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullt z0\.s,z32\.h,z0\.h\[0\]'
1253 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smullt z0\.s,z0\.h,z8\.h\[0\]'
1254 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smullt z0\.s,z0\.h,z0\.h\[8\]'
1255 [^ :]+:[0-9]+: Error: operand mismatch -- `smullt z0\.h,z0\.h,z0\.h\[0\]'
1256 [^ :]+:[0-9]+: Info:    did you mean this\?
1257 [^ :]+:[0-9]+: Info:            smullt z0\.d, z0\.s, z0\.s\[0\]
1258 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullt z32\.d,z0\.s,z0\.s\[0\]'
1259 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullt z0\.d,z32\.s,z0\.s\[0\]'
1260 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smullt z0\.d,z0\.s,z16\.s\[0\]'
1261 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smullt z0\.d,z0\.s,z0\.s\[4\]'
1262 [^ :]+:[0-9]+: Error: operand mismatch -- `smullt z0\.s,z0\.s,z0\.s\[0\]'
1263 [^ :]+:[0-9]+: Info:    did you mean this\?
1264 [^ :]+:[0-9]+: Info:            smullt z0\.d, z0\.s, z0\.s\[0\]
1265 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullt z32\.h,z0\.b,z0\.b'
1266 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullt z0\.h,z32\.b,z0\.b'
1267 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smullt z0\.h,z0\.b,z32\.b'
1268 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smullt z0\.s,z0\.h,z0\.x'
1269 [^ :]+:[0-9]+: Error: operand mismatch -- `smullt z0\.h,z0\.b,z0\.h'
1270 [^ :]+:[0-9]+: Info:    did you mean this\?
1271 [^ :]+:[0-9]+: Info:            smullt z0\.h, z0\.b, z0\.b
1272 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1273 [^ :]+:[0-9]+: Info:            smullt z0\.s, z0\.h, z0\.h
1274 [^ :]+:[0-9]+: Info:            smullt z0\.d, z0\.s, z0\.s
1275 [^ :]+:[0-9]+: Error: invalid register list at operand 3 -- `splice z0\.b,p0,{z0\.b,z2\.b}'
1276 [^ :]+:[0-9]+: Error: operand mismatch -- `splice z0\.h,p0,{z0\.b,z1\.b}'
1277 [^ :]+:[0-9]+: Info:    did you mean this\?
1278 [^ :]+:[0-9]+: Info:            splice z0\.b, p0, {z0\.b, z1\.b}
1279 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1280 [^ :]+:[0-9]+: Info:            splice z0\.h, p0, {z0\.h, z1\.h}
1281 [^ :]+:[0-9]+: Info:            splice z0\.s, p0, {z0\.s, z1\.s}
1282 [^ :]+:[0-9]+: Info:            splice z0\.d, p0, {z0\.d, z1\.d}
1283 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.h,z1\.b}'
1284 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.b,z1\.h}'
1285 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `splice z32\.b,p0,{z0\.b,z1\.b}'
1286 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `splice z0\.b,p8,{z0\.b,z1\.b}'
1287 [^ :]+:[0-9]+: Error: invalid register list at operand 3 -- `splice z0\.b,p0,{z31\.b,z1\.b}'
1288 [^ :]+:[0-9]+: Error: operand 3 must be a list of SVE vector registers -- `splice z0\.b,p0,{z31\.b,z32\.b}'
1289 [^ :]+:[0-9]+: Error: operand 3 must be a list of SVE vector registers -- `splice z0\.b,p0,{z32\.b,z1\.b}'
1290 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqabs z32\.b,p0/m,z0\.b'
1291 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqabs z0\.b,p8/m,z0\.b'
1292 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqabs z0\.b,p0/m,z32\.b'
1293 [^ :]+:[0-9]+: Error: operand mismatch -- `sqabs z0\.b,p0/m,z0\.h'
1294 [^ :]+:[0-9]+: Info:    did you mean this\?
1295 [^ :]+:[0-9]+: Info:            sqabs z0\.b, p0/m, z0\.b
1296 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1297 [^ :]+:[0-9]+: Info:            sqabs z0\.h, p0/m, z0\.h
1298 [^ :]+:[0-9]+: Info:            sqabs z0\.s, p0/m, z0\.s
1299 [^ :]+:[0-9]+: Info:            sqabs z0\.d, p0/m, z0\.d
1300 [^ :]+:[0-9]+: Error: operand mismatch -- `sqabs z0\.b,p0/z,z0\.b'
1301 [^ :]+:[0-9]+: Info:    did you mean this\?
1302 [^ :]+:[0-9]+: Info:            sqabs z0\.b, p0/m, z0\.b
1303 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1304 [^ :]+:[0-9]+: Info:            sqabs z0\.h, p0/m, z0\.h
1305 [^ :]+:[0-9]+: Info:            sqabs z0\.s, p0/m, z0\.s
1306 [^ :]+:[0-9]+: Info:            sqabs z0\.d, p0/m, z0\.d
1307 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqadd z32\.b,p0/m,z0\.b,z0\.b'
1308 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqadd z0\.b,p0/m,z32\.b,z0\.b'
1309 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqadd z0\.b,p0/m,z0\.b,z32\.b'
1310 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqadd z0\.b,p0/m,z1\.b,z0\.b'
1311 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqadd z0\.b,p8/m,z0\.b,z0\.b'
1312 [^ :]+:[0-9]+: Error: operand mismatch -- `sqadd z0\.h,p0/m,z0\.b,z0\.b'
1313 [^ :]+:[0-9]+: Info:    did you mean this\?
1314 [^ :]+:[0-9]+: Info:            sqadd z0\.b, p0/m, z0\.b, z0\.b
1315 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1316 [^ :]+:[0-9]+: Info:            sqadd z0\.h, p0/m, z0\.h, z0\.h
1317 [^ :]+:[0-9]+: Info:            sqadd z0\.s, p0/m, z0\.s, z0\.s
1318 [^ :]+:[0-9]+: Info:            sqadd z0\.d, p0/m, z0\.d, z0\.d
1319 [^ :]+:[0-9]+: Error: operand mismatch -- `sqadd z0\.b,p0/z,z0\.b,z0\.b'
1320 [^ :]+:[0-9]+: Info:    did you mean this\?
1321 [^ :]+:[0-9]+: Info:            sqadd z0\.b, p0/m, z0\.b, z0\.b
1322 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1323 [^ :]+:[0-9]+: Info:            sqadd z0\.h, p0/m, z0\.h, z0\.h
1324 [^ :]+:[0-9]+: Info:            sqadd z0\.s, p0/m, z0\.s, z0\.s
1325 [^ :]+:[0-9]+: Info:            sqadd z0\.d, p0/m, z0\.d, z0\.d
1326 [^ :]+:[0-9]+: Error: rotate expected to be 90 or 270 at operand 4 -- `sqcadd z0\.b,z0\.b,z0\.b,#180'
1327 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `sqcadd z0\.b,z1\.b,z0\.b,#90'
1328 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqcadd z32\.b,z0\.b,z0\.b,#90'
1329 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqcadd z0\.b,z32\.b,z0\.b,#90'
1330 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqcadd z0\.b,z0\.b,z32\.b,#90'
1331 [^ :]+:[0-9]+: Error: operand mismatch -- `sqcadd z0\.b,z0\.b,z0\.h,#90'
1332 [^ :]+:[0-9]+: Info:    did you mean this\?
1333 [^ :]+:[0-9]+: Info:            sqcadd z0\.b, z0\.b, z0\.b, #90
1334 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1335 [^ :]+:[0-9]+: Info:            sqcadd z0\.h, z0\.h, z0\.h, #90
1336 [^ :]+:[0-9]+: Info:            sqcadd z0\.s, z0\.s, z0\.s, #90
1337 [^ :]+:[0-9]+: Info:            sqcadd z0\.d, z0\.d, z0\.d, #90
1338 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalb z32\.s,z0\.h,z0\.h\[0\]'
1339 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalb z0\.s,z32\.h,z0\.h\[0\]'
1340 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlalb z0\.s,z0\.h,z8\.h\[0\]'
1341 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlalb z0\.s,z0\.h,z0\.h\[8\]'
1342 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalb z0\.h,z0\.h,z0\.h\[0\]'
1343 [^ :]+:[0-9]+: Info:    did you mean this\?
1344 [^ :]+:[0-9]+: Info:            sqdmlalb z0\.d, z0\.s, z0\.s\[0\]
1345 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalb z32\.d,z0\.s,z0\.s\[0\]'
1346 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalb z0\.d,z32\.s,z0\.s\[0\]'
1347 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlalb z0\.d,z0\.s,z16\.s\[0\]'
1348 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlalb z0\.d,z0\.s,z0\.s\[4\]'
1349 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalb z0\.s,z0\.s,z0\.s\[0\]'
1350 [^ :]+:[0-9]+: Info:    did you mean this\?
1351 [^ :]+:[0-9]+: Info:            sqdmlalb z0\.d, z0\.s, z0\.s\[0\]
1352 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalb z32\.h,z0\.b,z0\.b'
1353 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalb z0\.h,z32\.b,z0\.b'
1354 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlalb z0\.h,z0\.b,z32\.b'
1355 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlalb z0\.s,z0\.h,z0\.x'
1356 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalb z0\.h,z0\.b,z0\.h'
1357 [^ :]+:[0-9]+: Info:    did you mean this\?
1358 [^ :]+:[0-9]+: Info:            sqdmlalb z0\.h, z0\.b, z0\.b
1359 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1360 [^ :]+:[0-9]+: Info:            sqdmlalb z0\.s, z0\.h, z0\.h
1361 [^ :]+:[0-9]+: Info:            sqdmlalb z0\.d, z0\.s, z0\.s
1362 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalbt z32\.h,z0\.b,z0\.b'
1363 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalbt z0\.h,z32\.b,z0\.b'
1364 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqdmlalbt z0\.h,z0\.b,z32\.b'
1365 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlalbt z0\.s,z0\.h,z0\.x'
1366 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalbt z0\.h,z0\.b,z0\.h'
1367 [^ :]+:[0-9]+: Info:    did you mean this\?
1368 [^ :]+:[0-9]+: Info:            sqdmlalbt z0\.h, z0\.b, z0\.b
1369 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1370 [^ :]+:[0-9]+: Info:            sqdmlalbt z0\.s, z0\.h, z0\.h
1371 [^ :]+:[0-9]+: Info:            sqdmlalbt z0\.d, z0\.s, z0\.s
1372 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalt z32\.s,z0\.h,z0\.h\[0\]'
1373 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalt z0\.s,z32\.h,z0\.h\[0\]'
1374 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlalt z0\.s,z0\.h,z8\.h\[0\]'
1375 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlalt z0\.s,z0\.h,z0\.h\[8\]'
1376 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalt z0\.h,z0\.h,z0\.h\[0\]'
1377 [^ :]+:[0-9]+: Info:    did you mean this\?
1378 [^ :]+:[0-9]+: Info:            sqdmlalt z0\.d, z0\.s, z0\.s\[0\]
1379 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalt z32\.d,z0\.s,z0\.s\[0\]'
1380 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalt z0\.d,z32\.s,z0\.s\[0\]'
1381 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlalt z0\.d,z0\.s,z16\.s\[0\]'
1382 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlalt z0\.d,z0\.s,z0\.s\[4\]'
1383 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalt z0\.s,z0\.s,z0\.s\[0\]'
1384 [^ :]+:[0-9]+: Info:    did you mean this\?
1385 [^ :]+:[0-9]+: Info:            sqdmlalt z0\.d, z0\.s, z0\.s\[0\]
1386 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalt z32\.h,z0\.b,z0\.b'
1387 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalt z0\.h,z32\.b,z0\.b'
1388 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlalt z0\.h,z0\.b,z32\.b'
1389 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlalt z0\.s,z0\.h,z0\.x'
1390 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalt z0\.h,z0\.b,z0\.h'
1391 [^ :]+:[0-9]+: Info:    did you mean this\?
1392 [^ :]+:[0-9]+: Info:            sqdmlalt z0\.h, z0\.b, z0\.b
1393 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1394 [^ :]+:[0-9]+: Info:            sqdmlalt z0\.s, z0\.h, z0\.h
1395 [^ :]+:[0-9]+: Info:            sqdmlalt z0\.d, z0\.s, z0\.s
1396 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslb z32\.s,z0\.h,z0\.h\[0\]'
1397 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslb z0\.s,z32\.h,z0\.h\[0\]'
1398 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlslb z0\.s,z0\.h,z8\.h\[0\]'
1399 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlslb z0\.s,z0\.h,z0\.h\[8\]'
1400 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslb z0\.h,z0\.h,z0\.h\[0\]'
1401 [^ :]+:[0-9]+: Info:    did you mean this\?
1402 [^ :]+:[0-9]+: Info:            sqdmlslb z0\.d, z0\.s, z0\.s\[0\]
1403 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslb z32\.d,z0\.s,z0\.s\[0\]'
1404 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslb z0\.d,z32\.s,z0\.s\[0\]'
1405 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlslb z0\.d,z0\.s,z16\.s\[0\]'
1406 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlslb z0\.d,z0\.s,z0\.s\[4\]'
1407 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslb z0\.s,z0\.s,z0\.s\[0\]'
1408 [^ :]+:[0-9]+: Info:    did you mean this\?
1409 [^ :]+:[0-9]+: Info:            sqdmlslb z0\.d, z0\.s, z0\.s\[0\]
1410 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslb z32\.h,z0\.b,z0\.b'
1411 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslb z0\.h,z32\.b,z0\.b'
1412 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlslb z0\.h,z0\.b,z32\.b'
1413 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlslb z0\.s,z0\.h,z0\.x'
1414 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslb z0\.h,z0\.b,z0\.h'
1415 [^ :]+:[0-9]+: Info:    did you mean this\?
1416 [^ :]+:[0-9]+: Info:            sqdmlslb z0\.h, z0\.b, z0\.b
1417 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1418 [^ :]+:[0-9]+: Info:            sqdmlslb z0\.s, z0\.h, z0\.h
1419 [^ :]+:[0-9]+: Info:            sqdmlslb z0\.d, z0\.s, z0\.s
1420 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslbt z32\.h,z0\.b,z0\.b'
1421 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslbt z0\.h,z32\.b,z0\.b'
1422 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqdmlslbt z0\.h,z0\.b,z32\.b'
1423 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlslbt z0\.s,z0\.h,z0\.x'
1424 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslbt z0\.h,z0\.b,z0\.h'
1425 [^ :]+:[0-9]+: Info:    did you mean this\?
1426 [^ :]+:[0-9]+: Info:            sqdmlslbt z0\.h, z0\.b, z0\.b
1427 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1428 [^ :]+:[0-9]+: Info:            sqdmlslbt z0\.s, z0\.h, z0\.h
1429 [^ :]+:[0-9]+: Info:            sqdmlslbt z0\.d, z0\.s, z0\.s
1430 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslt z32\.s,z0\.h,z0\.h\[0\]'
1431 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslt z0\.s,z32\.h,z0\.h\[0\]'
1432 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlslt z0\.s,z0\.h,z8\.h\[0\]'
1433 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlslt z0\.s,z0\.h,z0\.h\[8\]'
1434 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslt z0\.h,z0\.h,z0\.h\[0\]'
1435 [^ :]+:[0-9]+: Info:    did you mean this\?
1436 [^ :]+:[0-9]+: Info:            sqdmlslt z0\.d, z0\.s, z0\.s\[0\]
1437 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslt z32\.d,z0\.s,z0\.s\[0\]'
1438 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslt z0\.d,z32\.s,z0\.s\[0\]'
1439 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlslt z0\.d,z0\.s,z16\.s\[0\]'
1440 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlslt z0\.d,z0\.s,z0\.s\[4\]'
1441 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslt z0\.s,z0\.s,z0\.s\[0\]'
1442 [^ :]+:[0-9]+: Info:    did you mean this\?
1443 [^ :]+:[0-9]+: Info:            sqdmlslt z0\.d, z0\.s, z0\.s\[0\]
1444 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslt z32\.h,z0\.b,z0\.b'
1445 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslt z0\.h,z32\.b,z0\.b'
1446 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlslt z0\.h,z0\.b,z32\.b'
1447 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlslt z0\.s,z0\.h,z0\.x'
1448 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslt z0\.h,z0\.b,z0\.h'
1449 [^ :]+:[0-9]+: Info:    did you mean this\?
1450 [^ :]+:[0-9]+: Info:            sqdmlslt z0\.h, z0\.b, z0\.b
1451 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1452 [^ :]+:[0-9]+: Info:            sqdmlslt z0\.s, z0\.h, z0\.h
1453 [^ :]+:[0-9]+: Info:            sqdmlslt z0\.d, z0\.s, z0\.s
1454 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.h,z0\.h,z0\.h\[0\]'
1455 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.h,z32\.h,z0\.h\[0\]'
1456 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmulh z0\.h,z0\.h,z8\.h\[0\]'
1457 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmulh z0\.h,z0\.h,z0\.h\[8\]'
1458 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.s,z0\.h,z0\.h\[0\]'
1459 [^ :]+:[0-9]+: Info:    did you mean this\?
1460 [^ :]+:[0-9]+: Info:            sqdmulh z0\.h, z0\.h, z0\.h\[0\]
1461 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.h,z0\.h,z0\.s\[0\]'
1462 [^ :]+:[0-9]+: Info:    did you mean this\?
1463 [^ :]+:[0-9]+: Info:            sqdmulh z0\.h, z0\.h, z0\.h\[0\]
1464 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.s,z0\.s,z0\.s\[0\]'
1465 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.s,z32\.s,z0\.s\[0\]'
1466 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmulh z0\.s,z0\.s,z8\.s\[0\]'
1467 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmulh z0\.s,z0\.s,z0\.s\[4\]'
1468 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.s,z0\.h,z0\.s\[0\]'
1469 [^ :]+:[0-9]+: Info:    did you mean this\?
1470 [^ :]+:[0-9]+: Info:            sqdmulh z0\.h, z0\.h, z0\.h\[0\]
1471 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.s,z0\.s,z0\.h\[0\]'
1472 [^ :]+:[0-9]+: Info:    did you mean this\?
1473 [^ :]+:[0-9]+: Info:            sqdmulh z0\.h, z0\.h, z0\.h\[0\]
1474 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.d,z0\.d,z0\.d\[0\]'
1475 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.d,z32\.d,z0\.d\[0\]'
1476 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmulh z0\.d,z0\.d,z16\.d\[0\]'
1477 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqdmulh z0\.d,z0\.d,z0\.d\[2\]'
1478 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.d,z0\.h,z0\.d\[0\]'
1479 [^ :]+:[0-9]+: Info:    did you mean this\?
1480 [^ :]+:[0-9]+: Info:            sqdmulh z0\.h, z0\.h, z0\.h\[0\]
1481 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.d,z0\.d,z0\.h\[0\]'
1482 [^ :]+:[0-9]+: Info:    did you mean this\?
1483 [^ :]+:[0-9]+: Info:            sqdmulh z0\.h, z0\.h, z0\.h\[0\]
1484 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.h,z0\.b,z0\.b'
1485 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.h,z32\.b,z0\.b'
1486 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmulh z0\.h,z0\.b,z32\.b'
1487 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmulh z0\.s,z0\.h,z0\.x'
1488 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.h,z0\.b,z0\.h'
1489 [^ :]+:[0-9]+: Info:    did you mean this\?
1490 [^ :]+:[0-9]+: Info:            sqdmulh z0\.h, z0\.h, z0\.h
1491 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1492 [^ :]+:[0-9]+: Info:            sqdmulh z0\.b, z0\.b, z0\.b
1493 [^ :]+:[0-9]+: Info:            sqdmulh z0\.s, z0\.s, z0\.s
1494 [^ :]+:[0-9]+: Info:            sqdmulh z0\.d, z0\.d, z0\.d
1495 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullb z32\.s,z0\.h,z0\.h\[0\]'
1496 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullb z0\.s,z32\.h,z0\.h\[0\]'
1497 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmullb z0\.s,z0\.h,z8\.h\[0\]'
1498 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmullb z0\.s,z0\.h,z0\.h\[8\]'
1499 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullb z0\.h,z0\.h,z0\.h\[0\]'
1500 [^ :]+:[0-9]+: Info:    did you mean this\?
1501 [^ :]+:[0-9]+: Info:            sqdmullb z0\.d, z0\.s, z0\.s\[0\]
1502 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullb z32\.d,z0\.s,z0\.s\[0\]'
1503 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullb z0\.d,z32\.s,z0\.s\[0\]'
1504 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmullb z0\.d,z0\.s,z16\.s\[0\]'
1505 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmullb z0\.d,z0\.s,z0\.s\[4\]'
1506 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullb z0\.s,z0\.s,z0\.s\[0\]'
1507 [^ :]+:[0-9]+: Info:    did you mean this\?
1508 [^ :]+:[0-9]+: Info:            sqdmullb z0\.d, z0\.s, z0\.s\[0\]
1509 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullb z32\.h,z0\.b,z0\.b'
1510 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullb z0\.h,z32\.b,z0\.b'
1511 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmullb z0\.h,z0\.b,z32\.b'
1512 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmullb z0\.s,z0\.h,z0\.x'
1513 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullb z0\.h,z0\.b,z0\.h'
1514 [^ :]+:[0-9]+: Info:    did you mean this\?
1515 [^ :]+:[0-9]+: Info:            sqdmullb z0\.h, z0\.b, z0\.b
1516 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1517 [^ :]+:[0-9]+: Info:            sqdmullb z0\.s, z0\.h, z0\.h
1518 [^ :]+:[0-9]+: Info:            sqdmullb z0\.d, z0\.s, z0\.s
1519 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullt z32\.s,z0\.h,z0\.h\[0\]'
1520 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullt z0\.s,z32\.h,z0\.h\[0\]'
1521 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmullt z0\.s,z0\.h,z8\.h\[0\]'
1522 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmullt z0\.s,z0\.h,z0\.h\[8\]'
1523 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullt z0\.h,z0\.h,z0\.h\[0\]'
1524 [^ :]+:[0-9]+: Info:    did you mean this\?
1525 [^ :]+:[0-9]+: Info:            sqdmullt z0\.d, z0\.s, z0\.s\[0\]
1526 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullt z32\.d,z0\.s,z0\.s\[0\]'
1527 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullt z0\.d,z32\.s,z0\.s\[0\]'
1528 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmullt z0\.d,z0\.s,z16\.s\[0\]'
1529 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmullt z0\.d,z0\.s,z0\.s\[4\]'
1530 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullt z0\.s,z0\.s,z0\.s\[0\]'
1531 [^ :]+:[0-9]+: Info:    did you mean this\?
1532 [^ :]+:[0-9]+: Info:            sqdmullt z0\.d, z0\.s, z0\.s\[0\]
1533 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullt z32\.h,z0\.b,z0\.b'
1534 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullt z0\.h,z32\.b,z0\.b'
1535 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmullt z0\.h,z0\.b,z32\.b'
1536 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmullt z0\.s,z0\.h,z0\.x'
1537 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullt z0\.h,z0\.b,z0\.h'
1538 [^ :]+:[0-9]+: Info:    did you mean this\?
1539 [^ :]+:[0-9]+: Info:            sqdmullt z0\.h, z0\.b, z0\.b
1540 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1541 [^ :]+:[0-9]+: Info:            sqdmullt z0\.s, z0\.h, z0\.h
1542 [^ :]+:[0-9]+: Info:            sqdmullt z0\.d, z0\.s, z0\.s
1543 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqneg z32\.b,p0/m,z0\.b'
1544 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqneg z0\.b,p8/m,z0\.b'
1545 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqneg z0\.b,p0/m,z32\.b'
1546 [^ :]+:[0-9]+: Error: operand mismatch -- `sqneg z0\.b,p0/m,z0\.h'
1547 [^ :]+:[0-9]+: Info:    did you mean this\?
1548 [^ :]+:[0-9]+: Info:            sqneg z0\.b, p0/m, z0\.b
1549 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1550 [^ :]+:[0-9]+: Info:            sqneg z0\.h, p0/m, z0\.h
1551 [^ :]+:[0-9]+: Info:            sqneg z0\.s, p0/m, z0\.s
1552 [^ :]+:[0-9]+: Info:            sqneg z0\.d, p0/m, z0\.d
1553 [^ :]+:[0-9]+: Error: operand mismatch -- `sqneg z0\.b,p0/z,z0\.b'
1554 [^ :]+:[0-9]+: Info:    did you mean this\?
1555 [^ :]+:[0-9]+: Info:            sqneg z0\.b, p0/m, z0\.b
1556 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1557 [^ :]+:[0-9]+: Info:            sqneg z0\.h, p0/m, z0\.h
1558 [^ :]+:[0-9]+: Info:            sqneg z0\.s, p0/m, z0\.s
1559 [^ :]+:[0-9]+: Info:            sqneg z0\.d, p0/m, z0\.d
1560 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdcmlah z32\.h,z0\.h,z0\.h\[0\],#0'
1561 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdcmlah z0\.h,z32\.h,z0\.h\[0\],#0'
1562 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdcmlah z0\.h,z0\.h,z8\.h\[0\],#0'
1563 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdcmlah z0\.h,z0\.h,z0\.h\[4\],#0'
1564 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.h,z0\.h,z0\.h\[0\],#1'
1565 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.h,z0\.h,z0\.h\[0\],#360'
1566 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.h,z0\.h,z0\.s\[0\],#0'
1567 [^ :]+:[0-9]+: Info:    did you mean this\?
1568 [^ :]+:[0-9]+: Info:            sqrdcmlah z0\.s, z0\.s, z0\.s\[0\], #0
1569 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.h,z0\.s,z0\.h\[0\],#0'
1570 [^ :]+:[0-9]+: Info:    did you mean this\?
1571 [^ :]+:[0-9]+: Info:            sqrdcmlah z0\.s, z0\.s, z0\.s\[0\], #0
1572 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdcmlah z32\.s,z0\.s,z0\.s\[0\],#0'
1573 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdcmlah z0\.s,z32\.s,z0\.s\[0\],#0'
1574 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdcmlah z0\.s,z0\.s,z16\.s\[0\],#0'
1575 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdcmlah z0\.s,z0\.s,z0\.s\[2\],#0'
1576 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.s,z0\.s,z0\.s\[0\],#1'
1577 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.s,z0\.s,z0\.s\[0\],#360'
1578 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.s,z0\.s,z0\.h\[0\],#0'
1579 [^ :]+:[0-9]+: Info:    did you mean this\?
1580 [^ :]+:[0-9]+: Info:            sqrdcmlah z0\.s, z0\.s, z0\.s\[0\], #0
1581 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.s,z0\.h,z0\.s\[0\],#0'
1582 [^ :]+:[0-9]+: Info:    did you mean this\?
1583 [^ :]+:[0-9]+: Info:            sqrdcmlah z0\.s, z0\.s, z0\.s\[0\], #0
1584 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdcmlah z32\.b,z0\.b,z0\.b,#0'
1585 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdcmlah z0\.b,z32\.b,z0\.b,#0'
1586 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdcmlah z0\.b,z0\.b,z32\.b,#0'
1587 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.b,z0\.b,z0\.b,#1'
1588 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.b,z0\.b,z0\.b,#360'
1589 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.b,z0\.b,z0\.h,#0'
1590 [^ :]+:[0-9]+: Info:    did you mean this\?
1591 [^ :]+:[0-9]+: Info:            sqrdcmlah z0\.b, z0\.b, z0\.b, #0
1592 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1593 [^ :]+:[0-9]+: Info:            sqrdcmlah z0\.h, z0\.h, z0\.h, #0
1594 [^ :]+:[0-9]+: Info:            sqrdcmlah z0\.s, z0\.s, z0\.s, #0
1595 [^ :]+:[0-9]+: Info:            sqrdcmlah z0\.d, z0\.d, z0\.d, #0
1596 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.h,z0\.h,z0\.h\[0\]'
1597 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.h,z32\.h,z0\.h\[0\]'
1598 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlah z0\.h,z0\.h,z8\.h\[0\]'
1599 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqrdmlah z0\.h,z0\.h,z0\.h\[8\]'
1600 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.h,z0\.h\[0\]'
1601 [^ :]+:[0-9]+: Info:    did you mean this\?
1602 [^ :]+:[0-9]+: Info:            sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
1603 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.h,z0\.h,z0\.s\[0\]'
1604 [^ :]+:[0-9]+: Info:    did you mean this\?
1605 [^ :]+:[0-9]+: Info:            sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
1606 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.s,z0\.s,z0\.s\[0\]'
1607 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.s,z32\.s,z0\.s\[0\]'
1608 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlah z0\.s,z0\.s,z8\.s\[0\]'
1609 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmlah z0\.s,z0\.s,z0\.s\[4\]'
1610 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.h,z0\.s\[0\]'
1611 [^ :]+:[0-9]+: Info:    did you mean this\?
1612 [^ :]+:[0-9]+: Info:            sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
1613 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.s,z0\.h\[0\]'
1614 [^ :]+:[0-9]+: Info:    did you mean this\?
1615 [^ :]+:[0-9]+: Info:            sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
1616 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.d,z0\.d,z0\.d\[0\]'
1617 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.d,z32\.d,z0\.d\[0\]'
1618 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmlah z0\.d,z0\.d,z16\.d\[0\]'
1619 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmlah z0\.d,z0\.d,z0\.d\[2\]'
1620 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.d,z0\.h,z0\.d\[0\]'
1621 [^ :]+:[0-9]+: Info:    did you mean this\?
1622 [^ :]+:[0-9]+: Info:            sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
1623 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.d,z0\.d,z0\.h\[0\]'
1624 [^ :]+:[0-9]+: Info:    did you mean this\?
1625 [^ :]+:[0-9]+: Info:            sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
1626 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.h,z0\.b,z0\.b'
1627 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.h,z32\.b,z0\.b'
1628 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdmlah z0\.h,z0\.b,z32\.b'
1629 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqrdmlah z0\.s,z0\.h,z0\.x'
1630 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.h,z0\.b,z0\.h'
1631 [^ :]+:[0-9]+: Info:    did you mean this\?
1632 [^ :]+:[0-9]+: Info:            sqrdmlah z0\.h, z0\.h, z0\.h
1633 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1634 [^ :]+:[0-9]+: Info:            sqrdmlah z0\.b, z0\.b, z0\.b
1635 [^ :]+:[0-9]+: Info:            sqrdmlah z0\.s, z0\.s, z0\.s
1636 [^ :]+:[0-9]+: Info:            sqrdmlah z0\.d, z0\.d, z0\.d
1637 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.h,z0\.h,z0\.h\[0\]'
1638 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.h,z32\.h,z0\.h\[0\]'
1639 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlsh z0\.h,z0\.h,z8\.h\[0\]'
1640 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqrdmlsh z0\.h,z0\.h,z0\.h\[8\]'
1641 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.h,z0\.h\[0\]'
1642 [^ :]+:[0-9]+: Info:    did you mean this\?
1643 [^ :]+:[0-9]+: Info:            sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
1644 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.h,z0\.h,z0\.s\[0\]'
1645 [^ :]+:[0-9]+: Info:    did you mean this\?
1646 [^ :]+:[0-9]+: Info:            sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
1647 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.s,z0\.s,z0\.s\[0\]'
1648 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.s,z32\.s,z0\.s\[0\]'
1649 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlsh z0\.s,z0\.s,z8\.s\[0\]'
1650 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmlsh z0\.s,z0\.s,z0\.s\[4\]'
1651 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.h,z0\.s\[0\]'
1652 [^ :]+:[0-9]+: Info:    did you mean this\?
1653 [^ :]+:[0-9]+: Info:            sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
1654 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.s,z0\.h\[0\]'
1655 [^ :]+:[0-9]+: Info:    did you mean this\?
1656 [^ :]+:[0-9]+: Info:            sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
1657 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.d,z0\.d,z0\.d\[0\]'
1658 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.d,z32\.d,z0\.d\[0\]'
1659 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmlsh z0\.d,z0\.d,z16\.d\[0\]'
1660 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmlsh z0\.d,z0\.d,z0\.d\[2\]'
1661 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.d,z0\.h,z0\.d\[0\]'
1662 [^ :]+:[0-9]+: Info:    did you mean this\?
1663 [^ :]+:[0-9]+: Info:            sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
1664 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.d,z0\.d,z0\.h\[0\]'
1665 [^ :]+:[0-9]+: Info:    did you mean this\?
1666 [^ :]+:[0-9]+: Info:            sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
1667 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.h,z0\.b,z0\.b'
1668 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.h,z32\.b,z0\.b'
1669 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdmlsh z0\.h,z0\.b,z32\.b'
1670 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqrdmlsh z0\.s,z0\.h,z0\.x'
1671 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.h,z0\.b,z0\.h'
1672 [^ :]+:[0-9]+: Info:    did you mean this\?
1673 [^ :]+:[0-9]+: Info:            sqrdmlsh z0\.h, z0\.h, z0\.h
1674 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1675 [^ :]+:[0-9]+: Info:            sqrdmlsh z0\.b, z0\.b, z0\.b
1676 [^ :]+:[0-9]+: Info:            sqrdmlsh z0\.s, z0\.s, z0\.s
1677 [^ :]+:[0-9]+: Info:            sqrdmlsh z0\.d, z0\.d, z0\.d
1678 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.h,z0\.h,z0\.h\[0\]'
1679 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.h,z32\.h,z0\.h\[0\]'
1680 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmulh z0\.h,z0\.h,z8\.h\[0\]'
1681 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqrdmulh z0\.h,z0\.h,z0\.h\[8\]'
1682 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.s,z0\.h,z0\.h\[0\]'
1683 [^ :]+:[0-9]+: Info:    did you mean this\?
1684 [^ :]+:[0-9]+: Info:            sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
1685 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.h,z0\.h,z0\.s\[0\]'
1686 [^ :]+:[0-9]+: Info:    did you mean this\?
1687 [^ :]+:[0-9]+: Info:            sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
1688 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.s,z0\.s,z0\.s\[0\]'
1689 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.s,z32\.s,z0\.s\[0\]'
1690 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmulh z0\.s,z0\.s,z8\.s\[0\]'
1691 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmulh z0\.s,z0\.s,z0\.s\[4\]'
1692 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.s,z0\.h,z0\.s\[0\]'
1693 [^ :]+:[0-9]+: Info:    did you mean this\?
1694 [^ :]+:[0-9]+: Info:            sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
1695 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.s,z0\.s,z0\.h\[0\]'
1696 [^ :]+:[0-9]+: Info:    did you mean this\?
1697 [^ :]+:[0-9]+: Info:            sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
1698 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.d,z0\.d,z0\.d\[0\]'
1699 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.d,z32\.d,z0\.d\[0\]'
1700 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmulh z0\.d,z0\.d,z16\.d\[0\]'
1701 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmulh z0\.d,z0\.d,z0\.d\[2\]'
1702 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.d,z0\.h,z0\.d\[0\]'
1703 [^ :]+:[0-9]+: Info:    did you mean this\?
1704 [^ :]+:[0-9]+: Info:            sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
1705 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.d,z0\.d,z0\.h\[0\]'
1706 [^ :]+:[0-9]+: Info:    did you mean this\?
1707 [^ :]+:[0-9]+: Info:            sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
1708 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.h,z0\.b,z0\.b'
1709 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.h,z32\.b,z0\.b'
1710 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdmulh z0\.h,z0\.b,z32\.b'
1711 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqrdmulh z0\.s,z0\.h,z0\.x'
1712 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.h,z0\.b,z0\.h'
1713 [^ :]+:[0-9]+: Info:    did you mean this\?
1714 [^ :]+:[0-9]+: Info:            sqrdmulh z0\.h, z0\.h, z0\.h
1715 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1716 [^ :]+:[0-9]+: Info:            sqrdmulh z0\.b, z0\.b, z0\.b
1717 [^ :]+:[0-9]+: Info:            sqrdmulh z0\.s, z0\.s, z0\.s
1718 [^ :]+:[0-9]+: Info:            sqrdmulh z0\.d, z0\.d, z0\.d
1719 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqrshl z32\.b,p0/m,z0\.b,z0\.b'
1720 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqrshl z0\.b,p0/m,z32\.b,z0\.b'
1721 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqrshl z0\.b,p0/m,z0\.b,z32\.b'
1722 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqrshl z0\.b,p0/m,z1\.b,z0\.b'
1723 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqrshl z0\.b,p8/m,z0\.b,z0\.b'
1724 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrshl z0\.h,p0/m,z0\.b,z0\.b'
1725 [^ :]+:[0-9]+: Info:    did you mean this\?
1726 [^ :]+:[0-9]+: Info:            sqrshl z0\.b, p0/m, z0\.b, z0\.b
1727 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1728 [^ :]+:[0-9]+: Info:            sqrshl z0\.h, p0/m, z0\.h, z0\.h
1729 [^ :]+:[0-9]+: Info:            sqrshl z0\.s, p0/m, z0\.s, z0\.s
1730 [^ :]+:[0-9]+: Info:            sqrshl z0\.d, p0/m, z0\.d, z0\.d
1731 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrshl z0\.b,p0/z,z0\.b,z0\.b'
1732 [^ :]+:[0-9]+: Info:    did you mean this\?
1733 [^ :]+:[0-9]+: Info:            sqrshl z0\.b, p0/m, z0\.b, z0\.b
1734 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1735 [^ :]+:[0-9]+: Info:            sqrshl z0\.h, p0/m, z0\.h, z0\.h
1736 [^ :]+:[0-9]+: Info:            sqrshl z0\.s, p0/m, z0\.s, z0\.s
1737 [^ :]+:[0-9]+: Info:            sqrshl z0\.d, p0/m, z0\.d, z0\.d
1738 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshlr z32\.b,p0/m,z0\.b,z0\.b'
1739 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqrshlr z0\.b,p0/m,z32\.b,z0\.b'
1740 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqrshlr z0\.b,p0/m,z0\.b,z32\.b'
1741 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqrshlr z0\.b,p0/m,z1\.b,z0\.b'
1742 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqrshlr z0\.b,p8/m,z0\.b,z0\.b'
1743 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrshlr z0\.h,p0/m,z0\.b,z0\.b'
1744 [^ :]+:[0-9]+: Info:    did you mean this\?
1745 [^ :]+:[0-9]+: Info:            sqrshlr z0\.b, p0/m, z0\.b, z0\.b
1746 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1747 [^ :]+:[0-9]+: Info:            sqrshlr z0\.h, p0/m, z0\.h, z0\.h
1748 [^ :]+:[0-9]+: Info:            sqrshlr z0\.s, p0/m, z0\.s, z0\.s
1749 [^ :]+:[0-9]+: Info:            sqrshlr z0\.d, p0/m, z0\.d, z0\.d
1750 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrshlr z0\.b,p0/z,z0\.b,z0\.b'
1751 [^ :]+:[0-9]+: Info:    did you mean this\?
1752 [^ :]+:[0-9]+: Info:            sqrshlr z0\.b, p0/m, z0\.b, z0\.b
1753 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1754 [^ :]+:[0-9]+: Info:            sqrshlr z0\.h, p0/m, z0\.h, z0\.h
1755 [^ :]+:[0-9]+: Info:            sqrshlr z0\.s, p0/m, z0\.s, z0\.s
1756 [^ :]+:[0-9]+: Info:            sqrshlr z0\.d, p0/m, z0\.d, z0\.d
1757 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrnb z32\.b,z0\.h,#8'
1758 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrnb z0\.b,z32\.h,#8'
1759 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnb z0\.b,z0\.h,#9'
1760 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnb z0\.b,z0\.h,#0'
1761 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrnb z0\.h,z0\.h,#8'
1762 [^ :]+:[0-9]+: Info:    did you mean this\?
1763 [^ :]+:[0-9]+: Info:            sqrshrnb z0\.b, z0\.h, #8
1764 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1765 [^ :]+:[0-9]+: Info:            sqrshrnb z0\.h, z0\.s, #8
1766 [^ :]+:[0-9]+: Info:            sqrshrnb z0\.s, z0\.d, #8
1767 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrnb z0\.h,z0\.s,#0'
1768 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrnb z0\.h,z0\.s,#17'
1769 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnb z0\.s,z0\.d,#0'
1770 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnb z0\.s,z0\.d,#33'
1771 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqrshrnt z0\.b,z0\.h,#1'
1772 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrnt z32\.b,z0\.h,#8'
1773 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrnt z0\.b,z32\.h,#8'
1774 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnt z0\.b,z0\.h,#9'
1775 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnt z0\.b,z0\.h,#0'
1776 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrnt z0\.h,z0\.h,#8'
1777 [^ :]+:[0-9]+: Info:    did you mean this\?
1778 [^ :]+:[0-9]+: Info:            sqrshrnt z0\.b, z0\.h, #8
1779 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1780 [^ :]+:[0-9]+: Info:            sqrshrnt z0\.h, z0\.s, #8
1781 [^ :]+:[0-9]+: Info:            sqrshrnt z0\.s, z0\.d, #8
1782 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrnt z0\.h,z0\.s,#0'
1783 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrnt z0\.h,z0\.s,#17'
1784 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnt z0\.s,z0\.d,#0'
1785 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnt z0\.s,z0\.d,#33'
1786 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrunb z32\.b,z0\.h,#8'
1787 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrunb z0\.b,z32\.h,#8'
1788 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunb z0\.b,z0\.h,#9'
1789 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunb z0\.b,z0\.h,#0'
1790 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrunb z0\.h,z0\.h,#8'
1791 [^ :]+:[0-9]+: Info:    did you mean this\?
1792 [^ :]+:[0-9]+: Info:            sqrshrunb z0\.b, z0\.h, #8
1793 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1794 [^ :]+:[0-9]+: Info:            sqrshrunb z0\.h, z0\.s, #8
1795 [^ :]+:[0-9]+: Info:            sqrshrunb z0\.s, z0\.d, #8
1796 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrunb z0\.h,z0\.s,#0'
1797 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrunb z0\.h,z0\.s,#17'
1798 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrunb z0\.s,z0\.d,#0'
1799 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrunb z0\.s,z0\.d,#33'
1800 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqrshrunt z0\.b,z0\.h,#1'
1801 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrunt z32\.b,z0\.h,#8'
1802 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrunt z0\.b,z32\.h,#8'
1803 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunt z0\.b,z0\.h,#9'
1804 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunt z0\.b,z0\.h,#0'
1805 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrunt z0\.h,z0\.h,#8'
1806 [^ :]+:[0-9]+: Info:    did you mean this\?
1807 [^ :]+:[0-9]+: Info:            sqrshrunt z0\.b, z0\.h, #8
1808 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1809 [^ :]+:[0-9]+: Info:            sqrshrunt z0\.h, z0\.s, #8
1810 [^ :]+:[0-9]+: Info:            sqrshrunt z0\.s, z0\.d, #8
1811 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrunt z0\.h,z0\.s,#0'
1812 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrunt z0\.h,z0\.s,#17'
1813 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrunt z0\.s,z0\.d,#0'
1814 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrunt z0\.s,z0\.d,#33'
1815 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshl z0\.h,p0/m,z0\.b,#0'
1816 [^ :]+:[0-9]+: Info:    did you mean this\?
1817 [^ :]+:[0-9]+: Info:            sqshl z0\.b, p0/m, z0\.b, #0
1818 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1819 [^ :]+:[0-9]+: Info:            sqshl z0\.h, p0/m, z0\.h, #0
1820 [^ :]+:[0-9]+: Info:            sqshl z0\.s, p0/m, z0\.s, #0
1821 [^ :]+:[0-9]+: Info:            sqshl z0\.d, p0/m, z0\.d, #0
1822 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqshl z32\.b,p0/m,z32\.b,#0'
1823 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshl z0\.b,p0/m,z1\.b,#0'
1824 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshl z0\.b,p8/m,z0\.b,#0'
1825 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 4 -- `sqshl z0\.b,p0/m,z0\.b,#8'
1826 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `sqshl z0\.h,p0/m,z0\.h,#16'
1827 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 4 -- `sqshl z0\.s,p0/m,z0\.s,#32'
1828 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 4 -- `sqshl z0\.d,p0/m,z0\.d,#64'
1829 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqshl z32\.b,p0/m,z0\.b,z0\.b'
1830 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqshl z0\.b,p0/m,z32\.b,z0\.b'
1831 [^ :]+:[0-9]+: Error: constant expression required at operand 4 -- `sqshl z0\.b,p0/m,z0\.b,z32\.b'
1832 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshl z0\.b,p0/m,z1\.b,z0\.b'
1833 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshl z0\.b,p8/m,z0\.b,z0\.b'
1834 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshl z0\.h,p0/m,z0\.b,z0\.b'
1835 [^ :]+:[0-9]+: Info:    did you mean this\?
1836 [^ :]+:[0-9]+: Info:            sqshl z0\.b, p0/m, z0\.b, z0\.b
1837 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1838 [^ :]+:[0-9]+: Info:            sqshl z0\.h, p0/m, z0\.h, z0\.h
1839 [^ :]+:[0-9]+: Info:            sqshl z0\.s, p0/m, z0\.s, z0\.s
1840 [^ :]+:[0-9]+: Info:            sqshl z0\.d, p0/m, z0\.d, z0\.d
1841 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshl z0\.b,p0/z,z0\.b,z0\.b'
1842 [^ :]+:[0-9]+: Info:    did you mean this\?
1843 [^ :]+:[0-9]+: Info:            sqshl z0\.b, p0/m, z0\.b, z0\.b
1844 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1845 [^ :]+:[0-9]+: Info:            sqshl z0\.h, p0/m, z0\.h, z0\.h
1846 [^ :]+:[0-9]+: Info:            sqshl z0\.s, p0/m, z0\.s, z0\.s
1847 [^ :]+:[0-9]+: Info:            sqshl z0\.d, p0/m, z0\.d, z0\.d
1848 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshlr z32\.b,p0/m,z0\.b,z0\.b'
1849 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqshlr z0\.b,p0/m,z32\.b,z0\.b'
1850 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqshlr z0\.b,p0/m,z0\.b,z32\.b'
1851 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshlr z0\.b,p0/m,z1\.b,z0\.b'
1852 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshlr z0\.b,p8/m,z0\.b,z0\.b'
1853 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshlr z0\.h,p0/m,z0\.b,z0\.b'
1854 [^ :]+:[0-9]+: Info:    did you mean this\?
1855 [^ :]+:[0-9]+: Info:            sqshlr z0\.b, p0/m, z0\.b, z0\.b
1856 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1857 [^ :]+:[0-9]+: Info:            sqshlr z0\.h, p0/m, z0\.h, z0\.h
1858 [^ :]+:[0-9]+: Info:            sqshlr z0\.s, p0/m, z0\.s, z0\.s
1859 [^ :]+:[0-9]+: Info:            sqshlr z0\.d, p0/m, z0\.d, z0\.d
1860 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshlr z0\.b,p0/z,z0\.b,z0\.b'
1861 [^ :]+:[0-9]+: Info:    did you mean this\?
1862 [^ :]+:[0-9]+: Info:            sqshlr z0\.b, p0/m, z0\.b, z0\.b
1863 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1864 [^ :]+:[0-9]+: Info:            sqshlr z0\.h, p0/m, z0\.h, z0\.h
1865 [^ :]+:[0-9]+: Info:            sqshlr z0\.s, p0/m, z0\.s, z0\.s
1866 [^ :]+:[0-9]+: Info:            sqshlr z0\.d, p0/m, z0\.d, z0\.d
1867 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshlu z0\.h,p0/m,z0\.b,#0'
1868 [^ :]+:[0-9]+: Info:    did you mean this\?
1869 [^ :]+:[0-9]+: Info:            sqshlu z0\.b, p0/m, z0\.b, #0
1870 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1871 [^ :]+:[0-9]+: Info:            sqshlu z0\.h, p0/m, z0\.h, #0
1872 [^ :]+:[0-9]+: Info:            sqshlu z0\.s, p0/m, z0\.s, #0
1873 [^ :]+:[0-9]+: Info:            sqshlu z0\.d, p0/m, z0\.d, #0
1874 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqshlu z32\.b,p0/m,z32\.b,#0'
1875 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshlu z0\.b,p0/m,z1\.b,#0'
1876 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshlu z0\.b,p8/m,z0\.b,#0'
1877 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 4 -- `sqshlu z0\.b,p0/m,z0\.b,#8'
1878 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `sqshlu z0\.h,p0/m,z0\.h,#16'
1879 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 4 -- `sqshlu z0\.s,p0/m,z0\.s,#32'
1880 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 4 -- `sqshlu z0\.d,p0/m,z0\.d,#64'
1881 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrnb z32\.b,z0\.h,#8'
1882 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrnb z0\.b,z32\.h,#8'
1883 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnb z0\.b,z0\.h,#9'
1884 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnb z0\.b,z0\.h,#0'
1885 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshrnb z0\.h,z0\.h,#8'
1886 [^ :]+:[0-9]+: Info:    did you mean this\?
1887 [^ :]+:[0-9]+: Info:            sqshrnb z0\.b, z0\.h, #8
1888 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1889 [^ :]+:[0-9]+: Info:            sqshrnb z0\.h, z0\.s, #8
1890 [^ :]+:[0-9]+: Info:            sqshrnb z0\.s, z0\.d, #8
1891 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrnb z0\.h,z0\.s,#0'
1892 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrnb z0\.h,z0\.s,#17'
1893 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnb z0\.s,z0\.d,#0'
1894 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnb z0\.s,z0\.d,#33'
1895 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqshrnt z0\.b,z0\.h,#1'
1896 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrnt z32\.b,z0\.h,#8'
1897 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrnt z0\.b,z32\.h,#8'
1898 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnt z0\.b,z0\.h,#9'
1899 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnt z0\.b,z0\.h,#0'
1900 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshrnt z0\.h,z0\.h,#8'
1901 [^ :]+:[0-9]+: Info:    did you mean this\?
1902 [^ :]+:[0-9]+: Info:            sqshrnt z0\.b, z0\.h, #8
1903 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1904 [^ :]+:[0-9]+: Info:            sqshrnt z0\.h, z0\.s, #8
1905 [^ :]+:[0-9]+: Info:            sqshrnt z0\.s, z0\.d, #8
1906 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrnt z0\.h,z0\.s,#0'
1907 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrnt z0\.h,z0\.s,#17'
1908 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnt z0\.s,z0\.d,#0'
1909 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnt z0\.s,z0\.d,#33'
1910 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrunb z32\.b,z0\.h,#8'
1911 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrunb z0\.b,z32\.h,#8'
1912 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunb z0\.b,z0\.h,#9'
1913 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunb z0\.b,z0\.h,#0'
1914 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshrunb z0\.h,z0\.h,#8'
1915 [^ :]+:[0-9]+: Info:    did you mean this\?
1916 [^ :]+:[0-9]+: Info:            sqshrunb z0\.b, z0\.h, #8
1917 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1918 [^ :]+:[0-9]+: Info:            sqshrunb z0\.h, z0\.s, #8
1919 [^ :]+:[0-9]+: Info:            sqshrunb z0\.s, z0\.d, #8
1920 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrunb z0\.h,z0\.s,#0'
1921 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrunb z0\.h,z0\.s,#17'
1922 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunb z0\.s,z0\.d,#0'
1923 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunb z0\.s,z0\.d,#33'
1924 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqshrunt z0\.b,z0\.h,#1'
1925 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrunt z32\.b,z0\.h,#8'
1926 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrunt z0\.b,z32\.h,#8'
1927 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunt z0\.b,z0\.h,#9'
1928 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunt z0\.b,z0\.h,#0'
1929 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshrunt z0\.h,z0\.h,#8'
1930 [^ :]+:[0-9]+: Info:    did you mean this\?
1931 [^ :]+:[0-9]+: Info:            sqshrunt z0\.b, z0\.h, #8
1932 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1933 [^ :]+:[0-9]+: Info:            sqshrunt z0\.h, z0\.s, #8
1934 [^ :]+:[0-9]+: Info:            sqshrunt z0\.s, z0\.d, #8
1935 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrunt z0\.h,z0\.s,#0'
1936 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrunt z0\.h,z0\.s,#17'
1937 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunt z0\.s,z0\.d,#0'
1938 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunt z0\.s,z0\.d,#33'
1939 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqsub z32\.b,p0/m,z0\.b,z0\.b'
1940 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqsub z0\.b,p0/m,z32\.b,z0\.b'
1941 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqsub z0\.b,p0/m,z0\.b,z32\.b'
1942 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqsub z0\.b,p0/m,z1\.b,z0\.b'
1943 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqsub z0\.b,p8/m,z0\.b,z0\.b'
1944 [^ :]+:[0-9]+: Error: operand mismatch -- `sqsub z0\.h,p0/m,z0\.b,z0\.b'
1945 [^ :]+:[0-9]+: Info:    did you mean this\?
1946 [^ :]+:[0-9]+: Info:            sqsub z0\.b, p0/m, z0\.b, z0\.b
1947 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1948 [^ :]+:[0-9]+: Info:            sqsub z0\.h, p0/m, z0\.h, z0\.h
1949 [^ :]+:[0-9]+: Info:            sqsub z0\.s, p0/m, z0\.s, z0\.s
1950 [^ :]+:[0-9]+: Info:            sqsub z0\.d, p0/m, z0\.d, z0\.d
1951 [^ :]+:[0-9]+: Error: operand mismatch -- `sqsub z0\.b,p0/z,z0\.b,z0\.b'
1952 [^ :]+:[0-9]+: Info:    did you mean this\?
1953 [^ :]+:[0-9]+: Info:            sqsub z0\.b, p0/m, z0\.b, z0\.b
1954 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1955 [^ :]+:[0-9]+: Info:            sqsub z0\.h, p0/m, z0\.h, z0\.h
1956 [^ :]+:[0-9]+: Info:            sqsub z0\.s, p0/m, z0\.s, z0\.s
1957 [^ :]+:[0-9]+: Info:            sqsub z0\.d, p0/m, z0\.d, z0\.d
1958 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqsubr z32\.b,p0/m,z0\.b,z0\.b'
1959 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqsubr z0\.b,p0/m,z32\.b,z0\.b'
1960 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqsubr z0\.b,p0/m,z0\.b,z32\.b'
1961 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqsubr z0\.b,p0/m,z1\.b,z0\.b'
1962 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqsubr z0\.b,p8/m,z0\.b,z0\.b'
1963 [^ :]+:[0-9]+: Error: operand mismatch -- `sqsubr z0\.h,p0/m,z0\.b,z0\.b'
1964 [^ :]+:[0-9]+: Info:    did you mean this\?
1965 [^ :]+:[0-9]+: Info:            sqsubr z0\.b, p0/m, z0\.b, z0\.b
1966 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1967 [^ :]+:[0-9]+: Info:            sqsubr z0\.h, p0/m, z0\.h, z0\.h
1968 [^ :]+:[0-9]+: Info:            sqsubr z0\.s, p0/m, z0\.s, z0\.s
1969 [^ :]+:[0-9]+: Info:            sqsubr z0\.d, p0/m, z0\.d, z0\.d
1970 [^ :]+:[0-9]+: Error: operand mismatch -- `sqsubr z0\.b,p0/z,z0\.b,z0\.b'
1971 [^ :]+:[0-9]+: Info:    did you mean this\?
1972 [^ :]+:[0-9]+: Info:            sqsubr z0\.b, p0/m, z0\.b, z0\.b
1973 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1974 [^ :]+:[0-9]+: Info:            sqsubr z0\.h, p0/m, z0\.h, z0\.h
1975 [^ :]+:[0-9]+: Info:            sqsubr z0\.s, p0/m, z0\.s, z0\.s
1976 [^ :]+:[0-9]+: Info:            sqsubr z0\.d, p0/m, z0\.d, z0\.d
1977 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtnb z32\.b,z0\.h'
1978 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtnb z0\.b,z32\.h'
1979 [^ :]+:[0-9]+: Error: operand mismatch -- `sqxtnb z0\.b,z0\.s'
1980 [^ :]+:[0-9]+: Info:    did you mean this\?
1981 [^ :]+:[0-9]+: Info:            sqxtnb z0\.b, z0\.h
1982 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1983 [^ :]+:[0-9]+: Info:            sqxtnb z0\.h, z0\.s
1984 [^ :]+:[0-9]+: Info:            sqxtnb z0\.s, z0\.d
1985 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtnt z32\.b,z0\.h'
1986 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtnt z0\.b,z32\.h'
1987 [^ :]+:[0-9]+: Error: operand mismatch -- `sqxtnt z0\.b,z0\.s'
1988 [^ :]+:[0-9]+: Info:    did you mean this\?
1989 [^ :]+:[0-9]+: Info:            sqxtnt z0\.b, z0\.h
1990 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1991 [^ :]+:[0-9]+: Info:            sqxtnt z0\.h, z0\.s
1992 [^ :]+:[0-9]+: Info:            sqxtnt z0\.s, z0\.d
1993 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtunb z32\.b,z0\.h'
1994 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtunb z0\.b,z32\.h'
1995 [^ :]+:[0-9]+: Error: operand mismatch -- `sqxtunb z0\.b,z0\.s'
1996 [^ :]+:[0-9]+: Info:    did you mean this\?
1997 [^ :]+:[0-9]+: Info:            sqxtunb z0\.b, z0\.h
1998 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
1999 [^ :]+:[0-9]+: Info:            sqxtunb z0\.h, z0\.s
2000 [^ :]+:[0-9]+: Info:            sqxtunb z0\.s, z0\.d
2001 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtunt z32\.b,z0\.h'
2002 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtunt z0\.b,z32\.h'
2003 [^ :]+:[0-9]+: Error: operand mismatch -- `sqxtunt z0\.b,z0\.s'
2004 [^ :]+:[0-9]+: Info:    did you mean this\?
2005 [^ :]+:[0-9]+: Info:            sqxtunt z0\.b, z0\.h
2006 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2007 [^ :]+:[0-9]+: Info:            sqxtunt z0\.h, z0\.s
2008 [^ :]+:[0-9]+: Info:            sqxtunt z0\.s, z0\.d
2009 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `srhadd z32\.b,p0/m,z0\.b,z0\.b'
2010 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `srhadd z0\.b,p0/m,z32\.b,z0\.b'
2011 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `srhadd z0\.b,p0/m,z0\.b,z32\.b'
2012 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srhadd z0\.b,p0/m,z1\.b,z0\.b'
2013 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srhadd z0\.b,p8/m,z0\.b,z0\.b'
2014 [^ :]+:[0-9]+: Error: operand mismatch -- `srhadd z0\.h,p0/m,z0\.b,z0\.b'
2015 [^ :]+:[0-9]+: Info:    did you mean this\?
2016 [^ :]+:[0-9]+: Info:            srhadd z0\.b, p0/m, z0\.b, z0\.b
2017 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2018 [^ :]+:[0-9]+: Info:            srhadd z0\.h, p0/m, z0\.h, z0\.h
2019 [^ :]+:[0-9]+: Info:            srhadd z0\.s, p0/m, z0\.s, z0\.s
2020 [^ :]+:[0-9]+: Info:            srhadd z0\.d, p0/m, z0\.d, z0\.d
2021 [^ :]+:[0-9]+: Error: operand mismatch -- `srhadd z0\.b,p0/z,z0\.b,z0\.b'
2022 [^ :]+:[0-9]+: Info:    did you mean this\?
2023 [^ :]+:[0-9]+: Info:            srhadd z0\.b, p0/m, z0\.b, z0\.b
2024 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2025 [^ :]+:[0-9]+: Info:            srhadd z0\.h, p0/m, z0\.h, z0\.h
2026 [^ :]+:[0-9]+: Info:            srhadd z0\.s, p0/m, z0\.s, z0\.s
2027 [^ :]+:[0-9]+: Info:            srhadd z0\.d, p0/m, z0\.d, z0\.d
2028 [^ :]+:[0-9]+: Error: operand mismatch -- `sri z0\.h,z0\.b,#1'
2029 [^ :]+:[0-9]+: Info:    did you mean this\?
2030 [^ :]+:[0-9]+: Info:            sri z0\.b, z0\.b, #1
2031 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2032 [^ :]+:[0-9]+: Info:            sri z0\.h, z0\.h, #1
2033 [^ :]+:[0-9]+: Info:            sri z0\.s, z0\.s, #1
2034 [^ :]+:[0-9]+: Info:            sri z0\.d, z0\.d, #1
2035 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sri z32\.b,z0\.b,#1'
2036 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sri z0\.b,z32\.b,#1'
2037 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sri z0\.b,z0\.b,#0'
2038 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sri z0\.b,z0\.b,#9'
2039 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sri z0\.h,z0\.h,#0'
2040 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sri z0\.h,z0\.h,#17'
2041 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sri z0\.s,z0\.s,#0'
2042 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sri z0\.s,z0\.s,#33'
2043 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `sri z0\.d,z0\.d,#0'
2044 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `srshl z32\.b,p0/m,z0\.b,z0\.b'
2045 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `srshl z0\.b,p0/m,z32\.b,z0\.b'
2046 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `srshl z0\.b,p0/m,z0\.b,z32\.b'
2047 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srshl z0\.b,p0/m,z1\.b,z0\.b'
2048 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srshl z0\.b,p8/m,z0\.b,z0\.b'
2049 [^ :]+:[0-9]+: Error: operand mismatch -- `srshl z0\.h,p0/m,z0\.b,z0\.b'
2050 [^ :]+:[0-9]+: Info:    did you mean this\?
2051 [^ :]+:[0-9]+: Info:            srshl z0\.b, p0/m, z0\.b, z0\.b
2052 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2053 [^ :]+:[0-9]+: Info:            srshl z0\.h, p0/m, z0\.h, z0\.h
2054 [^ :]+:[0-9]+: Info:            srshl z0\.s, p0/m, z0\.s, z0\.s
2055 [^ :]+:[0-9]+: Info:            srshl z0\.d, p0/m, z0\.d, z0\.d
2056 [^ :]+:[0-9]+: Error: operand mismatch -- `srshl z0\.b,p0/z,z0\.b,z0\.b'
2057 [^ :]+:[0-9]+: Info:    did you mean this\?
2058 [^ :]+:[0-9]+: Info:            srshl z0\.b, p0/m, z0\.b, z0\.b
2059 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2060 [^ :]+:[0-9]+: Info:            srshl z0\.h, p0/m, z0\.h, z0\.h
2061 [^ :]+:[0-9]+: Info:            srshl z0\.s, p0/m, z0\.s, z0\.s
2062 [^ :]+:[0-9]+: Info:            srshl z0\.d, p0/m, z0\.d, z0\.d
2063 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `srshlr z32\.b,p0/m,z0\.b,z0\.b'
2064 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `srshlr z0\.b,p0/m,z32\.b,z0\.b'
2065 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `srshlr z0\.b,p0/m,z0\.b,z32\.b'
2066 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srshlr z0\.b,p0/m,z1\.b,z0\.b'
2067 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srshlr z0\.b,p8/m,z0\.b,z0\.b'
2068 [^ :]+:[0-9]+: Error: operand mismatch -- `srshlr z0\.h,p0/m,z0\.b,z0\.b'
2069 [^ :]+:[0-9]+: Info:    did you mean this\?
2070 [^ :]+:[0-9]+: Info:            srshlr z0\.b, p0/m, z0\.b, z0\.b
2071 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2072 [^ :]+:[0-9]+: Info:            srshlr z0\.h, p0/m, z0\.h, z0\.h
2073 [^ :]+:[0-9]+: Info:            srshlr z0\.s, p0/m, z0\.s, z0\.s
2074 [^ :]+:[0-9]+: Info:            srshlr z0\.d, p0/m, z0\.d, z0\.d
2075 [^ :]+:[0-9]+: Error: operand mismatch -- `srshlr z0\.b,p0/z,z0\.b,z0\.b'
2076 [^ :]+:[0-9]+: Info:    did you mean this\?
2077 [^ :]+:[0-9]+: Info:            srshlr z0\.b, p0/m, z0\.b, z0\.b
2078 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2079 [^ :]+:[0-9]+: Info:            srshlr z0\.h, p0/m, z0\.h, z0\.h
2080 [^ :]+:[0-9]+: Info:            srshlr z0\.s, p0/m, z0\.s, z0\.s
2081 [^ :]+:[0-9]+: Info:            srshlr z0\.d, p0/m, z0\.d, z0\.d
2082 [^ :]+:[0-9]+: Error: operand mismatch -- `srshr z0\.h,p0/m,z0\.b,#1'
2083 [^ :]+:[0-9]+: Info:    did you mean this\?
2084 [^ :]+:[0-9]+: Info:            srshr z0\.b, p0/m, z0\.b, #1
2085 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2086 [^ :]+:[0-9]+: Info:            srshr z0\.h, p0/m, z0\.h, #1
2087 [^ :]+:[0-9]+: Info:            srshr z0\.s, p0/m, z0\.s, #1
2088 [^ :]+:[0-9]+: Info:            srshr z0\.d, p0/m, z0\.d, #1
2089 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `srshr z32\.b,p0/m,z32\.b,#1'
2090 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srshr z0\.b,p0/m,z1\.b,#1'
2091 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srshr z0\.b,p8/m,z0\.b,#1'
2092 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `srshr z0\.b,p0/m,z0\.b,#0'
2093 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `srshr z0\.b,p0/m,z0\.b,#9'
2094 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 4 -- `srshr z0\.h,p0/m,z0\.h,#0'
2095 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 4 -- `srshr z0\.h,p0/m,z0\.h,#17'
2096 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `srshr z0\.s,p0/m,z0\.s,#0'
2097 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `srshr z0\.s,p0/m,z0\.s,#33'
2098 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `srshr z0\.d,p0/m,z0\.d,#0'
2099 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `srshr z0\.d,p0/m,z0\.d,#65'
2100 [^ :]+:[0-9]+: Error: operand mismatch -- `srsra z0\.h,z0\.b,#1'
2101 [^ :]+:[0-9]+: Info:    did you mean this\?
2102 [^ :]+:[0-9]+: Info:            srsra z0\.b, z0\.b, #1
2103 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2104 [^ :]+:[0-9]+: Info:            srsra z0\.h, z0\.h, #1
2105 [^ :]+:[0-9]+: Info:            srsra z0\.s, z0\.s, #1
2106 [^ :]+:[0-9]+: Info:            srsra z0\.d, z0\.d, #1
2107 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `srsra z32\.b,z0\.b,#1'
2108 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `srsra z0\.b,z32\.b,#1'
2109 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `srsra z0\.b,z0\.b,#0'
2110 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `srsra z0\.b,z0\.b,#9'
2111 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `srsra z0\.h,z0\.h,#0'
2112 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `srsra z0\.h,z0\.h,#17'
2113 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `srsra z0\.s,z0\.s,#0'
2114 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `srsra z0\.s,z0\.s,#33'
2115 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `srsra z0\.d,z0\.d,#0'
2116 [^ :]+:[0-9]+: Error: operand mismatch -- `sshllb z0\.b,z0\.b,#0'
2117 [^ :]+:[0-9]+: Info:    did you mean this\?
2118 [^ :]+:[0-9]+: Info:            sshllb z0\.h, z0\.b, #0
2119 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2120 [^ :]+:[0-9]+: Info:            sshllb z0\.s, z0\.h, #0
2121 [^ :]+:[0-9]+: Info:            sshllb z0\.d, z0\.s, #0
2122 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sshllb z32\.h,z0\.b,#0'
2123 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sshllb z0\.h,z32\.b,#0'
2124 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `sshllb z0\.h,z0\.b,#8'
2125 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `sshllb z0\.s,z0\.h,#16'
2126 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `sshllb z0\.d,z0\.s,#32'
2127 [^ :]+:[0-9]+: Error: operand mismatch -- `sshllt z0\.b,z0\.b,#0'
2128 [^ :]+:[0-9]+: Info:    did you mean this\?
2129 [^ :]+:[0-9]+: Info:            sshllt z0\.h, z0\.b, #0
2130 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2131 [^ :]+:[0-9]+: Info:            sshllt z0\.s, z0\.h, #0
2132 [^ :]+:[0-9]+: Info:            sshllt z0\.d, z0\.s, #0
2133 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sshllt z32\.h,z0\.b,#0'
2134 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sshllt z0\.h,z32\.b,#0'
2135 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `sshllt z0\.h,z0\.b,#8'
2136 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `sshllt z0\.s,z0\.h,#16'
2137 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `sshllt z0\.d,z0\.s,#32'
2138 [^ :]+:[0-9]+: Error: operand mismatch -- `ssra z0\.h,z0\.b,#1'
2139 [^ :]+:[0-9]+: Info:    did you mean this\?
2140 [^ :]+:[0-9]+: Info:            ssra z0\.b, z0\.b, #1
2141 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2142 [^ :]+:[0-9]+: Info:            ssra z0\.h, z0\.h, #1
2143 [^ :]+:[0-9]+: Info:            ssra z0\.s, z0\.s, #1
2144 [^ :]+:[0-9]+: Info:            ssra z0\.d, z0\.d, #1
2145 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `ssra z32\.b,z0\.b,#1'
2146 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssra z0\.b,z32\.b,#1'
2147 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ssra z0\.b,z0\.b,#0'
2148 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ssra z0\.b,z0\.b,#9'
2149 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `ssra z0\.h,z0\.h,#0'
2150 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `ssra z0\.h,z0\.h,#17'
2151 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `ssra z0\.s,z0\.s,#0'
2152 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `ssra z0\.s,z0\.s,#33'
2153 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `ssra z0\.d,z0\.d,#0'
2154 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssublb z32\.h,z0\.b,z0\.b'
2155 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssublb z0\.h,z32\.b,z0\.b'
2156 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssublb z0\.h,z0\.b,z32\.b'
2157 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssublb z0\.s,z0\.h,z0\.x'
2158 [^ :]+:[0-9]+: Error: operand mismatch -- `ssublb z0\.h,z0\.b,z0\.h'
2159 [^ :]+:[0-9]+: Info:    did you mean this\?
2160 [^ :]+:[0-9]+: Info:            ssublb z0\.h, z0\.b, z0\.b
2161 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2162 [^ :]+:[0-9]+: Info:            ssublb z0\.s, z0\.h, z0\.h
2163 [^ :]+:[0-9]+: Info:            ssublb z0\.d, z0\.s, z0\.s
2164 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssublbt z32\.h,z0\.b,z0\.b'
2165 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssublbt z0\.h,z32\.b,z0\.b'
2166 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssublbt z0\.h,z0\.b,z32\.b'
2167 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssublbt z0\.s,z0\.h,z0\.x'
2168 [^ :]+:[0-9]+: Error: operand mismatch -- `ssublbt z0\.h,z0\.b,z0\.h'
2169 [^ :]+:[0-9]+: Info:    did you mean this\?
2170 [^ :]+:[0-9]+: Info:            ssublbt z0\.h, z0\.b, z0\.b
2171 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2172 [^ :]+:[0-9]+: Info:            ssublbt z0\.s, z0\.h, z0\.h
2173 [^ :]+:[0-9]+: Info:            ssublbt z0\.d, z0\.s, z0\.s
2174 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssublt z32\.h,z0\.b,z0\.b'
2175 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssublt z0\.h,z32\.b,z0\.b'
2176 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssublt z0\.h,z0\.b,z32\.b'
2177 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssublt z0\.s,z0\.h,z0\.x'
2178 [^ :]+:[0-9]+: Error: operand mismatch -- `ssublt z0\.h,z0\.b,z0\.h'
2179 [^ :]+:[0-9]+: Info:    did you mean this\?
2180 [^ :]+:[0-9]+: Info:            ssublt z0\.h, z0\.b, z0\.b
2181 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2182 [^ :]+:[0-9]+: Info:            ssublt z0\.s, z0\.h, z0\.h
2183 [^ :]+:[0-9]+: Info:            ssublt z0\.d, z0\.s, z0\.s
2184 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssubltb z32\.h,z0\.b,z0\.b'
2185 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssubltb z0\.h,z32\.b,z0\.b'
2186 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssubltb z0\.h,z0\.b,z32\.b'
2187 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssubltb z0\.s,z0\.h,z0\.x'
2188 [^ :]+:[0-9]+: Error: operand mismatch -- `ssubltb z0\.h,z0\.b,z0\.h'
2189 [^ :]+:[0-9]+: Info:    did you mean this\?
2190 [^ :]+:[0-9]+: Info:            ssubltb z0\.h, z0\.b, z0\.b
2191 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2192 [^ :]+:[0-9]+: Info:            ssubltb z0\.s, z0\.h, z0\.h
2193 [^ :]+:[0-9]+: Info:            ssubltb z0\.d, z0\.s, z0\.s
2194 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssubwb z32\.h,z0\.h,z0\.b'
2195 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssubwb z0\.h,z32\.h,z0\.b'
2196 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssubwb z0\.h,z0\.h,z32\.b'
2197 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssubwb z0\.s,z0\.s,z0\.x'
2198 [^ :]+:[0-9]+: Error: operand mismatch -- `ssubwb z0\.h,z0\.h,z0\.h'
2199 [^ :]+:[0-9]+: Info:    did you mean this\?
2200 [^ :]+:[0-9]+: Info:            ssubwb z0\.h, z0\.h, z0\.b
2201 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2202 [^ :]+:[0-9]+: Info:            ssubwb z0\.s, z0\.s, z0\.h
2203 [^ :]+:[0-9]+: Info:            ssubwb z0\.d, z0\.d, z0\.s
2204 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssubwt z32\.h,z0\.h,z0\.b'
2205 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssubwt z0\.h,z32\.h,z0\.b'
2206 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssubwt z0\.h,z0\.h,z32\.b'
2207 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssubwt z0\.s,z0\.s,z0\.x'
2208 [^ :]+:[0-9]+: Error: operand mismatch -- `ssubwt z0\.h,z0\.h,z0\.h'
2209 [^ :]+:[0-9]+: Info:    did you mean this\?
2210 [^ :]+:[0-9]+: Info:            ssubwt z0\.h, z0\.h, z0\.b
2211 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2212 [^ :]+:[0-9]+: Info:            ssubwt z0\.s, z0\.s, z0\.h
2213 [^ :]+:[0-9]+: Info:            ssubwt z0\.d, z0\.d, z0\.s
2214 [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1b {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
2215 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1b {z0\.d},p0/m,\[z0\.d\]'
2216 [^ :]+:[0-9]+: Info:    did you mean this\?
2217 [^ :]+:[0-9]+: Info:            stnt1b {z0\.s}, p0, \[z0\.s, xzr\]
2218 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1b {z32\.d},p0,\[z0\.d\]'
2219 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.d},p8,\[z0\.d\]'
2220 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1b {z0\.d},p0,\[z32\.d\]'
2221 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,sp\]'
2222 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,x32\]'
2223 [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,w16\]'
2224 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,z0\.d\]'
2225 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1b {z0\.s},p0,\[z0\.d\]'
2226 [^ :]+:[0-9]+: Info:    did you mean this\?
2227 [^ :]+:[0-9]+: Info:            stnt1b {z0\.s}, p0, \[z0\.s, xzr\]
2228 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1b {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
2229 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1b {z32\.s},p0,\[z0\.s\]'
2230 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.s},p8,\[z0\.s\]'
2231 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1b {z0\.s},p0,\[z32\.s\]'
2232 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,sp\]'
2233 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,x32\]'
2234 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,z0\.s\]'
2235 [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1d {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
2236 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.d},p0/m,\[z0\.d\]'
2237 [^ :]+:[0-9]+: Info:    did you mean this\?
2238 [^ :]+:[0-9]+: Info:            stnt1d {z0\.d}, p0, \[z0\.d, xzr\]
2239 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1d {z32\.d},p0,\[z0\.d\]'
2240 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1d {z0\.d},p8,\[z0\.d\]'
2241 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1d {z0\.d},p0,\[z32\.d\]'
2242 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,sp\]'
2243 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,x32\]'
2244 [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,w16\]'
2245 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,z0\.d\]'
2246 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.s},p0,\[z0\.d\]'
2247 [^ :]+:[0-9]+: Info:    did you mean this\?
2248 [^ :]+:[0-9]+: Info:            stnt1d {z0\.d}, p0, \[z0\.d, xzr\]
2249 [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1h {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
2250 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.d},p0/m,\[z0\.d\]'
2251 [^ :]+:[0-9]+: Info:    did you mean this\?
2252 [^ :]+:[0-9]+: Info:            stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
2253 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.d},p0,\[z0\.d\]'
2254 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.d},p8,\[z0\.d\]'
2255 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1h {z0\.d},p0,\[z32\.d\]'
2256 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,sp\]'
2257 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,x32\]'
2258 [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,w16\]'
2259 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,z0\.d\]'
2260 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.s},p0,\[z0\.d\]'
2261 [^ :]+:[0-9]+: Info:    did you mean this\?
2262 [^ :]+:[0-9]+: Info:            stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
2263 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1h {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
2264 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.s},p0,\[z0\.s\]'
2265 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.s},p8,\[z0\.s\]'
2266 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1h {z0\.s},p0,\[z32\.s\]'
2267 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,sp\]'
2268 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,x32\]'
2269 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,z0\.s\]'
2270 [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1w {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
2271 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1w {z0\.d},p0/m,\[z0\.d\]'
2272 [^ :]+:[0-9]+: Info:    did you mean this\?
2273 [^ :]+:[0-9]+: Info:            stnt1w {z0\.s}, p0, \[z0\.s, xzr\]
2274 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1w {z32\.d},p0,\[z0\.d\]'
2275 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.d},p8,\[z0\.d\]'
2276 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1w {z0\.d},p0,\[z32\.d\]'
2277 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,sp\]'
2278 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,x32\]'
2279 [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,w16\]'
2280 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,z0\.d\]'
2281 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1w {z0\.s},p0,\[z0\.d\]'
2282 [^ :]+:[0-9]+: Info:    did you mean this\?
2283 [^ :]+:[0-9]+: Info:            stnt1w {z0\.s}, p0, \[z0\.s, xzr\]
2284 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1w {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
2285 [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1w {z32\.s},p0,\[z0\.s\]'
2286 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.s},p8,\[z0\.s\]'
2287 [^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1w {z0\.s},p0,\[z32\.s\]'
2288 [^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,sp\]'
2289 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,x32\]'
2290 [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,z0\.s\]'
2291 [^ :]+:[0-9]+: Error: operand mismatch -- `subhnb z0\.h,z0\.h,z0\.h'
2292 [^ :]+:[0-9]+: Info:    did you mean this\?
2293 [^ :]+:[0-9]+: Info:            subhnb z0\.b, z0\.h, z0\.h
2294 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2295 [^ :]+:[0-9]+: Info:            subhnb z0\.h, z0\.s, z0\.s
2296 [^ :]+:[0-9]+: Info:            subhnb z0\.s, z0\.d, z0\.d
2297 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `subhnb z32\.b,z0\.h,z0\.h'
2298 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `subhnb z0\.b,z32\.h,z0\.h'
2299 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `subhnb z0\.b,z0\.h,z32\.h'
2300 [^ :]+:[0-9]+: Error: operand mismatch -- `subhnt z0\.h,z0\.h,z0\.h'
2301 [^ :]+:[0-9]+: Info:    did you mean this\?
2302 [^ :]+:[0-9]+: Info:            subhnt z0\.b, z0\.h, z0\.h
2303 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2304 [^ :]+:[0-9]+: Info:            subhnt z0\.h, z0\.s, z0\.s
2305 [^ :]+:[0-9]+: Info:            subhnt z0\.s, z0\.d, z0\.d
2306 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `subhnt z32\.b,z0\.h,z0\.h'
2307 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `subhnt z0\.b,z32\.h,z0\.h'
2308 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `subhnt z0\.b,z0\.h,z32\.h'
2309 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `suqadd z32\.b,p0/m,z0\.b,z0\.b'
2310 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `suqadd z0\.b,p0/m,z32\.b,z0\.b'
2311 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `suqadd z0\.b,p0/m,z0\.b,z32\.b'
2312 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `suqadd z0\.b,p0/m,z1\.b,z0\.b'
2313 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `suqadd z0\.b,p8/m,z0\.b,z0\.b'
2314 [^ :]+:[0-9]+: Error: operand mismatch -- `suqadd z0\.h,p0/m,z0\.b,z0\.b'
2315 [^ :]+:[0-9]+: Info:    did you mean this\?
2316 [^ :]+:[0-9]+: Info:            suqadd z0\.b, p0/m, z0\.b, z0\.b
2317 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2318 [^ :]+:[0-9]+: Info:            suqadd z0\.h, p0/m, z0\.h, z0\.h
2319 [^ :]+:[0-9]+: Info:            suqadd z0\.s, p0/m, z0\.s, z0\.s
2320 [^ :]+:[0-9]+: Info:            suqadd z0\.d, p0/m, z0\.d, z0\.d
2321 [^ :]+:[0-9]+: Error: operand mismatch -- `suqadd z0\.b,p0/z,z0\.b,z0\.b'
2322 [^ :]+:[0-9]+: Info:    did you mean this\?
2323 [^ :]+:[0-9]+: Info:            suqadd z0\.b, p0/m, z0\.b, z0\.b
2324 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2325 [^ :]+:[0-9]+: Info:            suqadd z0\.h, p0/m, z0\.h, z0\.h
2326 [^ :]+:[0-9]+: Info:            suqadd z0\.s, p0/m, z0\.s, z0\.s
2327 [^ :]+:[0-9]+: Info:            suqadd z0\.d, p0/m, z0\.d, z0\.d
2328 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `tbl z32\.b,{z0\.b,z1\.b},z0\.b'
2329 [^ :]+:[0-9]+: Error: operand 2 must be a list of SVE vector registers -- `tbl z0\.b,{z31\.b,z32\.b},z0\.b'
2330 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `tbl z0\.b,{z31\.b,z1\.b},z0\.b'
2331 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `tbl z0\.b,{z0\.b,z1\.b},z32\.b'
2332 [^ :]+:[0-9]+: Error: operand mismatch -- `tbl z0\.b,{z0\.b,z1\.b},z0\.h'
2333 [^ :]+:[0-9]+: Info:    did you mean this\?
2334 [^ :]+:[0-9]+: Info:            tbl z0\.b, {z0\.b, z1\.b}, z0\.b
2335 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2336 [^ :]+:[0-9]+: Info:            tbl z0\.h, {z0\.h, z1\.h}, z0\.h
2337 [^ :]+:[0-9]+: Info:            tbl z0\.s, {z0\.s, z1\.s}, z0\.s
2338 [^ :]+:[0-9]+: Info:            tbl z0\.d, {z0\.d, z1\.d}, z0\.d
2339 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.b,z1\.h},z0\.b'
2340 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.h,z0\.b},z0\.b'
2341 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `tbl z0\.h,{z0\.b,z0\.b},z0\.b'
2342 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `tbx z32\.h,z0\.b,z0\.b'
2343 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `tbx z0\.h,z32\.b,z0\.b'
2344 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `tbx z0\.h,z0\.b,z32\.b'
2345 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `tbx z0\.s,z0\.h,z0\.x'
2346 [^ :]+:[0-9]+: Error: operand mismatch -- `tbx z0\.h,z0\.b,z0\.h'
2347 [^ :]+:[0-9]+: Info:    did you mean this\?
2348 [^ :]+:[0-9]+: Info:            tbx z0\.h, z0\.h, z0\.h
2349 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2350 [^ :]+:[0-9]+: Info:            tbx z0\.b, z0\.b, z0\.b
2351 [^ :]+:[0-9]+: Info:            tbx z0\.s, z0\.s, z0\.s
2352 [^ :]+:[0-9]+: Info:            tbx z0\.d, z0\.d, z0\.d
2353 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaba z32\.h,z0\.b,z0\.b'
2354 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaba z0\.h,z32\.b,z0\.b'
2355 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaba z0\.h,z0\.b,z32\.b'
2356 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaba z0\.s,z0\.h,z0\.x'
2357 [^ :]+:[0-9]+: Error: operand mismatch -- `uaba z0\.h,z0\.b,z0\.h'
2358 [^ :]+:[0-9]+: Info:    did you mean this\?
2359 [^ :]+:[0-9]+: Info:            uaba z0\.h, z0\.h, z0\.h
2360 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2361 [^ :]+:[0-9]+: Info:            uaba z0\.b, z0\.b, z0\.b
2362 [^ :]+:[0-9]+: Info:            uaba z0\.s, z0\.s, z0\.s
2363 [^ :]+:[0-9]+: Info:            uaba z0\.d, z0\.d, z0\.d
2364 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabalb z32\.h,z0\.b,z0\.b'
2365 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabalb z0\.h,z32\.b,z0\.b'
2366 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabalb z0\.h,z0\.b,z32\.b'
2367 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabalb z0\.s,z0\.h,z0\.x'
2368 [^ :]+:[0-9]+: Error: operand mismatch -- `uabalb z0\.h,z0\.b,z0\.h'
2369 [^ :]+:[0-9]+: Info:    did you mean this\?
2370 [^ :]+:[0-9]+: Info:            uabalb z0\.h, z0\.b, z0\.b
2371 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2372 [^ :]+:[0-9]+: Info:            uabalb z0\.s, z0\.h, z0\.h
2373 [^ :]+:[0-9]+: Info:            uabalb z0\.d, z0\.s, z0\.s
2374 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabalt z32\.h,z0\.b,z0\.b'
2375 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabalt z0\.h,z32\.b,z0\.b'
2376 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabalt z0\.h,z0\.b,z32\.b'
2377 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabalt z0\.s,z0\.h,z0\.x'
2378 [^ :]+:[0-9]+: Error: operand mismatch -- `uabalt z0\.h,z0\.b,z0\.h'
2379 [^ :]+:[0-9]+: Info:    did you mean this\?
2380 [^ :]+:[0-9]+: Info:            uabalt z0\.h, z0\.b, z0\.b
2381 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2382 [^ :]+:[0-9]+: Info:            uabalt z0\.s, z0\.h, z0\.h
2383 [^ :]+:[0-9]+: Info:            uabalt z0\.d, z0\.s, z0\.s
2384 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabdlb z32\.h,z0\.b,z0\.b'
2385 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabdlb z0\.h,z32\.b,z0\.b'
2386 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabdlb z0\.h,z0\.b,z32\.b'
2387 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabdlb z0\.s,z0\.h,z0\.x'
2388 [^ :]+:[0-9]+: Error: operand mismatch -- `uabdlb z0\.h,z0\.b,z0\.h'
2389 [^ :]+:[0-9]+: Info:    did you mean this\?
2390 [^ :]+:[0-9]+: Info:            uabdlb z0\.h, z0\.b, z0\.b
2391 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2392 [^ :]+:[0-9]+: Info:            uabdlb z0\.s, z0\.h, z0\.h
2393 [^ :]+:[0-9]+: Info:            uabdlb z0\.d, z0\.s, z0\.s
2394 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabdlt z32\.h,z0\.b,z0\.b'
2395 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabdlt z0\.h,z32\.b,z0\.b'
2396 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabdlt z0\.h,z0\.b,z32\.b'
2397 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabdlt z0\.s,z0\.h,z0\.x'
2398 [^ :]+:[0-9]+: Error: operand mismatch -- `uabdlt z0\.h,z0\.b,z0\.h'
2399 [^ :]+:[0-9]+: Info:    did you mean this\?
2400 [^ :]+:[0-9]+: Info:            uabdlt z0\.h, z0\.b, z0\.b
2401 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2402 [^ :]+:[0-9]+: Info:            uabdlt z0\.s, z0\.h, z0\.h
2403 [^ :]+:[0-9]+: Info:            uabdlt z0\.d, z0\.s, z0\.s
2404 [^ :]+:[0-9]+: Error: operand mismatch -- `uadalp z0\.b,p0/m,z0\.b'
2405 [^ :]+:[0-9]+: Info:    did you mean this\?
2406 [^ :]+:[0-9]+: Info:            uadalp z0\.h, p0/m, z0\.b
2407 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2408 [^ :]+:[0-9]+: Info:            uadalp z0\.s, p0/m, z0\.h
2409 [^ :]+:[0-9]+: Info:            uadalp z0\.d, p0/m, z0\.s
2410 [^ :]+:[0-9]+: Error: operand mismatch -- `uadalp z0\.h,p0/z,z0\.b'
2411 [^ :]+:[0-9]+: Info:    did you mean this\?
2412 [^ :]+:[0-9]+: Info:            uadalp z0\.h, p0/m, z0\.b
2413 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2414 [^ :]+:[0-9]+: Info:            uadalp z0\.s, p0/m, z0\.h
2415 [^ :]+:[0-9]+: Info:            uadalp z0\.d, p0/m, z0\.s
2416 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uadalp z0\.h,p8/m,z0\.b'
2417 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uadalp z32\.h,p0/m,z0\.b'
2418 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uadalp z0\.h,p0/m,z32\.b'
2419 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddlb z32\.h,z0\.b,z0\.b'
2420 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddlb z0\.h,z32\.b,z0\.b'
2421 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddlb z0\.h,z0\.b,z32\.b'
2422 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddlb z0\.s,z0\.h,z0\.x'
2423 [^ :]+:[0-9]+: Error: operand mismatch -- `uaddlb z0\.h,z0\.b,z0\.h'
2424 [^ :]+:[0-9]+: Info:    did you mean this\?
2425 [^ :]+:[0-9]+: Info:            uaddlb z0\.h, z0\.b, z0\.b
2426 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2427 [^ :]+:[0-9]+: Info:            uaddlb z0\.s, z0\.h, z0\.h
2428 [^ :]+:[0-9]+: Info:            uaddlb z0\.d, z0\.s, z0\.s
2429 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddlt z32\.h,z0\.b,z0\.b'
2430 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddlt z0\.h,z32\.b,z0\.b'
2431 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddlt z0\.h,z0\.b,z32\.b'
2432 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddlt z0\.s,z0\.h,z0\.x'
2433 [^ :]+:[0-9]+: Error: operand mismatch -- `uaddlt z0\.h,z0\.b,z0\.h'
2434 [^ :]+:[0-9]+: Info:    did you mean this\?
2435 [^ :]+:[0-9]+: Info:            uaddlt z0\.h, z0\.b, z0\.b
2436 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2437 [^ :]+:[0-9]+: Info:            uaddlt z0\.s, z0\.h, z0\.h
2438 [^ :]+:[0-9]+: Info:            uaddlt z0\.d, z0\.s, z0\.s
2439 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddwb z32\.h,z0\.h,z0\.b'
2440 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddwb z0\.h,z32\.h,z0\.b'
2441 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddwb z0\.h,z0\.h,z32\.b'
2442 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddwb z0\.s,z0\.s,z0\.x'
2443 [^ :]+:[0-9]+: Error: operand mismatch -- `uaddwb z0\.h,z0\.h,z0\.h'
2444 [^ :]+:[0-9]+: Info:    did you mean this\?
2445 [^ :]+:[0-9]+: Info:            uaddwb z0\.h, z0\.h, z0\.b
2446 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2447 [^ :]+:[0-9]+: Info:            uaddwb z0\.s, z0\.s, z0\.h
2448 [^ :]+:[0-9]+: Info:            uaddwb z0\.d, z0\.d, z0\.s
2449 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddwt z32\.h,z0\.h,z0\.b'
2450 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddwt z0\.h,z32\.h,z0\.b'
2451 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddwt z0\.h,z0\.h,z32\.b'
2452 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddwt z0\.s,z0\.s,z0\.x'
2453 [^ :]+:[0-9]+: Error: operand mismatch -- `uaddwt z0\.h,z0\.h,z0\.h'
2454 [^ :]+:[0-9]+: Info:    did you mean this\?
2455 [^ :]+:[0-9]+: Info:            uaddwt z0\.h, z0\.h, z0\.b
2456 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2457 [^ :]+:[0-9]+: Info:            uaddwt z0\.s, z0\.s, z0\.h
2458 [^ :]+:[0-9]+: Info:            uaddwt z0\.d, z0\.d, z0\.s
2459 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uhadd z32\.b,p0/m,z0\.b,z0\.b'
2460 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uhadd z0\.b,p0/m,z32\.b,z0\.b'
2461 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uhadd z0\.b,p0/m,z0\.b,z32\.b'
2462 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uhadd z0\.b,p0/m,z1\.b,z0\.b'
2463 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uhadd z0\.b,p8/m,z0\.b,z0\.b'
2464 [^ :]+:[0-9]+: Error: operand mismatch -- `uhadd z0\.h,p0/m,z0\.b,z0\.b'
2465 [^ :]+:[0-9]+: Info:    did you mean this\?
2466 [^ :]+:[0-9]+: Info:            uhadd z0\.b, p0/m, z0\.b, z0\.b
2467 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2468 [^ :]+:[0-9]+: Info:            uhadd z0\.h, p0/m, z0\.h, z0\.h
2469 [^ :]+:[0-9]+: Info:            uhadd z0\.s, p0/m, z0\.s, z0\.s
2470 [^ :]+:[0-9]+: Info:            uhadd z0\.d, p0/m, z0\.d, z0\.d
2471 [^ :]+:[0-9]+: Error: operand mismatch -- `uhadd z0\.b,p0/z,z0\.b,z0\.b'
2472 [^ :]+:[0-9]+: Info:    did you mean this\?
2473 [^ :]+:[0-9]+: Info:            uhadd z0\.b, p0/m, z0\.b, z0\.b
2474 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2475 [^ :]+:[0-9]+: Info:            uhadd z0\.h, p0/m, z0\.h, z0\.h
2476 [^ :]+:[0-9]+: Info:            uhadd z0\.s, p0/m, z0\.s, z0\.s
2477 [^ :]+:[0-9]+: Info:            uhadd z0\.d, p0/m, z0\.d, z0\.d
2478 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uhsub z32\.b,p0/m,z0\.b,z0\.b'
2479 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uhsub z0\.b,p0/m,z32\.b,z0\.b'
2480 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uhsub z0\.b,p0/m,z0\.b,z32\.b'
2481 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uhsub z0\.b,p0/m,z1\.b,z0\.b'
2482 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uhsub z0\.b,p8/m,z0\.b,z0\.b'
2483 [^ :]+:[0-9]+: Error: operand mismatch -- `uhsub z0\.h,p0/m,z0\.b,z0\.b'
2484 [^ :]+:[0-9]+: Info:    did you mean this\?
2485 [^ :]+:[0-9]+: Info:            uhsub z0\.b, p0/m, z0\.b, z0\.b
2486 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2487 [^ :]+:[0-9]+: Info:            uhsub z0\.h, p0/m, z0\.h, z0\.h
2488 [^ :]+:[0-9]+: Info:            uhsub z0\.s, p0/m, z0\.s, z0\.s
2489 [^ :]+:[0-9]+: Info:            uhsub z0\.d, p0/m, z0\.d, z0\.d
2490 [^ :]+:[0-9]+: Error: operand mismatch -- `uhsub z0\.b,p0/z,z0\.b,z0\.b'
2491 [^ :]+:[0-9]+: Info:    did you mean this\?
2492 [^ :]+:[0-9]+: Info:            uhsub z0\.b, p0/m, z0\.b, z0\.b
2493 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2494 [^ :]+:[0-9]+: Info:            uhsub z0\.h, p0/m, z0\.h, z0\.h
2495 [^ :]+:[0-9]+: Info:            uhsub z0\.s, p0/m, z0\.s, z0\.s
2496 [^ :]+:[0-9]+: Info:            uhsub z0\.d, p0/m, z0\.d, z0\.d
2497 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uhsubr z32\.b,p0/m,z0\.b,z0\.b'
2498 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uhsubr z0\.b,p0/m,z32\.b,z0\.b'
2499 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uhsubr z0\.b,p0/m,z0\.b,z32\.b'
2500 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uhsubr z0\.b,p0/m,z1\.b,z0\.b'
2501 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uhsubr z0\.b,p8/m,z0\.b,z0\.b'
2502 [^ :]+:[0-9]+: Error: operand mismatch -- `uhsubr z0\.h,p0/m,z0\.b,z0\.b'
2503 [^ :]+:[0-9]+: Info:    did you mean this\?
2504 [^ :]+:[0-9]+: Info:            uhsubr z0\.b, p0/m, z0\.b, z0\.b
2505 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2506 [^ :]+:[0-9]+: Info:            uhsubr z0\.h, p0/m, z0\.h, z0\.h
2507 [^ :]+:[0-9]+: Info:            uhsubr z0\.s, p0/m, z0\.s, z0\.s
2508 [^ :]+:[0-9]+: Info:            uhsubr z0\.d, p0/m, z0\.d, z0\.d
2509 [^ :]+:[0-9]+: Error: operand mismatch -- `uhsubr z0\.b,p0/z,z0\.b,z0\.b'
2510 [^ :]+:[0-9]+: Info:    did you mean this\?
2511 [^ :]+:[0-9]+: Info:            uhsubr z0\.b, p0/m, z0\.b, z0\.b
2512 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2513 [^ :]+:[0-9]+: Info:            uhsubr z0\.h, p0/m, z0\.h, z0\.h
2514 [^ :]+:[0-9]+: Info:            uhsubr z0\.s, p0/m, z0\.s, z0\.s
2515 [^ :]+:[0-9]+: Info:            uhsubr z0\.d, p0/m, z0\.d, z0\.d
2516 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umaxp z32\.b,p0/m,z0\.b,z0\.b'
2517 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `umaxp z0\.b,p0/m,z32\.b,z0\.b'
2518 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `umaxp z0\.b,p0/m,z0\.b,z32\.b'
2519 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `umaxp z0\.b,p0/m,z1\.b,z0\.b'
2520 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `umaxp z0\.b,p8/m,z0\.b,z0\.b'
2521 [^ :]+:[0-9]+: Error: operand mismatch -- `umaxp z0\.h,p0/m,z0\.b,z0\.b'
2522 [^ :]+:[0-9]+: Info:    did you mean this\?
2523 [^ :]+:[0-9]+: Info:            umaxp z0\.b, p0/m, z0\.b, z0\.b
2524 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2525 [^ :]+:[0-9]+: Info:            umaxp z0\.h, p0/m, z0\.h, z0\.h
2526 [^ :]+:[0-9]+: Info:            umaxp z0\.s, p0/m, z0\.s, z0\.s
2527 [^ :]+:[0-9]+: Info:            umaxp z0\.d, p0/m, z0\.d, z0\.d
2528 [^ :]+:[0-9]+: Error: operand mismatch -- `umaxp z0\.b,p0/z,z0\.b,z0\.b'
2529 [^ :]+:[0-9]+: Info:    did you mean this\?
2530 [^ :]+:[0-9]+: Info:            umaxp z0\.b, p0/m, z0\.b, z0\.b
2531 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2532 [^ :]+:[0-9]+: Info:            umaxp z0\.h, p0/m, z0\.h, z0\.h
2533 [^ :]+:[0-9]+: Info:            umaxp z0\.s, p0/m, z0\.s, z0\.s
2534 [^ :]+:[0-9]+: Info:            umaxp z0\.d, p0/m, z0\.d, z0\.d
2535 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uminp z32\.b,p0/m,z0\.b,z0\.b'
2536 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uminp z0\.b,p0/m,z32\.b,z0\.b'
2537 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uminp z0\.b,p0/m,z0\.b,z32\.b'
2538 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uminp z0\.b,p0/m,z1\.b,z0\.b'
2539 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uminp z0\.b,p8/m,z0\.b,z0\.b'
2540 [^ :]+:[0-9]+: Error: operand mismatch -- `uminp z0\.h,p0/m,z0\.b,z0\.b'
2541 [^ :]+:[0-9]+: Info:    did you mean this\?
2542 [^ :]+:[0-9]+: Info:            uminp z0\.b, p0/m, z0\.b, z0\.b
2543 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2544 [^ :]+:[0-9]+: Info:            uminp z0\.h, p0/m, z0\.h, z0\.h
2545 [^ :]+:[0-9]+: Info:            uminp z0\.s, p0/m, z0\.s, z0\.s
2546 [^ :]+:[0-9]+: Info:            uminp z0\.d, p0/m, z0\.d, z0\.d
2547 [^ :]+:[0-9]+: Error: operand mismatch -- `uminp z0\.b,p0/z,z0\.b,z0\.b'
2548 [^ :]+:[0-9]+: Info:    did you mean this\?
2549 [^ :]+:[0-9]+: Info:            uminp z0\.b, p0/m, z0\.b, z0\.b
2550 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2551 [^ :]+:[0-9]+: Info:            uminp z0\.h, p0/m, z0\.h, z0\.h
2552 [^ :]+:[0-9]+: Info:            uminp z0\.s, p0/m, z0\.s, z0\.s
2553 [^ :]+:[0-9]+: Info:            uminp z0\.d, p0/m, z0\.d, z0\.d
2554 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalb z32\.s,z0\.h,z0\.h\[0\]'
2555 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalb z0\.s,z32\.h,z0\.h\[0\]'
2556 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlalb z0\.s,z0\.h,z8\.h\[0\]'
2557 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlalb z0\.s,z0\.h,z0\.h\[8\]'
2558 [^ :]+:[0-9]+: Error: operand mismatch -- `umlalb z0\.h,z0\.h,z0\.h\[0\]'
2559 [^ :]+:[0-9]+: Info:    did you mean this\?
2560 [^ :]+:[0-9]+: Info:            umlalb z0\.d, z0\.s, z0\.s\[0\]
2561 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalb z32\.d,z0\.s,z0\.s\[0\]'
2562 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalb z0\.d,z32\.s,z0\.s\[0\]'
2563 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlalb z0\.d,z0\.s,z16\.s\[0\]'
2564 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlalb z0\.d,z0\.s,z0\.s\[4\]'
2565 [^ :]+:[0-9]+: Error: operand mismatch -- `umlalb z0\.s,z0\.s,z0\.s\[0\]'
2566 [^ :]+:[0-9]+: Info:    did you mean this\?
2567 [^ :]+:[0-9]+: Info:            umlalb z0\.d, z0\.s, z0\.s\[0\]
2568 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalb z32\.h,z0\.b,z0\.b'
2569 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalb z0\.h,z32\.b,z0\.b'
2570 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlalb z0\.h,z0\.b,z32\.b'
2571 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlalb z0\.s,z0\.h,z0\.x'
2572 [^ :]+:[0-9]+: Error: operand mismatch -- `umlalb z0\.h,z0\.b,z0\.h'
2573 [^ :]+:[0-9]+: Info:    did you mean this\?
2574 [^ :]+:[0-9]+: Info:            umlalb z0\.h, z0\.b, z0\.b
2575 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2576 [^ :]+:[0-9]+: Info:            umlalb z0\.s, z0\.h, z0\.h
2577 [^ :]+:[0-9]+: Info:            umlalb z0\.d, z0\.s, z0\.s
2578 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalt z32\.s,z0\.h,z0\.h\[0\]'
2579 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalt z0\.s,z32\.h,z0\.h\[0\]'
2580 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlalt z0\.s,z0\.h,z8\.h\[0\]'
2581 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlalt z0\.s,z0\.h,z0\.h\[8\]'
2582 [^ :]+:[0-9]+: Error: operand mismatch -- `umlalt z0\.h,z0\.h,z0\.h\[0\]'
2583 [^ :]+:[0-9]+: Info:    did you mean this\?
2584 [^ :]+:[0-9]+: Info:            umlalt z0\.d, z0\.s, z0\.s\[0\]
2585 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalt z32\.d,z0\.s,z0\.s\[0\]'
2586 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalt z0\.d,z32\.s,z0\.s\[0\]'
2587 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlalt z0\.d,z0\.s,z16\.s\[0\]'
2588 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlalt z0\.d,z0\.s,z0\.s\[4\]'
2589 [^ :]+:[0-9]+: Error: operand mismatch -- `umlalt z0\.s,z0\.s,z0\.s\[0\]'
2590 [^ :]+:[0-9]+: Info:    did you mean this\?
2591 [^ :]+:[0-9]+: Info:            umlalt z0\.d, z0\.s, z0\.s\[0\]
2592 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalt z32\.h,z0\.b,z0\.b'
2593 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalt z0\.h,z32\.b,z0\.b'
2594 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlalt z0\.h,z0\.b,z32\.b'
2595 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlalt z0\.s,z0\.h,z0\.x'
2596 [^ :]+:[0-9]+: Error: operand mismatch -- `umlalt z0\.h,z0\.b,z0\.h'
2597 [^ :]+:[0-9]+: Info:    did you mean this\?
2598 [^ :]+:[0-9]+: Info:            umlalt z0\.h, z0\.b, z0\.b
2599 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2600 [^ :]+:[0-9]+: Info:            umlalt z0\.s, z0\.h, z0\.h
2601 [^ :]+:[0-9]+: Info:            umlalt z0\.d, z0\.s, z0\.s
2602 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslb z32\.s,z0\.h,z0\.h\[0\]'
2603 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslb z0\.s,z32\.h,z0\.h\[0\]'
2604 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlslb z0\.s,z0\.h,z8\.h\[0\]'
2605 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlslb z0\.s,z0\.h,z0\.h\[8\]'
2606 [^ :]+:[0-9]+: Error: operand mismatch -- `umlslb z0\.h,z0\.h,z0\.h\[0\]'
2607 [^ :]+:[0-9]+: Info:    did you mean this\?
2608 [^ :]+:[0-9]+: Info:            umlslb z0\.d, z0\.s, z0\.s\[0\]
2609 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslb z32\.d,z0\.s,z0\.s\[0\]'
2610 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslb z0\.d,z32\.s,z0\.s\[0\]'
2611 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlslb z0\.d,z0\.s,z16\.s\[0\]'
2612 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlslb z0\.d,z0\.s,z0\.s\[4\]'
2613 [^ :]+:[0-9]+: Error: operand mismatch -- `umlslb z0\.s,z0\.s,z0\.s\[0\]'
2614 [^ :]+:[0-9]+: Info:    did you mean this\?
2615 [^ :]+:[0-9]+: Info:            umlslb z0\.d, z0\.s, z0\.s\[0\]
2616 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslb z32\.h,z0\.b,z0\.b'
2617 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslb z0\.h,z32\.b,z0\.b'
2618 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlslb z0\.h,z0\.b,z32\.b'
2619 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlslb z0\.s,z0\.h,z0\.x'
2620 [^ :]+:[0-9]+: Error: operand mismatch -- `umlslb z0\.h,z0\.b,z0\.h'
2621 [^ :]+:[0-9]+: Info:    did you mean this\?
2622 [^ :]+:[0-9]+: Info:            umlslb z0\.h, z0\.b, z0\.b
2623 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2624 [^ :]+:[0-9]+: Info:            umlslb z0\.s, z0\.h, z0\.h
2625 [^ :]+:[0-9]+: Info:            umlslb z0\.d, z0\.s, z0\.s
2626 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslt z32\.s,z0\.h,z0\.h\[0\]'
2627 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslt z0\.s,z32\.h,z0\.h\[0\]'
2628 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlslt z0\.s,z0\.h,z8\.h\[0\]'
2629 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlslt z0\.s,z0\.h,z0\.h\[8\]'
2630 [^ :]+:[0-9]+: Error: operand mismatch -- `umlslt z0\.h,z0\.h,z0\.h\[0\]'
2631 [^ :]+:[0-9]+: Info:    did you mean this\?
2632 [^ :]+:[0-9]+: Info:            umlslt z0\.d, z0\.s, z0\.s\[0\]
2633 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslt z32\.d,z0\.s,z0\.s\[0\]'
2634 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslt z0\.d,z32\.s,z0\.s\[0\]'
2635 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlslt z0\.d,z0\.s,z16\.s\[0\]'
2636 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlslt z0\.d,z0\.s,z0\.s\[4\]'
2637 [^ :]+:[0-9]+: Error: operand mismatch -- `umlslt z0\.s,z0\.s,z0\.s\[0\]'
2638 [^ :]+:[0-9]+: Info:    did you mean this\?
2639 [^ :]+:[0-9]+: Info:            umlslt z0\.d, z0\.s, z0\.s\[0\]
2640 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslt z32\.h,z0\.b,z0\.b'
2641 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslt z0\.h,z32\.b,z0\.b'
2642 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlslt z0\.h,z0\.b,z32\.b'
2643 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlslt z0\.s,z0\.h,z0\.x'
2644 [^ :]+:[0-9]+: Error: operand mismatch -- `umlslt z0\.h,z0\.b,z0\.h'
2645 [^ :]+:[0-9]+: Info:    did you mean this\?
2646 [^ :]+:[0-9]+: Info:            umlslt z0\.h, z0\.b, z0\.b
2647 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2648 [^ :]+:[0-9]+: Info:            umlslt z0\.s, z0\.h, z0\.h
2649 [^ :]+:[0-9]+: Info:            umlslt z0\.d, z0\.s, z0\.s
2650 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umulh z32\.h,z0\.b,z0\.b'
2651 [^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `umulh z0\.h,z32\.b,z0\.b'
2652 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `umulh z0\.h,z0\.b,z32\.b'
2653 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umulh z0\.s,z0\.h,z0\.x'
2654 [^ :]+:[0-9]+: Error: operand mismatch -- `umulh z0\.h,z0\.b,z0\.h'
2655 [^ :]+:[0-9]+: Info:    did you mean this\?
2656 [^ :]+:[0-9]+: Info:            umulh z0\.h, z0\.h, z0\.h
2657 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2658 [^ :]+:[0-9]+: Info:            umulh z0\.b, z0\.b, z0\.b
2659 [^ :]+:[0-9]+: Info:            umulh z0\.s, z0\.s, z0\.s
2660 [^ :]+:[0-9]+: Info:            umulh z0\.d, z0\.d, z0\.d
2661 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullb z32\.s,z0\.h,z0\.h\[0\]'
2662 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullb z0\.s,z32\.h,z0\.h\[0\]'
2663 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umullb z0\.s,z0\.h,z8\.h\[0\]'
2664 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umullb z0\.s,z0\.h,z0\.h\[8\]'
2665 [^ :]+:[0-9]+: Error: operand mismatch -- `umullb z0\.h,z0\.h,z0\.h\[0\]'
2666 [^ :]+:[0-9]+: Info:    did you mean this\?
2667 [^ :]+:[0-9]+: Info:            umullb z0\.d, z0\.s, z0\.s\[0\]
2668 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullb z32\.d,z0\.s,z0\.s\[0\]'
2669 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullb z0\.d,z32\.s,z0\.s\[0\]'
2670 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umullb z0\.d,z0\.s,z16\.s\[0\]'
2671 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umullb z0\.d,z0\.s,z0\.s\[4\]'
2672 [^ :]+:[0-9]+: Error: operand mismatch -- `umullb z0\.s,z0\.s,z0\.s\[0\]'
2673 [^ :]+:[0-9]+: Info:    did you mean this\?
2674 [^ :]+:[0-9]+: Info:            umullb z0\.d, z0\.s, z0\.s\[0\]
2675 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullb z32\.h,z0\.b,z0\.b'
2676 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullb z0\.h,z32\.b,z0\.b'
2677 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umullb z0\.h,z0\.b,z32\.b'
2678 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umullb z0\.s,z0\.h,z0\.x'
2679 [^ :]+:[0-9]+: Error: operand mismatch -- `umullb z0\.h,z0\.b,z0\.h'
2680 [^ :]+:[0-9]+: Info:    did you mean this\?
2681 [^ :]+:[0-9]+: Info:            umullb z0\.h, z0\.b, z0\.b
2682 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2683 [^ :]+:[0-9]+: Info:            umullb z0\.s, z0\.h, z0\.h
2684 [^ :]+:[0-9]+: Info:            umullb z0\.d, z0\.s, z0\.s
2685 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullt z32\.s,z0\.h,z0\.h\[0\]'
2686 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullt z0\.s,z32\.h,z0\.h\[0\]'
2687 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umullt z0\.s,z0\.h,z8\.h\[0\]'
2688 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umullt z0\.s,z0\.h,z0\.h\[8\]'
2689 [^ :]+:[0-9]+: Error: operand mismatch -- `umullt z0\.h,z0\.h,z0\.h\[0\]'
2690 [^ :]+:[0-9]+: Info:    did you mean this\?
2691 [^ :]+:[0-9]+: Info:            umullt z0\.d, z0\.s, z0\.s\[0\]
2692 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullt z32\.d,z0\.s,z0\.s\[0\]'
2693 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullt z0\.d,z32\.s,z0\.s\[0\]'
2694 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umullt z0\.d,z0\.s,z16\.s\[0\]'
2695 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umullt z0\.d,z0\.s,z0\.s\[4\]'
2696 [^ :]+:[0-9]+: Error: operand mismatch -- `umullt z0\.s,z0\.s,z0\.s\[0\]'
2697 [^ :]+:[0-9]+: Info:    did you mean this\?
2698 [^ :]+:[0-9]+: Info:            umullt z0\.d, z0\.s, z0\.s\[0\]
2699 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullt z32\.h,z0\.b,z0\.b'
2700 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullt z0\.h,z32\.b,z0\.b'
2701 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umullt z0\.h,z0\.b,z32\.b'
2702 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umullt z0\.s,z0\.h,z0\.x'
2703 [^ :]+:[0-9]+: Error: operand mismatch -- `umullt z0\.h,z0\.b,z0\.h'
2704 [^ :]+:[0-9]+: Info:    did you mean this\?
2705 [^ :]+:[0-9]+: Info:            umullt z0\.h, z0\.b, z0\.b
2706 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2707 [^ :]+:[0-9]+: Info:            umullt z0\.s, z0\.h, z0\.h
2708 [^ :]+:[0-9]+: Info:            umullt z0\.d, z0\.s, z0\.s
2709 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `uqadd z32\.b,p0/m,z0\.b,z0\.b'
2710 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqadd z0\.b,p0/m,z32\.b,z0\.b'
2711 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqadd z0\.b,p0/m,z0\.b,z32\.b'
2712 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqadd z0\.b,p0/m,z1\.b,z0\.b'
2713 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqadd z0\.b,p8/m,z0\.b,z0\.b'
2714 [^ :]+:[0-9]+: Error: operand mismatch -- `uqadd z0\.h,p0/m,z0\.b,z0\.b'
2715 [^ :]+:[0-9]+: Info:    did you mean this\?
2716 [^ :]+:[0-9]+: Info:            uqadd z0\.b, p0/m, z0\.b, z0\.b
2717 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2718 [^ :]+:[0-9]+: Info:            uqadd z0\.h, p0/m, z0\.h, z0\.h
2719 [^ :]+:[0-9]+: Info:            uqadd z0\.s, p0/m, z0\.s, z0\.s
2720 [^ :]+:[0-9]+: Info:            uqadd z0\.d, p0/m, z0\.d, z0\.d
2721 [^ :]+:[0-9]+: Error: operand mismatch -- `uqadd z0\.b,p0/z,z0\.b,z0\.b'
2722 [^ :]+:[0-9]+: Info:    did you mean this\?
2723 [^ :]+:[0-9]+: Info:            uqadd z0\.b, p0/m, z0\.b, z0\.b
2724 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2725 [^ :]+:[0-9]+: Info:            uqadd z0\.h, p0/m, z0\.h, z0\.h
2726 [^ :]+:[0-9]+: Info:            uqadd z0\.s, p0/m, z0\.s, z0\.s
2727 [^ :]+:[0-9]+: Info:            uqadd z0\.d, p0/m, z0\.d, z0\.d
2728 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `uqrshl z32\.b,p0/m,z0\.b,z0\.b'
2729 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqrshl z0\.b,p0/m,z32\.b,z0\.b'
2730 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqrshl z0\.b,p0/m,z0\.b,z32\.b'
2731 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqrshl z0\.b,p0/m,z1\.b,z0\.b'
2732 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqrshl z0\.b,p8/m,z0\.b,z0\.b'
2733 [^ :]+:[0-9]+: Error: operand mismatch -- `uqrshl z0\.h,p0/m,z0\.b,z0\.b'
2734 [^ :]+:[0-9]+: Info:    did you mean this\?
2735 [^ :]+:[0-9]+: Info:            uqrshl z0\.b, p0/m, z0\.b, z0\.b
2736 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2737 [^ :]+:[0-9]+: Info:            uqrshl z0\.h, p0/m, z0\.h, z0\.h
2738 [^ :]+:[0-9]+: Info:            uqrshl z0\.s, p0/m, z0\.s, z0\.s
2739 [^ :]+:[0-9]+: Info:            uqrshl z0\.d, p0/m, z0\.d, z0\.d
2740 [^ :]+:[0-9]+: Error: operand mismatch -- `uqrshl z0\.b,p0/z,z0\.b,z0\.b'
2741 [^ :]+:[0-9]+: Info:    did you mean this\?
2742 [^ :]+:[0-9]+: Info:            uqrshl z0\.b, p0/m, z0\.b, z0\.b
2743 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2744 [^ :]+:[0-9]+: Info:            uqrshl z0\.h, p0/m, z0\.h, z0\.h
2745 [^ :]+:[0-9]+: Info:            uqrshl z0\.s, p0/m, z0\.s, z0\.s
2746 [^ :]+:[0-9]+: Info:            uqrshl z0\.d, p0/m, z0\.d, z0\.d
2747 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqrshlr z32\.b,p0/m,z0\.b,z0\.b'
2748 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqrshlr z0\.b,p0/m,z32\.b,z0\.b'
2749 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqrshlr z0\.b,p0/m,z0\.b,z32\.b'
2750 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqrshlr z0\.b,p0/m,z1\.b,z0\.b'
2751 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqrshlr z0\.b,p8/m,z0\.b,z0\.b'
2752 [^ :]+:[0-9]+: Error: operand mismatch -- `uqrshlr z0\.h,p0/m,z0\.b,z0\.b'
2753 [^ :]+:[0-9]+: Info:    did you mean this\?
2754 [^ :]+:[0-9]+: Info:            uqrshlr z0\.b, p0/m, z0\.b, z0\.b
2755 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2756 [^ :]+:[0-9]+: Info:            uqrshlr z0\.h, p0/m, z0\.h, z0\.h
2757 [^ :]+:[0-9]+: Info:            uqrshlr z0\.s, p0/m, z0\.s, z0\.s
2758 [^ :]+:[0-9]+: Info:            uqrshlr z0\.d, p0/m, z0\.d, z0\.d
2759 [^ :]+:[0-9]+: Error: operand mismatch -- `uqrshlr z0\.b,p0/z,z0\.b,z0\.b'
2760 [^ :]+:[0-9]+: Info:    did you mean this\?
2761 [^ :]+:[0-9]+: Info:            uqrshlr z0\.b, p0/m, z0\.b, z0\.b
2762 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2763 [^ :]+:[0-9]+: Info:            uqrshlr z0\.h, p0/m, z0\.h, z0\.h
2764 [^ :]+:[0-9]+: Info:            uqrshlr z0\.s, p0/m, z0\.s, z0\.s
2765 [^ :]+:[0-9]+: Info:            uqrshlr z0\.d, p0/m, z0\.d, z0\.d
2766 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqrshrnb z32\.b,z0\.h,#8'
2767 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqrshrnb z0\.b,z32\.h,#8'
2768 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnb z0\.b,z0\.h,#9'
2769 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnb z0\.b,z0\.h,#0'
2770 [^ :]+:[0-9]+: Error: operand mismatch -- `uqrshrnb z0\.h,z0\.h,#8'
2771 [^ :]+:[0-9]+: Info:    did you mean this\?
2772 [^ :]+:[0-9]+: Info:            uqrshrnb z0\.b, z0\.h, #8
2773 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2774 [^ :]+:[0-9]+: Info:            uqrshrnb z0\.h, z0\.s, #8
2775 [^ :]+:[0-9]+: Info:            uqrshrnb z0\.s, z0\.d, #8
2776 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqrshrnb z0\.h,z0\.s,#0'
2777 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqrshrnb z0\.h,z0\.s,#17'
2778 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqrshrnb z0\.s,z0\.d,#0'
2779 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqrshrnb z0\.s,z0\.d,#33'
2780 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `uqrshrnt z0\.b,z0\.h,#1'
2781 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqrshrnt z32\.b,z0\.h,#8'
2782 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqrshrnt z0\.b,z32\.h,#8'
2783 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnt z0\.b,z0\.h,#9'
2784 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnt z0\.b,z0\.h,#0'
2785 [^ :]+:[0-9]+: Error: operand mismatch -- `uqrshrnt z0\.h,z0\.h,#8'
2786 [^ :]+:[0-9]+: Info:    did you mean this\?
2787 [^ :]+:[0-9]+: Info:            uqrshrnt z0\.b, z0\.h, #8
2788 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2789 [^ :]+:[0-9]+: Info:            uqrshrnt z0\.h, z0\.s, #8
2790 [^ :]+:[0-9]+: Info:            uqrshrnt z0\.s, z0\.d, #8
2791 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqrshrnt z0\.h,z0\.s,#0'
2792 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqrshrnt z0\.h,z0\.s,#17'
2793 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqrshrnt z0\.s,z0\.d,#0'
2794 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqrshrnt z0\.s,z0\.d,#33'
2795 [^ :]+:[0-9]+: Error: operand mismatch -- `uqshl z0\.h,p0/m,z0\.b,#0'
2796 [^ :]+:[0-9]+: Info:    did you mean this\?
2797 [^ :]+:[0-9]+: Info:            uqshl z0\.b, p0/m, z0\.b, #0
2798 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2799 [^ :]+:[0-9]+: Info:            uqshl z0\.h, p0/m, z0\.h, #0
2800 [^ :]+:[0-9]+: Info:            uqshl z0\.s, p0/m, z0\.s, #0
2801 [^ :]+:[0-9]+: Info:            uqshl z0\.d, p0/m, z0\.d, #0
2802 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `uqshl z32\.b,p0/m,z32\.b,#0'
2803 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqshl z0\.b,p0/m,z1\.b,#0'
2804 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqshl z0\.b,p8/m,z0\.b,#0'
2805 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 4 -- `uqshl z0\.b,p0/m,z0\.b,#8'
2806 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `uqshl z0\.h,p0/m,z0\.h,#16'
2807 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 4 -- `uqshl z0\.s,p0/m,z0\.s,#32'
2808 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 4 -- `uqshl z0\.d,p0/m,z0\.d,#64'
2809 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `uqshl z32\.b,p0/m,z0\.b,z0\.b'
2810 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqshl z0\.b,p0/m,z32\.b,z0\.b'
2811 [^ :]+:[0-9]+: Error: constant expression required at operand 4 -- `uqshl z0\.b,p0/m,z0\.b,z32\.b'
2812 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqshl z0\.b,p0/m,z1\.b,z0\.b'
2813 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqshl z0\.b,p8/m,z0\.b,z0\.b'
2814 [^ :]+:[0-9]+: Error: operand mismatch -- `uqshl z0\.h,p0/m,z0\.b,z0\.b'
2815 [^ :]+:[0-9]+: Info:    did you mean this\?
2816 [^ :]+:[0-9]+: Info:            uqshl z0\.b, p0/m, z0\.b, z0\.b
2817 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2818 [^ :]+:[0-9]+: Info:            uqshl z0\.h, p0/m, z0\.h, z0\.h
2819 [^ :]+:[0-9]+: Info:            uqshl z0\.s, p0/m, z0\.s, z0\.s
2820 [^ :]+:[0-9]+: Info:            uqshl z0\.d, p0/m, z0\.d, z0\.d
2821 [^ :]+:[0-9]+: Error: operand mismatch -- `uqshl z0\.b,p0/z,z0\.b,z0\.b'
2822 [^ :]+:[0-9]+: Info:    did you mean this\?
2823 [^ :]+:[0-9]+: Info:            uqshl z0\.b, p0/m, z0\.b, z0\.b
2824 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2825 [^ :]+:[0-9]+: Info:            uqshl z0\.h, p0/m, z0\.h, z0\.h
2826 [^ :]+:[0-9]+: Info:            uqshl z0\.s, p0/m, z0\.s, z0\.s
2827 [^ :]+:[0-9]+: Info:            uqshl z0\.d, p0/m, z0\.d, z0\.d
2828 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqshlr z32\.b,p0/m,z0\.b,z0\.b'
2829 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqshlr z0\.b,p0/m,z32\.b,z0\.b'
2830 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqshlr z0\.b,p0/m,z0\.b,z32\.b'
2831 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqshlr z0\.b,p0/m,z1\.b,z0\.b'
2832 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqshlr z0\.b,p8/m,z0\.b,z0\.b'
2833 [^ :]+:[0-9]+: Error: operand mismatch -- `uqshlr z0\.h,p0/m,z0\.b,z0\.b'
2834 [^ :]+:[0-9]+: Info:    did you mean this\?
2835 [^ :]+:[0-9]+: Info:            uqshlr z0\.b, p0/m, z0\.b, z0\.b
2836 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2837 [^ :]+:[0-9]+: Info:            uqshlr z0\.h, p0/m, z0\.h, z0\.h
2838 [^ :]+:[0-9]+: Info:            uqshlr z0\.s, p0/m, z0\.s, z0\.s
2839 [^ :]+:[0-9]+: Info:            uqshlr z0\.d, p0/m, z0\.d, z0\.d
2840 [^ :]+:[0-9]+: Error: operand mismatch -- `uqshlr z0\.b,p0/z,z0\.b,z0\.b'
2841 [^ :]+:[0-9]+: Info:    did you mean this\?
2842 [^ :]+:[0-9]+: Info:            uqshlr z0\.b, p0/m, z0\.b, z0\.b
2843 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2844 [^ :]+:[0-9]+: Info:            uqshlr z0\.h, p0/m, z0\.h, z0\.h
2845 [^ :]+:[0-9]+: Info:            uqshlr z0\.s, p0/m, z0\.s, z0\.s
2846 [^ :]+:[0-9]+: Info:            uqshlr z0\.d, p0/m, z0\.d, z0\.d
2847 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqshrnb z32\.b,z0\.h,#8'
2848 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqshrnb z0\.b,z32\.h,#8'
2849 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnb z0\.b,z0\.h,#9'
2850 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnb z0\.b,z0\.h,#0'
2851 [^ :]+:[0-9]+: Error: operand mismatch -- `uqshrnb z0\.h,z0\.h,#8'
2852 [^ :]+:[0-9]+: Info:    did you mean this\?
2853 [^ :]+:[0-9]+: Info:            uqshrnb z0\.b, z0\.h, #8
2854 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2855 [^ :]+:[0-9]+: Info:            uqshrnb z0\.h, z0\.s, #8
2856 [^ :]+:[0-9]+: Info:            uqshrnb z0\.s, z0\.d, #8
2857 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqshrnb z0\.h,z0\.s,#0'
2858 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqshrnb z0\.h,z0\.s,#17'
2859 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnb z0\.s,z0\.d,#0'
2860 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnb z0\.s,z0\.d,#33'
2861 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `uqshrnt z0\.b,z0\.h,#1'
2862 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqshrnt z32\.b,z0\.h,#8'
2863 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqshrnt z0\.b,z32\.h,#8'
2864 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnt z0\.b,z0\.h,#9'
2865 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnt z0\.b,z0\.h,#0'
2866 [^ :]+:[0-9]+: Error: operand mismatch -- `uqshrnt z0\.h,z0\.h,#8'
2867 [^ :]+:[0-9]+: Info:    did you mean this\?
2868 [^ :]+:[0-9]+: Info:            uqshrnt z0\.b, z0\.h, #8
2869 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2870 [^ :]+:[0-9]+: Info:            uqshrnt z0\.h, z0\.s, #8
2871 [^ :]+:[0-9]+: Info:            uqshrnt z0\.s, z0\.d, #8
2872 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqshrnt z0\.h,z0\.s,#0'
2873 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqshrnt z0\.h,z0\.s,#17'
2874 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnt z0\.s,z0\.d,#0'
2875 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnt z0\.s,z0\.d,#33'
2876 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `uqsub z32\.b,p0/m,z0\.b,z0\.b'
2877 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqsub z0\.b,p0/m,z32\.b,z0\.b'
2878 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqsub z0\.b,p0/m,z0\.b,z32\.b'
2879 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqsub z0\.b,p0/m,z1\.b,z0\.b'
2880 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqsub z0\.b,p8/m,z0\.b,z0\.b'
2881 [^ :]+:[0-9]+: Error: operand mismatch -- `uqsub z0\.h,p0/m,z0\.b,z0\.b'
2882 [^ :]+:[0-9]+: Info:    did you mean this\?
2883 [^ :]+:[0-9]+: Info:            uqsub z0\.b, p0/m, z0\.b, z0\.b
2884 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2885 [^ :]+:[0-9]+: Info:            uqsub z0\.h, p0/m, z0\.h, z0\.h
2886 [^ :]+:[0-9]+: Info:            uqsub z0\.s, p0/m, z0\.s, z0\.s
2887 [^ :]+:[0-9]+: Info:            uqsub z0\.d, p0/m, z0\.d, z0\.d
2888 [^ :]+:[0-9]+: Error: operand mismatch -- `uqsub z0\.b,p0/z,z0\.b,z0\.b'
2889 [^ :]+:[0-9]+: Info:    did you mean this\?
2890 [^ :]+:[0-9]+: Info:            uqsub z0\.b, p0/m, z0\.b, z0\.b
2891 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2892 [^ :]+:[0-9]+: Info:            uqsub z0\.h, p0/m, z0\.h, z0\.h
2893 [^ :]+:[0-9]+: Info:            uqsub z0\.s, p0/m, z0\.s, z0\.s
2894 [^ :]+:[0-9]+: Info:            uqsub z0\.d, p0/m, z0\.d, z0\.d
2895 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqsubr z32\.b,p0/m,z0\.b,z0\.b'
2896 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqsubr z0\.b,p0/m,z32\.b,z0\.b'
2897 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqsubr z0\.b,p0/m,z0\.b,z32\.b'
2898 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqsubr z0\.b,p0/m,z1\.b,z0\.b'
2899 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqsubr z0\.b,p8/m,z0\.b,z0\.b'
2900 [^ :]+:[0-9]+: Error: operand mismatch -- `uqsubr z0\.h,p0/m,z0\.b,z0\.b'
2901 [^ :]+:[0-9]+: Info:    did you mean this\?
2902 [^ :]+:[0-9]+: Info:            uqsubr z0\.b, p0/m, z0\.b, z0\.b
2903 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2904 [^ :]+:[0-9]+: Info:            uqsubr z0\.h, p0/m, z0\.h, z0\.h
2905 [^ :]+:[0-9]+: Info:            uqsubr z0\.s, p0/m, z0\.s, z0\.s
2906 [^ :]+:[0-9]+: Info:            uqsubr z0\.d, p0/m, z0\.d, z0\.d
2907 [^ :]+:[0-9]+: Error: operand mismatch -- `uqsubr z0\.b,p0/z,z0\.b,z0\.b'
2908 [^ :]+:[0-9]+: Info:    did you mean this\?
2909 [^ :]+:[0-9]+: Info:            uqsubr z0\.b, p0/m, z0\.b, z0\.b
2910 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2911 [^ :]+:[0-9]+: Info:            uqsubr z0\.h, p0/m, z0\.h, z0\.h
2912 [^ :]+:[0-9]+: Info:            uqsubr z0\.s, p0/m, z0\.s, z0\.s
2913 [^ :]+:[0-9]+: Info:            uqsubr z0\.d, p0/m, z0\.d, z0\.d
2914 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqxtnb z32\.b,z0\.h'
2915 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqxtnb z0\.b,z32\.h'
2916 [^ :]+:[0-9]+: Error: operand mismatch -- `uqxtnb z0\.b,z0\.s'
2917 [^ :]+:[0-9]+: Info:    did you mean this\?
2918 [^ :]+:[0-9]+: Info:            uqxtnb z0\.b, z0\.h
2919 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2920 [^ :]+:[0-9]+: Info:            uqxtnb z0\.h, z0\.s
2921 [^ :]+:[0-9]+: Info:            uqxtnb z0\.s, z0\.d
2922 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqxtnt z32\.b,z0\.h'
2923 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqxtnt z0\.b,z32\.h'
2924 [^ :]+:[0-9]+: Error: operand mismatch -- `uqxtnt z0\.b,z0\.s'
2925 [^ :]+:[0-9]+: Info:    did you mean this\?
2926 [^ :]+:[0-9]+: Info:            uqxtnt z0\.b, z0\.h
2927 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2928 [^ :]+:[0-9]+: Info:            uqxtnt z0\.h, z0\.s
2929 [^ :]+:[0-9]+: Info:            uqxtnt z0\.s, z0\.d
2930 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `urecpe z32\.s,p0/m,z0\.s'
2931 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urecpe z0\.s,p0/m,z32\.s'
2932 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urecpe z0\.s,p8/m,z0\.s'
2933 [^ :]+:[0-9]+: Error: operand mismatch -- `urecpe z0\.d,p0/m,z0\.s'
2934 [^ :]+:[0-9]+: Info:    did you mean this\?
2935 [^ :]+:[0-9]+: Info:            urecpe z0\.s, p0/m, z0\.s
2936 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `urhadd z32\.b,p0/m,z0\.b,z0\.b'
2937 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urhadd z0\.b,p0/m,z32\.b,z0\.b'
2938 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `urhadd z0\.b,p0/m,z0\.b,z32\.b'
2939 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urhadd z0\.b,p0/m,z1\.b,z0\.b'
2940 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urhadd z0\.b,p8/m,z0\.b,z0\.b'
2941 [^ :]+:[0-9]+: Error: operand mismatch -- `urhadd z0\.h,p0/m,z0\.b,z0\.b'
2942 [^ :]+:[0-9]+: Info:    did you mean this\?
2943 [^ :]+:[0-9]+: Info:            urhadd z0\.b, p0/m, z0\.b, z0\.b
2944 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2945 [^ :]+:[0-9]+: Info:            urhadd z0\.h, p0/m, z0\.h, z0\.h
2946 [^ :]+:[0-9]+: Info:            urhadd z0\.s, p0/m, z0\.s, z0\.s
2947 [^ :]+:[0-9]+: Info:            urhadd z0\.d, p0/m, z0\.d, z0\.d
2948 [^ :]+:[0-9]+: Error: operand mismatch -- `urhadd z0\.b,p0/z,z0\.b,z0\.b'
2949 [^ :]+:[0-9]+: Info:    did you mean this\?
2950 [^ :]+:[0-9]+: Info:            urhadd z0\.b, p0/m, z0\.b, z0\.b
2951 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2952 [^ :]+:[0-9]+: Info:            urhadd z0\.h, p0/m, z0\.h, z0\.h
2953 [^ :]+:[0-9]+: Info:            urhadd z0\.s, p0/m, z0\.s, z0\.s
2954 [^ :]+:[0-9]+: Info:            urhadd z0\.d, p0/m, z0\.d, z0\.d
2955 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `urshl z32\.b,p0/m,z0\.b,z0\.b'
2956 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urshl z0\.b,p0/m,z32\.b,z0\.b'
2957 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `urshl z0\.b,p0/m,z0\.b,z32\.b'
2958 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urshl z0\.b,p0/m,z1\.b,z0\.b'
2959 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urshl z0\.b,p8/m,z0\.b,z0\.b'
2960 [^ :]+:[0-9]+: Error: operand mismatch -- `urshl z0\.h,p0/m,z0\.b,z0\.b'
2961 [^ :]+:[0-9]+: Info:    did you mean this\?
2962 [^ :]+:[0-9]+: Info:            urshl z0\.b, p0/m, z0\.b, z0\.b
2963 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2964 [^ :]+:[0-9]+: Info:            urshl z0\.h, p0/m, z0\.h, z0\.h
2965 [^ :]+:[0-9]+: Info:            urshl z0\.s, p0/m, z0\.s, z0\.s
2966 [^ :]+:[0-9]+: Info:            urshl z0\.d, p0/m, z0\.d, z0\.d
2967 [^ :]+:[0-9]+: Error: operand mismatch -- `urshl z0\.b,p0/z,z0\.b,z0\.b'
2968 [^ :]+:[0-9]+: Info:    did you mean this\?
2969 [^ :]+:[0-9]+: Info:            urshl z0\.b, p0/m, z0\.b, z0\.b
2970 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2971 [^ :]+:[0-9]+: Info:            urshl z0\.h, p0/m, z0\.h, z0\.h
2972 [^ :]+:[0-9]+: Info:            urshl z0\.s, p0/m, z0\.s, z0\.s
2973 [^ :]+:[0-9]+: Info:            urshl z0\.d, p0/m, z0\.d, z0\.d
2974 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `urshlr z32\.b,p0/m,z0\.b,z0\.b'
2975 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urshlr z0\.b,p0/m,z32\.b,z0\.b'
2976 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `urshlr z0\.b,p0/m,z0\.b,z32\.b'
2977 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urshlr z0\.b,p0/m,z1\.b,z0\.b'
2978 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urshlr z0\.b,p8/m,z0\.b,z0\.b'
2979 [^ :]+:[0-9]+: Error: operand mismatch -- `urshlr z0\.h,p0/m,z0\.b,z0\.b'
2980 [^ :]+:[0-9]+: Info:    did you mean this\?
2981 [^ :]+:[0-9]+: Info:            urshlr z0\.b, p0/m, z0\.b, z0\.b
2982 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2983 [^ :]+:[0-9]+: Info:            urshlr z0\.h, p0/m, z0\.h, z0\.h
2984 [^ :]+:[0-9]+: Info:            urshlr z0\.s, p0/m, z0\.s, z0\.s
2985 [^ :]+:[0-9]+: Info:            urshlr z0\.d, p0/m, z0\.d, z0\.d
2986 [^ :]+:[0-9]+: Error: operand mismatch -- `urshlr z0\.b,p0/z,z0\.b,z0\.b'
2987 [^ :]+:[0-9]+: Info:    did you mean this\?
2988 [^ :]+:[0-9]+: Info:            urshlr z0\.b, p0/m, z0\.b, z0\.b
2989 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2990 [^ :]+:[0-9]+: Info:            urshlr z0\.h, p0/m, z0\.h, z0\.h
2991 [^ :]+:[0-9]+: Info:            urshlr z0\.s, p0/m, z0\.s, z0\.s
2992 [^ :]+:[0-9]+: Info:            urshlr z0\.d, p0/m, z0\.d, z0\.d
2993 [^ :]+:[0-9]+: Error: operand mismatch -- `urshr z0\.h,p0/m,z0\.b,#1'
2994 [^ :]+:[0-9]+: Info:    did you mean this\?
2995 [^ :]+:[0-9]+: Info:            urshr z0\.b, p0/m, z0\.b, #1
2996 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
2997 [^ :]+:[0-9]+: Info:            urshr z0\.h, p0/m, z0\.h, #1
2998 [^ :]+:[0-9]+: Info:            urshr z0\.s, p0/m, z0\.s, #1
2999 [^ :]+:[0-9]+: Info:            urshr z0\.d, p0/m, z0\.d, #1
3000 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `urshr z32\.b,p0/m,z32\.b,#1'
3001 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urshr z0\.b,p0/m,z1\.b,#1'
3002 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urshr z0\.b,p8/m,z0\.b,#1'
3003 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `urshr z0\.b,p0/m,z0\.b,#0'
3004 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `urshr z0\.b,p0/m,z0\.b,#9'
3005 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 4 -- `urshr z0\.h,p0/m,z0\.h,#0'
3006 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 4 -- `urshr z0\.h,p0/m,z0\.h,#17'
3007 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `urshr z0\.s,p0/m,z0\.s,#0'
3008 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `urshr z0\.s,p0/m,z0\.s,#33'
3009 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `urshr z0\.d,p0/m,z0\.d,#0'
3010 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `urshr z0\.d,p0/m,z0\.d,#65'
3011 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ursqrte z32\.s,p0/m,z0\.s'
3012 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ursqrte z0\.s,p0/m,z32\.s'
3013 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ursqrte z0\.s,p8/m,z0\.s'
3014 [^ :]+:[0-9]+: Error: operand mismatch -- `ursqrte z0\.d,p0/m,z0\.s'
3015 [^ :]+:[0-9]+: Info:    did you mean this\?
3016 [^ :]+:[0-9]+: Info:            ursqrte z0\.s, p0/m, z0\.s
3017 [^ :]+:[0-9]+: Error: operand mismatch -- `ursra z0\.h,z0\.b,#1'
3018 [^ :]+:[0-9]+: Info:    did you mean this\?
3019 [^ :]+:[0-9]+: Info:            ursra z0\.b, z0\.b, #1
3020 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3021 [^ :]+:[0-9]+: Info:            ursra z0\.h, z0\.h, #1
3022 [^ :]+:[0-9]+: Info:            ursra z0\.s, z0\.s, #1
3023 [^ :]+:[0-9]+: Info:            ursra z0\.d, z0\.d, #1
3024 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `ursra z32\.b,z0\.b,#1'
3025 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ursra z0\.b,z32\.b,#1'
3026 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ursra z0\.b,z0\.b,#0'
3027 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ursra z0\.b,z0\.b,#9'
3028 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `ursra z0\.h,z0\.h,#0'
3029 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `ursra z0\.h,z0\.h,#17'
3030 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `ursra z0\.s,z0\.s,#0'
3031 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `ursra z0\.s,z0\.s,#33'
3032 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `ursra z0\.d,z0\.d,#0'
3033 [^ :]+:[0-9]+: Error: operand mismatch -- `ushllb z0\.b,z0\.b,#0'
3034 [^ :]+:[0-9]+: Info:    did you mean this\?
3035 [^ :]+:[0-9]+: Info:            ushllb z0\.h, z0\.b, #0
3036 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3037 [^ :]+:[0-9]+: Info:            ushllb z0\.s, z0\.h, #0
3038 [^ :]+:[0-9]+: Info:            ushllb z0\.d, z0\.s, #0
3039 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ushllb z32\.h,z0\.b,#0'
3040 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ushllb z0\.h,z32\.b,#0'
3041 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `ushllb z0\.h,z0\.b,#8'
3042 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `ushllb z0\.s,z0\.h,#16'
3043 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `ushllb z0\.d,z0\.s,#32'
3044 [^ :]+:[0-9]+: Error: operand mismatch -- `ushllt z0\.b,z0\.b,#0'
3045 [^ :]+:[0-9]+: Info:    did you mean this\?
3046 [^ :]+:[0-9]+: Info:            ushllt z0\.h, z0\.b, #0
3047 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3048 [^ :]+:[0-9]+: Info:            ushllt z0\.s, z0\.h, #0
3049 [^ :]+:[0-9]+: Info:            ushllt z0\.d, z0\.s, #0
3050 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ushllt z32\.h,z0\.b,#0'
3051 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ushllt z0\.h,z32\.b,#0'
3052 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `ushllt z0\.h,z0\.b,#8'
3053 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `ushllt z0\.s,z0\.h,#16'
3054 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `ushllt z0\.d,z0\.s,#32'
3055 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `usqadd z32\.b,p0/m,z0\.b,z0\.b'
3056 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usqadd z0\.b,p0/m,z32\.b,z0\.b'
3057 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `usqadd z0\.b,p0/m,z0\.b,z32\.b'
3058 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `usqadd z0\.b,p0/m,z1\.b,z0\.b'
3059 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `usqadd z0\.b,p8/m,z0\.b,z0\.b'
3060 [^ :]+:[0-9]+: Error: operand mismatch -- `usqadd z0\.h,p0/m,z0\.b,z0\.b'
3061 [^ :]+:[0-9]+: Info:    did you mean this\?
3062 [^ :]+:[0-9]+: Info:            usqadd z0\.b, p0/m, z0\.b, z0\.b
3063 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3064 [^ :]+:[0-9]+: Info:            usqadd z0\.h, p0/m, z0\.h, z0\.h
3065 [^ :]+:[0-9]+: Info:            usqadd z0\.s, p0/m, z0\.s, z0\.s
3066 [^ :]+:[0-9]+: Info:            usqadd z0\.d, p0/m, z0\.d, z0\.d
3067 [^ :]+:[0-9]+: Error: operand mismatch -- `usqadd z0\.b,p0/z,z0\.b,z0\.b'
3068 [^ :]+:[0-9]+: Info:    did you mean this\?
3069 [^ :]+:[0-9]+: Info:            usqadd z0\.b, p0/m, z0\.b, z0\.b
3070 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3071 [^ :]+:[0-9]+: Info:            usqadd z0\.h, p0/m, z0\.h, z0\.h
3072 [^ :]+:[0-9]+: Info:            usqadd z0\.s, p0/m, z0\.s, z0\.s
3073 [^ :]+:[0-9]+: Info:            usqadd z0\.d, p0/m, z0\.d, z0\.d
3074 [^ :]+:[0-9]+: Error: operand mismatch -- `usra z0\.h,z0\.b,#1'
3075 [^ :]+:[0-9]+: Info:    did you mean this\?
3076 [^ :]+:[0-9]+: Info:            usra z0\.b, z0\.b, #1
3077 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3078 [^ :]+:[0-9]+: Info:            usra z0\.h, z0\.h, #1
3079 [^ :]+:[0-9]+: Info:            usra z0\.s, z0\.s, #1
3080 [^ :]+:[0-9]+: Info:            usra z0\.d, z0\.d, #1
3081 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `usra z32\.b,z0\.b,#1'
3082 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usra z0\.b,z32\.b,#1'
3083 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `usra z0\.b,z0\.b,#0'
3084 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `usra z0\.b,z0\.b,#9'
3085 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `usra z0\.h,z0\.h,#0'
3086 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `usra z0\.h,z0\.h,#17'
3087 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `usra z0\.s,z0\.s,#0'
3088 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `usra z0\.s,z0\.s,#33'
3089 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `usra z0\.d,z0\.d,#0'
3090 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usublb z32\.h,z0\.b,z0\.b'
3091 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usublb z0\.h,z32\.b,z0\.b'
3092 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usublb z0\.h,z0\.b,z32\.b'
3093 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usublb z0\.s,z0\.h,z0\.x'
3094 [^ :]+:[0-9]+: Error: operand mismatch -- `usublb z0\.h,z0\.b,z0\.h'
3095 [^ :]+:[0-9]+: Info:    did you mean this\?
3096 [^ :]+:[0-9]+: Info:            usublb z0\.h, z0\.b, z0\.b
3097 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3098 [^ :]+:[0-9]+: Info:            usublb z0\.s, z0\.h, z0\.h
3099 [^ :]+:[0-9]+: Info:            usublb z0\.d, z0\.s, z0\.s
3100 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usublt z32\.h,z0\.b,z0\.b'
3101 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usublt z0\.h,z32\.b,z0\.b'
3102 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usublt z0\.h,z0\.b,z32\.b'
3103 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usublt z0\.s,z0\.h,z0\.x'
3104 [^ :]+:[0-9]+: Error: operand mismatch -- `usublt z0\.h,z0\.b,z0\.h'
3105 [^ :]+:[0-9]+: Info:    did you mean this\?
3106 [^ :]+:[0-9]+: Info:            usublt z0\.h, z0\.b, z0\.b
3107 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3108 [^ :]+:[0-9]+: Info:            usublt z0\.s, z0\.h, z0\.h
3109 [^ :]+:[0-9]+: Info:            usublt z0\.d, z0\.s, z0\.s
3110 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usubwb z32\.h,z0\.h,z0\.b'
3111 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usubwb z0\.h,z32\.h,z0\.b'
3112 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usubwb z0\.h,z0\.h,z32\.b'
3113 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usubwb z0\.s,z0\.s,z0\.x'
3114 [^ :]+:[0-9]+: Error: operand mismatch -- `usubwb z0\.h,z0\.h,z0\.h'
3115 [^ :]+:[0-9]+: Info:    did you mean this\?
3116 [^ :]+:[0-9]+: Info:            usubwb z0\.h, z0\.h, z0\.b
3117 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3118 [^ :]+:[0-9]+: Info:            usubwb z0\.s, z0\.s, z0\.h
3119 [^ :]+:[0-9]+: Info:            usubwb z0\.d, z0\.d, z0\.s
3120 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usubwt z32\.h,z0\.h,z0\.b'
3121 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usubwt z0\.h,z32\.h,z0\.b'
3122 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usubwt z0\.h,z0\.h,z32\.b'
3123 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usubwt z0\.s,z0\.s,z0\.x'
3124 [^ :]+:[0-9]+: Error: operand mismatch -- `usubwt z0\.h,z0\.h,z0\.h'
3125 [^ :]+:[0-9]+: Info:    did you mean this\?
3126 [^ :]+:[0-9]+: Info:            usubwt z0\.h, z0\.h, z0\.b
3127 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3128 [^ :]+:[0-9]+: Info:            usubwt z0\.s, z0\.s, z0\.h
3129 [^ :]+:[0-9]+: Info:            usubwt z0\.d, z0\.d, z0\.s
3130 [^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilege p16\.b,x0,x0'
3131 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,x32,x0'
3132 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,x0,x32'
3133 [^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,x0,x0'
3134 [^ :]+:[0-9]+: Info:    did you mean this\?
3135 [^ :]+:[0-9]+: Info:            whilege p0\.b, x0, x0
3136 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3137 [^ :]+:[0-9]+: Info:            whilege p0\.h, x0, x0
3138 [^ :]+:[0-9]+: Info:            whilege p0\.s, x0, x0
3139 [^ :]+:[0-9]+: Info:            whilege p0\.d, x0, x0
3140 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,x31,x0'
3141 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,x0,x31'
3142 [^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0\.b,x0,w0'
3143 [^ :]+:[0-9]+: Info:    did you mean this\?
3144 [^ :]+:[0-9]+: Info:            whilege p0\.b, x0, x0
3145 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3146 [^ :]+:[0-9]+: Info:            whilege p0\.h, x0, x0
3147 [^ :]+:[0-9]+: Info:            whilege p0\.s, x0, x0
3148 [^ :]+:[0-9]+: Info:            whilege p0\.d, x0, x0
3149 [^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0\.b,w0,x0'
3150 [^ :]+:[0-9]+: Info:    did you mean this\?
3151 [^ :]+:[0-9]+: Info:            whilege p0\.b, x0, x0
3152 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3153 [^ :]+:[0-9]+: Info:            whilege p0\.h, x0, x0
3154 [^ :]+:[0-9]+: Info:            whilege p0\.s, x0, x0
3155 [^ :]+:[0-9]+: Info:            whilege p0\.d, x0, x0
3156 [^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilege p16\.b,w0,w0'
3157 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,w32,w0'
3158 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,w0,w32'
3159 [^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,w0,w0'
3160 [^ :]+:[0-9]+: Info:    did you mean this\?
3161 [^ :]+:[0-9]+: Info:            whilege p0\.b, x0, x0
3162 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3163 [^ :]+:[0-9]+: Info:            whilege p0\.h, x0, x0
3164 [^ :]+:[0-9]+: Info:            whilege p0\.s, x0, x0
3165 [^ :]+:[0-9]+: Info:            whilege p0\.d, x0, x0
3166 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,w31,w0'
3167 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,w0,w31'
3168 [^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilegt p16\.b,x0,x0'
3169 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,x32,x0'
3170 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,x0,x32'
3171 [^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,x0,x0'
3172 [^ :]+:[0-9]+: Info:    did you mean this\?
3173 [^ :]+:[0-9]+: Info:            whilegt p0\.b, x0, x0
3174 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3175 [^ :]+:[0-9]+: Info:            whilegt p0\.h, x0, x0
3176 [^ :]+:[0-9]+: Info:            whilegt p0\.s, x0, x0
3177 [^ :]+:[0-9]+: Info:            whilegt p0\.d, x0, x0
3178 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,x31,x0'
3179 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,x0,x31'
3180 [^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0\.b,x0,w0'
3181 [^ :]+:[0-9]+: Info:    did you mean this\?
3182 [^ :]+:[0-9]+: Info:            whilegt p0\.b, x0, x0
3183 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3184 [^ :]+:[0-9]+: Info:            whilegt p0\.h, x0, x0
3185 [^ :]+:[0-9]+: Info:            whilegt p0\.s, x0, x0
3186 [^ :]+:[0-9]+: Info:            whilegt p0\.d, x0, x0
3187 [^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0\.b,w0,x0'
3188 [^ :]+:[0-9]+: Info:    did you mean this\?
3189 [^ :]+:[0-9]+: Info:            whilegt p0\.b, x0, x0
3190 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3191 [^ :]+:[0-9]+: Info:            whilegt p0\.h, x0, x0
3192 [^ :]+:[0-9]+: Info:            whilegt p0\.s, x0, x0
3193 [^ :]+:[0-9]+: Info:            whilegt p0\.d, x0, x0
3194 [^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilegt p16\.b,w0,w0'
3195 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,w32,w0'
3196 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,w0,w32'
3197 [^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,w0,w0'
3198 [^ :]+:[0-9]+: Info:    did you mean this\?
3199 [^ :]+:[0-9]+: Info:            whilegt p0\.b, x0, x0
3200 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3201 [^ :]+:[0-9]+: Info:            whilegt p0\.h, x0, x0
3202 [^ :]+:[0-9]+: Info:            whilegt p0\.s, x0, x0
3203 [^ :]+:[0-9]+: Info:            whilegt p0\.d, x0, x0
3204 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,w31,w0'
3205 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,w0,w31'
3206 [^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehi p16\.b,x0,x0'
3207 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,x32,x0'
3208 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,x0,x32'
3209 [^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,x0,x0'
3210 [^ :]+:[0-9]+: Info:    did you mean this\?
3211 [^ :]+:[0-9]+: Info:            whilehi p0\.b, x0, x0
3212 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3213 [^ :]+:[0-9]+: Info:            whilehi p0\.h, x0, x0
3214 [^ :]+:[0-9]+: Info:            whilehi p0\.s, x0, x0
3215 [^ :]+:[0-9]+: Info:            whilehi p0\.d, x0, x0
3216 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,x31,x0'
3217 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,x0,x31'
3218 [^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0\.b,x0,w0'
3219 [^ :]+:[0-9]+: Info:    did you mean this\?
3220 [^ :]+:[0-9]+: Info:            whilehi p0\.b, x0, x0
3221 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3222 [^ :]+:[0-9]+: Info:            whilehi p0\.h, x0, x0
3223 [^ :]+:[0-9]+: Info:            whilehi p0\.s, x0, x0
3224 [^ :]+:[0-9]+: Info:            whilehi p0\.d, x0, x0
3225 [^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0\.b,w0,x0'
3226 [^ :]+:[0-9]+: Info:    did you mean this\?
3227 [^ :]+:[0-9]+: Info:            whilehi p0\.b, x0, x0
3228 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3229 [^ :]+:[0-9]+: Info:            whilehi p0\.h, x0, x0
3230 [^ :]+:[0-9]+: Info:            whilehi p0\.s, x0, x0
3231 [^ :]+:[0-9]+: Info:            whilehi p0\.d, x0, x0
3232 [^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehi p16\.b,w0,w0'
3233 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,w32,w0'
3234 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,w0,w32'
3235 [^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,w0,w0'
3236 [^ :]+:[0-9]+: Info:    did you mean this\?
3237 [^ :]+:[0-9]+: Info:            whilehi p0\.b, x0, x0
3238 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3239 [^ :]+:[0-9]+: Info:            whilehi p0\.h, x0, x0
3240 [^ :]+:[0-9]+: Info:            whilehi p0\.s, x0, x0
3241 [^ :]+:[0-9]+: Info:            whilehi p0\.d, x0, x0
3242 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,w31,w0'
3243 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,w0,w31'
3244 [^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehs p16\.b,x0,x0'
3245 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,x32,x0'
3246 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,x0,x32'
3247 [^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,x0,x0'
3248 [^ :]+:[0-9]+: Info:    did you mean this\?
3249 [^ :]+:[0-9]+: Info:            whilehs p0\.b, x0, x0
3250 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3251 [^ :]+:[0-9]+: Info:            whilehs p0\.h, x0, x0
3252 [^ :]+:[0-9]+: Info:            whilehs p0\.s, x0, x0
3253 [^ :]+:[0-9]+: Info:            whilehs p0\.d, x0, x0
3254 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,x31,x0'
3255 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,x0,x31'
3256 [^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0\.b,x0,w0'
3257 [^ :]+:[0-9]+: Info:    did you mean this\?
3258 [^ :]+:[0-9]+: Info:            whilehs p0\.b, x0, x0
3259 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3260 [^ :]+:[0-9]+: Info:            whilehs p0\.h, x0, x0
3261 [^ :]+:[0-9]+: Info:            whilehs p0\.s, x0, x0
3262 [^ :]+:[0-9]+: Info:            whilehs p0\.d, x0, x0
3263 [^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0\.b,w0,x0'
3264 [^ :]+:[0-9]+: Info:    did you mean this\?
3265 [^ :]+:[0-9]+: Info:            whilehs p0\.b, x0, x0
3266 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3267 [^ :]+:[0-9]+: Info:            whilehs p0\.h, x0, x0
3268 [^ :]+:[0-9]+: Info:            whilehs p0\.s, x0, x0
3269 [^ :]+:[0-9]+: Info:            whilehs p0\.d, x0, x0
3270 [^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehs p16\.b,w0,w0'
3271 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,w32,w0'
3272 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,w0,w32'
3273 [^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,w0,w0'
3274 [^ :]+:[0-9]+: Info:    did you mean this\?
3275 [^ :]+:[0-9]+: Info:            whilehs p0\.b, x0, x0
3276 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3277 [^ :]+:[0-9]+: Info:            whilehs p0\.h, x0, x0
3278 [^ :]+:[0-9]+: Info:            whilehs p0\.s, x0, x0
3279 [^ :]+:[0-9]+: Info:            whilehs p0\.d, x0, x0
3280 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,w31,w0'
3281 [^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,w0,w31'
3282 [^ :]+:[0-9]+: Error: operand mismatch -- `whilerw p0\.b,w0,x0'
3283 [^ :]+:[0-9]+: Info:    did you mean this\?
3284 [^ :]+:[0-9]+: Info:            whilerw p0\.b, x0, x0
3285 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3286 [^ :]+:[0-9]+: Info:            whilerw p0\.h, x0, x0
3287 [^ :]+:[0-9]+: Info:            whilerw p0\.s, x0, x0
3288 [^ :]+:[0-9]+: Info:            whilerw p0\.d, x0, x0
3289 [^ :]+:[0-9]+: Error: operand mismatch -- `whilerw p0/m,x0,x0'
3290 [^ :]+:[0-9]+: Info:    did you mean this\?
3291 [^ :]+:[0-9]+: Info:            whilerw p0\.b, x0, x0
3292 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3293 [^ :]+:[0-9]+: Info:            whilerw p0\.h, x0, x0
3294 [^ :]+:[0-9]+: Info:            whilerw p0\.s, x0, x0
3295 [^ :]+:[0-9]+: Info:            whilerw p0\.d, x0, x0
3296 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilerw p0\.b,x32,x0'
3297 [^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilerw p16\.b,x0,x0'
3298 [^ :]+:[0-9]+: Error: operand mismatch -- `whilewr p0\.b,w0,x0'
3299 [^ :]+:[0-9]+: Info:    did you mean this\?
3300 [^ :]+:[0-9]+: Info:            whilewr p0\.b, x0, x0
3301 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3302 [^ :]+:[0-9]+: Info:            whilewr p0\.h, x0, x0
3303 [^ :]+:[0-9]+: Info:            whilewr p0\.s, x0, x0
3304 [^ :]+:[0-9]+: Info:            whilewr p0\.d, x0, x0
3305 [^ :]+:[0-9]+: Error: operand mismatch -- `whilewr p0/m,x0,x0'
3306 [^ :]+:[0-9]+: Info:    did you mean this\?
3307 [^ :]+:[0-9]+: Info:            whilewr p0\.b, x0, x0
3308 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3309 [^ :]+:[0-9]+: Info:            whilewr p0\.h, x0, x0
3310 [^ :]+:[0-9]+: Info:            whilewr p0\.s, x0, x0
3311 [^ :]+:[0-9]+: Info:            whilewr p0\.d, x0, x0
3312 [^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilewr p0\.b,x32,x0'
3313 [^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilewr p16\.b,x0,x0'
3314 [^ :]+:[0-9]+: Error: operand mismatch -- `xar z0\.h,z0\.b,z0\.b,#1'
3315 [^ :]+:[0-9]+: Info:    did you mean this\?
3316 [^ :]+:[0-9]+: Info:            xar z0\.b, z0\.b, z0\.b, #1
3317 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
3318 [^ :]+:[0-9]+: Info:            xar z0\.h, z0\.h, z0\.h, #1
3319 [^ :]+:[0-9]+: Info:            xar z0\.s, z0\.s, z0\.s, #1
3320 [^ :]+:[0-9]+: Info:            xar z0\.d, z0\.d, z0\.d, #1
3321 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `xar z0\.b,z1\.b,z0\.b,#1'
3322 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `xar z32\.b,z32\.b,z0\.b,#1'
3323 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `xar z0\.b,z0\.b,z32\.b,#1'
3324 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `xar z0\.b,z0\.b,z0\.b,#0'
3325 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `xar z0\.b,z0\.b,z0\.b,#9'
3326 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 4 -- `xar z0\.h,z0\.h,z0\.h,#0'
3327 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 4 -- `xar z0\.h,z0\.h,z0\.h,#17'
3328 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `xar z0\.s,z0\.s,z0\.s,#0'
3329 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `xar z0\.s,z0\.s,z0\.s,#33'
3330 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `xar z0\.d,z0\.d,z0\.d,#0'