1 // movi.s Test file for AArch64 AdvSIMD modified immediate instruction MOVI
5 .macro all_64bit_mask_movi dst
6 .irp b7, 0, 0xff00000000000000
7 .irp b6, 0, 0xff000000000000
8 .irp b5, 0, 0xff0000000000
9 .irp b4, 0, 0xff00000000
10 .irp b3, 0, 0xff000000
14 movi \dst, \b7 + \b6 + \b5 + \b4 + \b3 + \b2 + \b1 + \b0
26 // MOVI <Vd>.2D, #<imm>
27 all_64bit_mask_movi d31
28 all_64bit_mask_movi v15.2d
31 .macro all_8bit_imm_movi dst, from=0, to=255
34 all_8bit_imm_movi \dst, "(\from+1)", \to
39 // MOVI <Vd>.<T>, #<imm8>
41 all_8bit_imm_movi v15.\T, 0, 63
42 all_8bit_imm_movi v15.\T, 64, 127
43 all_8bit_imm_movi v15.\T, 128, 191
44 all_8bit_imm_movi v15.\T, 192, 255
48 .macro all_8bit_imm_movi_sft dst, from=0, to=255, shift_op, amount
49 movi \dst, \from, \shift_op \amount
51 all_8bit_imm_movi_sft \dst, "(\from+1)", \to, \shift_op, \amount
55 // Shift ones, per word
56 // MOVI <Vd>.<T>, #<imm8>, MSL #<amount>
59 // Have to break into four chunks to avoid "Fatal error: macros nested
61 all_8bit_imm_movi_sft v7.\T, 0, 63, MSL, \amount
62 all_8bit_imm_movi_sft v7.\T, 64, 127, MSL, \amount
63 all_8bit_imm_movi_sft v7.\T, 128, 191, MSL, \amount
64 all_8bit_imm_movi_sft v7.\T, 192, 255, MSL, \amount
69 // Shift zeros, per halfword
70 // MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}
73 all_8bit_imm_movi_sft v7.\T, 0, 63, LSL, \amount
74 all_8bit_imm_movi_sft v7.\T, 64, 127, LSL, \amount
75 all_8bit_imm_movi_sft v7.\T, 128, 191, LSL, \amount
76 all_8bit_imm_movi_sft v7.\T, 192, 255, LSL, \amount
77 all_8bit_imm_movi v15.\T, 0, 63
78 all_8bit_imm_movi v15.\T, 64, 127
79 all_8bit_imm_movi v15.\T, 128, 191
80 all_8bit_imm_movi v15.\T, 192, 255
85 // Shift zeros, per word
86 // MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}
88 .irp amount, 0, 8, 16, 24
89 all_8bit_imm_movi_sft v7.\T, 0, 63, LSL, \amount
90 all_8bit_imm_movi_sft v7.\T, 64, 127, LSL, \amount
91 all_8bit_imm_movi_sft v7.\T, 128, 191, LSL, \amount
92 all_8bit_imm_movi_sft v7.\T, 192, 255, LSL, \amount
93 all_8bit_imm_movi v15.\T, 0, 63
94 all_8bit_imm_movi v15.\T, 64, 127
95 all_8bit_imm_movi v15.\T, 128, 191
96 all_8bit_imm_movi v15.\T, 192, 255
100 // Shift zeros, per byte
101 // MOVI <Vd>.<T>, #<imm8>, LSL #0
102 // This used to be a programmer-friendly feature (allowing LSL #0),
103 // but it is now part of the architecture specification.
105 all_8bit_imm_movi_sft v7.\T, 0, 63, LSL, 0
106 all_8bit_imm_movi_sft v7.\T, 64, 127, LSL, 0
107 all_8bit_imm_movi_sft v7.\T, 128, 191, LSL, 0
108 all_8bit_imm_movi_sft v7.\T, 192, 255, LSL, 0
111 movi v0.2d, 18446744073709551615
114 movi d31, 18446744073709551615
115 .set bignum, 0xffffffffffffffff
117 // Allow -128 to 255 in #<imm8>