2 #objdump: -dr --prefix-addresses --show-raw-insn
4 .*: +file format .*arm.*
6 Disassembly of section .text:
7 0[0-9a-f]+ <[^>]+> fe000a00 vseleq.f32 s0, s0, s0
8 0[0-9a-f]+ <[^>]+> fe500aa0 vselvs.f32 s1, s1, s1
9 0[0-9a-f]+ <[^>]+> fe2ffa0f vselge.f32 s30, s30, s30
10 0[0-9a-f]+ <[^>]+> fe7ffaaf vselgt.f32 s31, s31, s31
11 0[0-9a-f]+ <[^>]+> fe000b00 vseleq.f64 d0, d0, d0
12 0[0-9a-f]+ <[^>]+> fe500ba0 vselvs.f64 d16, d16, d16
13 0[0-9a-f]+ <[^>]+> fe2ffb0f vselge.f64 d15, d15, d15
14 0[0-9a-f]+ <[^>]+> fe7ffbaf vselgt.f64 d31, d31, d31
15 0[0-9a-f]+ <[^>]+> fe800a00 vmaxnm.f32 s0, s0, s0
16 0[0-9a-f]+ <[^>]+> fec00aa0 vmaxnm.f32 s1, s1, s1
17 0[0-9a-f]+ <[^>]+> fe8ffa0f vmaxnm.f32 s30, s30, s30
18 0[0-9a-f]+ <[^>]+> fecffaaf vmaxnm.f32 s31, s31, s31
19 0[0-9a-f]+ <[^>]+> fe800b00 vmaxnm.f64 d0, d0, d0
20 0[0-9a-f]+ <[^>]+> fec00ba0 vmaxnm.f64 d16, d16, d16
21 0[0-9a-f]+ <[^>]+> fe8ffb0f vmaxnm.f64 d15, d15, d15
22 0[0-9a-f]+ <[^>]+> fecffbaf vmaxnm.f64 d31, d31, d31
23 0[0-9a-f]+ <[^>]+> fe800a40 vminnm.f32 s0, s0, s0
24 0[0-9a-f]+ <[^>]+> fec00ae0 vminnm.f32 s1, s1, s1
25 0[0-9a-f]+ <[^>]+> fe8ffa4f vminnm.f32 s30, s30, s30
26 0[0-9a-f]+ <[^>]+> fecffaef vminnm.f32 s31, s31, s31
27 0[0-9a-f]+ <[^>]+> fe800b40 vminnm.f64 d0, d0, d0
28 0[0-9a-f]+ <[^>]+> fec00be0 vminnm.f64 d16, d16, d16
29 0[0-9a-f]+ <[^>]+> fe8ffb4f vminnm.f64 d15, d15, d15
30 0[0-9a-f]+ <[^>]+> fecffbef vminnm.f64 d31, d31, d31
31 0[0-9a-f]+ <[^>]+> febc0ac0 vcvta.s32.f32 s0, s0
32 0[0-9a-f]+ <[^>]+> fefd0ae0 vcvtn.s32.f32 s1, s1
33 0[0-9a-f]+ <[^>]+> febefa4f vcvtp.u32.f32 s30, s30
34 0[0-9a-f]+ <[^>]+> fefffa6f vcvtm.u32.f32 s31, s31
35 0[0-9a-f]+ <[^>]+> febc0b40 vcvta.u32.f64 s0, d0
36 0[0-9a-f]+ <[^>]+> fefd0b60 vcvtn.u32.f64 s1, d16
37 0[0-9a-f]+ <[^>]+> febefb4f vcvtp.u32.f64 s30, d15
38 0[0-9a-f]+ <[^>]+> fefffb6f vcvtm.u32.f64 s31, d31
39 0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
40 0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1
41 0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30
42 0[0-9a-f]+ <[^>]+> fe7f faaf vselgt.f32 s31, s31, s31
43 0[0-9a-f]+ <[^>]+> fe00 0b00 vseleq.f64 d0, d0, d0
44 0[0-9a-f]+ <[^>]+> fe50 0ba0 vselvs.f64 d16, d16, d16
45 0[0-9a-f]+ <[^>]+> fe2f fb0f vselge.f64 d15, d15, d15
46 0[0-9a-f]+ <[^>]+> fe7f fbaf vselgt.f64 d31, d31, d31
47 0[0-9a-f]+ <[^>]+> fe80 0a00 vmaxnm.f32 s0, s0, s0
48 0[0-9a-f]+ <[^>]+> fec0 0aa0 vmaxnm.f32 s1, s1, s1
49 0[0-9a-f]+ <[^>]+> fe8f fa0f vmaxnm.f32 s30, s30, s30
50 0[0-9a-f]+ <[^>]+> fecf faaf vmaxnm.f32 s31, s31, s31
51 0[0-9a-f]+ <[^>]+> fe80 0b00 vmaxnm.f64 d0, d0, d0
52 0[0-9a-f]+ <[^>]+> fec0 0ba0 vmaxnm.f64 d16, d16, d16
53 0[0-9a-f]+ <[^>]+> fe8f fb0f vmaxnm.f64 d15, d15, d15
54 0[0-9a-f]+ <[^>]+> fecf fbaf vmaxnm.f64 d31, d31, d31
55 0[0-9a-f]+ <[^>]+> fe80 0a40 vminnm.f32 s0, s0, s0
56 0[0-9a-f]+ <[^>]+> fec0 0ae0 vminnm.f32 s1, s1, s1
57 0[0-9a-f]+ <[^>]+> fe8f fa4f vminnm.f32 s30, s30, s30
58 0[0-9a-f]+ <[^>]+> fecf faef vminnm.f32 s31, s31, s31
59 0[0-9a-f]+ <[^>]+> fe80 0b40 vminnm.f64 d0, d0, d0
60 0[0-9a-f]+ <[^>]+> fec0 0be0 vminnm.f64 d16, d16, d16
61 0[0-9a-f]+ <[^>]+> fe8f fb4f vminnm.f64 d15, d15, d15
62 0[0-9a-f]+ <[^>]+> fecf fbef vminnm.f64 d31, d31, d31
63 0[0-9a-f]+ <[^>]+> febc 0ac0 vcvta.s32.f32 s0, s0
64 0[0-9a-f]+ <[^>]+> fefd 0ae0 vcvtn.s32.f32 s1, s1
65 0[0-9a-f]+ <[^>]+> febe fa4f vcvtp.u32.f32 s30, s30
66 0[0-9a-f]+ <[^>]+> feff fa6f vcvtm.u32.f32 s31, s31
67 0[0-9a-f]+ <[^>]+> febc 0b40 vcvta.u32.f64 s0, d0
68 0[0-9a-f]+ <[^>]+> fefd 0b60 vcvtn.u32.f64 s1, d16
69 0[0-9a-f]+ <[^>]+> febe fb4f vcvtp.u32.f64 s30, d15
70 0[0-9a-f]+ <[^>]+> feff fb6f vcvtm.u32.f64 s31, d31
projects / deliverable / binutils-gdb.git / blob