2 #objdump: -dr --prefix-addresses --show-raw-insn
3 #skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
5 .*: +file format .*arm.*
7 Disassembly of section .text:
8 0[0-9a-f]+ <[^>]+> fe000a00 vseleq.f32 s0, s0, s0
9 0[0-9a-f]+ <[^>]+> fe500aa0 vselvs.f32 s1, s1, s1
10 0[0-9a-f]+ <[^>]+> fe2ffa0f vselge.f32 s30, s30, s30
11 0[0-9a-f]+ <[^>]+> fe7ffaaf vselgt.f32 s31, s31, s31
12 0[0-9a-f]+ <[^>]+> fe000b00 vseleq.f64 d0, d0, d0
13 0[0-9a-f]+ <[^>]+> fe500ba0 vselvs.f64 d16, d16, d16
14 0[0-9a-f]+ <[^>]+> fe2ffb0f vselge.f64 d15, d15, d15
15 0[0-9a-f]+ <[^>]+> fe7ffbaf vselgt.f64 d31, d31, d31
16 0[0-9a-f]+ <[^>]+> fe800a00 vmaxnm.f32 s0, s0, s0
17 0[0-9a-f]+ <[^>]+> fec00aa0 vmaxnm.f32 s1, s1, s1
18 0[0-9a-f]+ <[^>]+> fe8ffa0f vmaxnm.f32 s30, s30, s30
19 0[0-9a-f]+ <[^>]+> fecffaaf vmaxnm.f32 s31, s31, s31
20 0[0-9a-f]+ <[^>]+> fe800b00 vmaxnm.f64 d0, d0, d0
21 0[0-9a-f]+ <[^>]+> fec00ba0 vmaxnm.f64 d16, d16, d16
22 0[0-9a-f]+ <[^>]+> fe8ffb0f vmaxnm.f64 d15, d15, d15
23 0[0-9a-f]+ <[^>]+> fecffbaf vmaxnm.f64 d31, d31, d31
24 0[0-9a-f]+ <[^>]+> fe800a40 vminnm.f32 s0, s0, s0
25 0[0-9a-f]+ <[^>]+> fec00ae0 vminnm.f32 s1, s1, s1
26 0[0-9a-f]+ <[^>]+> fe8ffa4f vminnm.f32 s30, s30, s30
27 0[0-9a-f]+ <[^>]+> fecffaef vminnm.f32 s31, s31, s31
28 0[0-9a-f]+ <[^>]+> fe800b40 vminnm.f64 d0, d0, d0
29 0[0-9a-f]+ <[^>]+> fec00be0 vminnm.f64 d16, d16, d16
30 0[0-9a-f]+ <[^>]+> fe8ffb4f vminnm.f64 d15, d15, d15
31 0[0-9a-f]+ <[^>]+> fecffbef vminnm.f64 d31, d31, d31
32 0[0-9a-f]+ <[^>]+> febc0ac0 vcvta.s32.f32 s0, s0
33 0[0-9a-f]+ <[^>]+> fefd0ae0 vcvtn.s32.f32 s1, s1
34 0[0-9a-f]+ <[^>]+> febefa4f vcvtp.u32.f32 s30, s30
35 0[0-9a-f]+ <[^>]+> fefffa6f vcvtm.u32.f32 s31, s31
36 0[0-9a-f]+ <[^>]+> febc0bc0 vcvta.s32.f64 s0, d0
37 0[0-9a-f]+ <[^>]+> fefd0be0 vcvtn.s32.f64 s1, d16
38 0[0-9a-f]+ <[^>]+> febefb4f vcvtp.u32.f64 s30, d15
39 0[0-9a-f]+ <[^>]+> fefffb6f vcvtm.u32.f64 s31, d31
40 0[0-9a-f]+ <[^>]+> eeb60ac0 vrintz.f32 s0, s0
41 0[0-9a-f]+ <[^>]+> eef70a60 vrintx.f32 s1, s1
42 0[0-9a-f]+ <[^>]+> 0eb6fa4f vrintreq.f32 s30, s30
43 0[0-9a-f]+ <[^>]+> feb80a40 vrinta.f32 s0, s0
44 0[0-9a-f]+ <[^>]+> fef90a60 vrintn.f32 s1, s1
45 0[0-9a-f]+ <[^>]+> febafa4f vrintp.f32 s30, s30
46 0[0-9a-f]+ <[^>]+> fefbfa6f vrintm.f32 s31, s31
47 0[0-9a-f]+ <[^>]+> eeb60bc0 vrintz.f64 d0, d0
48 0[0-9a-f]+ <[^>]+> eeb71b41 vrintx.f64 d1, d1
49 0[0-9a-f]+ <[^>]+> 0ef6eb6e vrintreq.f64 d30, d30
50 0[0-9a-f]+ <[^>]+> feb80b40 vrinta.f64 d0, d0
51 0[0-9a-f]+ <[^>]+> feb91b41 vrintn.f64 d1, d1
52 0[0-9a-f]+ <[^>]+> fefaeb6e vrintp.f64 d30, d30
53 0[0-9a-f]+ <[^>]+> fefbfb6f vrintm.f64 d31, d31
54 0[0-9a-f]+ <[^>]+> eeb30bc0 vcvtt.f16.f64 s0, d0
55 0[0-9a-f]+ <[^>]+> eef30b60 vcvtb.f16.f64 s1, d16
56 0[0-9a-f]+ <[^>]+> eeb3fbcf vcvtt.f16.f64 s30, d15
57 0[0-9a-f]+ <[^>]+> eef3fb6f vcvtb.f16.f64 s31, d31
58 0[0-9a-f]+ <[^>]+> eeb20bc0 vcvtt.f64.f16 d0, s0
59 0[0-9a-f]+ <[^>]+> eef20b60 vcvtb.f64.f16 d16, s1
60 0[0-9a-f]+ <[^>]+> eeb2fbcf vcvtt.f64.f16 d15, s30
61 0[0-9a-f]+ <[^>]+> eef2fb6f vcvtb.f64.f16 d31, s31
62 0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
63 0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1
64 0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30
65 0[0-9a-f]+ <[^>]+> fe7f faaf vselgt.f32 s31, s31, s31
66 0[0-9a-f]+ <[^>]+> fe00 0b00 vseleq.f64 d0, d0, d0
67 0[0-9a-f]+ <[^>]+> fe50 0ba0 vselvs.f64 d16, d16, d16
68 0[0-9a-f]+ <[^>]+> fe2f fb0f vselge.f64 d15, d15, d15
69 0[0-9a-f]+ <[^>]+> fe7f fbaf vselgt.f64 d31, d31, d31
70 0[0-9a-f]+ <[^>]+> fe80 0a00 vmaxnm.f32 s0, s0, s0
71 0[0-9a-f]+ <[^>]+> fec0 0aa0 vmaxnm.f32 s1, s1, s1
72 0[0-9a-f]+ <[^>]+> fe8f fa0f vmaxnm.f32 s30, s30, s30
73 0[0-9a-f]+ <[^>]+> fecf faaf vmaxnm.f32 s31, s31, s31
74 0[0-9a-f]+ <[^>]+> fe80 0b00 vmaxnm.f64 d0, d0, d0
75 0[0-9a-f]+ <[^>]+> fec0 0ba0 vmaxnm.f64 d16, d16, d16
76 0[0-9a-f]+ <[^>]+> fe8f fb0f vmaxnm.f64 d15, d15, d15
77 0[0-9a-f]+ <[^>]+> fecf fbaf vmaxnm.f64 d31, d31, d31
78 0[0-9a-f]+ <[^>]+> fe80 0a40 vminnm.f32 s0, s0, s0
79 0[0-9a-f]+ <[^>]+> fec0 0ae0 vminnm.f32 s1, s1, s1
80 0[0-9a-f]+ <[^>]+> fe8f fa4f vminnm.f32 s30, s30, s30
81 0[0-9a-f]+ <[^>]+> fecf faef vminnm.f32 s31, s31, s31
82 0[0-9a-f]+ <[^>]+> fe80 0b40 vminnm.f64 d0, d0, d0
83 0[0-9a-f]+ <[^>]+> fec0 0be0 vminnm.f64 d16, d16, d16
84 0[0-9a-f]+ <[^>]+> fe8f fb4f vminnm.f64 d15, d15, d15
85 0[0-9a-f]+ <[^>]+> fecf fbef vminnm.f64 d31, d31, d31
86 0[0-9a-f]+ <[^>]+> febc 0ac0 vcvta.s32.f32 s0, s0
87 0[0-9a-f]+ <[^>]+> fefd 0ae0 vcvtn.s32.f32 s1, s1
88 0[0-9a-f]+ <[^>]+> febe fa4f vcvtp.u32.f32 s30, s30
89 0[0-9a-f]+ <[^>]+> feff fa6f vcvtm.u32.f32 s31, s31
90 0[0-9a-f]+ <[^>]+> febc 0bc0 vcvta.s32.f64 s0, d0
91 0[0-9a-f]+ <[^>]+> fefd 0be0 vcvtn.s32.f64 s1, d16
92 0[0-9a-f]+ <[^>]+> febe fb4f vcvtp.u32.f64 s30, d15
93 0[0-9a-f]+ <[^>]+> feff fb6f vcvtm.u32.f64 s31, d31
94 0[0-9a-f]+ <[^>]+> eeb6 0ac0 vrintz.f32 s0, s0
95 0[0-9a-f]+ <[^>]+> eef7 0a60 vrintx.f32 s1, s1
96 0[0-9a-f]+ <[^>]+> eeb6 fa4f vrintr.f32 s30, s30
97 0[0-9a-f]+ <[^>]+> feb8 0a40 vrinta.f32 s0, s0
98 0[0-9a-f]+ <[^>]+> fef9 0a60 vrintn.f32 s1, s1
99 0[0-9a-f]+ <[^>]+> feba fa4f vrintp.f32 s30, s30
100 0[0-9a-f]+ <[^>]+> fefb fa6f vrintm.f32 s31, s31
101 0[0-9a-f]+ <[^>]+> eeb6 0bc0 vrintz.f64 d0, d0
102 0[0-9a-f]+ <[^>]+> eeb7 1b41 vrintx.f64 d1, d1
103 0[0-9a-f]+ <[^>]+> eef6 eb6e vrintr.f64 d30, d30
104 0[0-9a-f]+ <[^>]+> feb8 0b40 vrinta.f64 d0, d0
105 0[0-9a-f]+ <[^>]+> feb9 1b41 vrintn.f64 d1, d1
106 0[0-9a-f]+ <[^>]+> fefa eb6e vrintp.f64 d30, d30
107 0[0-9a-f]+ <[^>]+> fefb fb6f vrintm.f64 d31, d31
108 0[0-9a-f]+ <[^>]+> eeb3 0bc0 vcvtt.f16.f64 s0, d0
109 0[0-9a-f]+ <[^>]+> eef3 0b60 vcvtb.f16.f64 s1, d16
110 0[0-9a-f]+ <[^>]+> eeb3 fbcf vcvtt.f16.f64 s30, d15
111 0[0-9a-f]+ <[^>]+> eef3 fb6f vcvtb.f16.f64 s31, d31
112 0[0-9a-f]+ <[^>]+> eeb2 0bc0 vcvtt.f64.f16 d0, s0
113 0[0-9a-f]+ <[^>]+> eef2 0b60 vcvtb.f64.f16 d16, s1
114 0[0-9a-f]+ <[^>]+> eeb2 fbcf vcvtt.f64.f16 d15, s30
115 0[0-9a-f]+ <[^>]+> eef2 fb6f vcvtb.f64.f16 d31, s31
projects / deliverable / binutils-gdb.git / blob