[ARM] Assembler and disassembler support Dot Product Extension
[deliverable/binutils-gdb.git] / gas / testsuite / gas / arm / armv8-r+simd.d
1 #name: Valid v8-r+simdv3
2 #source: armv8-ar+simd.s
3 #as: -march=armv8-r
4 #objdump: -dr --prefix-addresses --show-raw-insn
5 #skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
6
7 .*: +file format .*arm.*
8
9 Disassembly of section .text:
10 0[0-9a-f]+ <[^>]+> f3000f10 vmaxnm.f32 d0, d0, d0
11 0[0-9a-f]+ <[^>]+> f3400fb0 vmaxnm.f32 d16, d16, d16
12 0[0-9a-f]+ <[^>]+> f30fff1f vmaxnm.f32 d15, d15, d15
13 0[0-9a-f]+ <[^>]+> f34fffbf vmaxnm.f32 d31, d31, d31
14 0[0-9a-f]+ <[^>]+> f3000f50 vmaxnm.f32 q0, q0, q0
15 0[0-9a-f]+ <[^>]+> f3400ff0 vmaxnm.f32 q8, q8, q8
16 0[0-9a-f]+ <[^>]+> f30eef5e vmaxnm.f32 q7, q7, q7
17 0[0-9a-f]+ <[^>]+> f34eeffe vmaxnm.f32 q15, q15, q15
18 0[0-9a-f]+ <[^>]+> f3200f10 vminnm.f32 d0, d0, d0
19 0[0-9a-f]+ <[^>]+> f3600fb0 vminnm.f32 d16, d16, d16
20 0[0-9a-f]+ <[^>]+> f32fff1f vminnm.f32 d15, d15, d15
21 0[0-9a-f]+ <[^>]+> f36fffbf vminnm.f32 d31, d31, d31
22 0[0-9a-f]+ <[^>]+> f3200f50 vminnm.f32 q0, q0, q0
23 0[0-9a-f]+ <[^>]+> f3600ff0 vminnm.f32 q8, q8, q8
24 0[0-9a-f]+ <[^>]+> f32eef5e vminnm.f32 q7, q7, q7
25 0[0-9a-f]+ <[^>]+> f36eeffe vminnm.f32 q15, q15, q15
26 0[0-9a-f]+ <[^>]+> f3bb0000 vcvta.s32.f32 d0, d0
27 0[0-9a-f]+ <[^>]+> f3fb0120 vcvtn.s32.f32 d16, d16
28 0[0-9a-f]+ <[^>]+> f3bbf28f vcvtp.u32.f32 d15, d15
29 0[0-9a-f]+ <[^>]+> f3fbf3af vcvtm.u32.f32 d31, d31
30 0[0-9a-f]+ <[^>]+> f3bb0040 vcvta.s32.f32 q0, q0
31 0[0-9a-f]+ <[^>]+> f3fb0160 vcvtn.s32.f32 q8, q8
32 0[0-9a-f]+ <[^>]+> f3bbe2ce vcvtp.u32.f32 q7, q7
33 0[0-9a-f]+ <[^>]+> f3fbe3ee vcvtm.u32.f32 q15, q15
34 0[0-9a-f]+ <[^>]+> f3ba0500 vrinta.f32 d0, d0
35 0[0-9a-f]+ <[^>]+> f3fa0420 vrintn.f32 d16, d16
36 0[0-9a-f]+ <[^>]+> f3baf68f vrintm.f32 d15, d15
37 0[0-9a-f]+ <[^>]+> f3faf7af vrintp.f32 d31, d31
38 0[0-9a-f]+ <[^>]+> f3ba04af vrintx.f32 d0, d31
39 0[0-9a-f]+ <[^>]+> f3fa058f vrintz.f32 d16, d15
40 0[0-9a-f]+ <[^>]+> f3ba0540 vrinta.f32 q0, q0
41 0[0-9a-f]+ <[^>]+> f3fa0460 vrintn.f32 q8, q8
42 0[0-9a-f]+ <[^>]+> f3bae6ce vrintm.f32 q7, q7
43 0[0-9a-f]+ <[^>]+> f3fae7ee vrintp.f32 q15, q15
44 0[0-9a-f]+ <[^>]+> f3ba04ee vrintx.f32 q0, q15
45 0[0-9a-f]+ <[^>]+> f3fa05ce vrintz.f32 q8, q7
46 0[0-9a-f]+ <[^>]+> ff00 0f10 vmaxnm.f32 d0, d0, d0
47 0[0-9a-f]+ <[^>]+> ff40 0fb0 vmaxnm.f32 d16, d16, d16
48 0[0-9a-f]+ <[^>]+> ff0f ff1f vmaxnm.f32 d15, d15, d15
49 0[0-9a-f]+ <[^>]+> ff4f ffbf vmaxnm.f32 d31, d31, d31
50 0[0-9a-f]+ <[^>]+> ff00 0f50 vmaxnm.f32 q0, q0, q0
51 0[0-9a-f]+ <[^>]+> ff40 0ff0 vmaxnm.f32 q8, q8, q8
52 0[0-9a-f]+ <[^>]+> ff0e ef5e vmaxnm.f32 q7, q7, q7
53 0[0-9a-f]+ <[^>]+> ff4e effe vmaxnm.f32 q15, q15, q15
54 0[0-9a-f]+ <[^>]+> ff20 0f10 vminnm.f32 d0, d0, d0
55 0[0-9a-f]+ <[^>]+> ff60 0fb0 vminnm.f32 d16, d16, d16
56 0[0-9a-f]+ <[^>]+> ff2f ff1f vminnm.f32 d15, d15, d15
57 0[0-9a-f]+ <[^>]+> ff6f ffbf vminnm.f32 d31, d31, d31
58 0[0-9a-f]+ <[^>]+> ff20 0f50 vminnm.f32 q0, q0, q0
59 0[0-9a-f]+ <[^>]+> ff60 0ff0 vminnm.f32 q8, q8, q8
60 0[0-9a-f]+ <[^>]+> ff2e ef5e vminnm.f32 q7, q7, q7
61 0[0-9a-f]+ <[^>]+> ff6e effe vminnm.f32 q15, q15, q15
62 0[0-9a-f]+ <[^>]+> ffbb 0000 vcvta.s32.f32 d0, d0
63 0[0-9a-f]+ <[^>]+> fffb 0120 vcvtn.s32.f32 d16, d16
64 0[0-9a-f]+ <[^>]+> ffbb f28f vcvtp.u32.f32 d15, d15
65 0[0-9a-f]+ <[^>]+> fffb f3af vcvtm.u32.f32 d31, d31
66 0[0-9a-f]+ <[^>]+> ffbb 0040 vcvta.s32.f32 q0, q0
67 0[0-9a-f]+ <[^>]+> fffb 0160 vcvtn.s32.f32 q8, q8
68 0[0-9a-f]+ <[^>]+> ffbb e2ce vcvtp.u32.f32 q7, q7
69 0[0-9a-f]+ <[^>]+> fffb e3ee vcvtm.u32.f32 q15, q15
70 0[0-9a-f]+ <[^>]+> ffba 0500 vrinta.f32 d0, d0
71 0[0-9a-f]+ <[^>]+> fffa 0420 vrintn.f32 d16, d16
72 0[0-9a-f]+ <[^>]+> ffba f68f vrintm.f32 d15, d15
73 0[0-9a-f]+ <[^>]+> fffa f7af vrintp.f32 d31, d31
74 0[0-9a-f]+ <[^>]+> ffba 04af vrintx.f32 d0, d31
75 0[0-9a-f]+ <[^>]+> fffa 058f vrintz.f32 d16, d15
76 0[0-9a-f]+ <[^>]+> ffba 0540 vrinta.f32 q0, q0
77 0[0-9a-f]+ <[^>]+> fffa 0460 vrintn.f32 q8, q8
78 0[0-9a-f]+ <[^>]+> ffba e6ce vrintm.f32 q7, q7
79 0[0-9a-f]+ <[^>]+> fffa e7ee vrintp.f32 q15, q15
80 0[0-9a-f]+ <[^>]+> ffba 04ee vrintx.f32 q0, q15
81 0[0-9a-f]+ <[^>]+> fffa 05ce vrintz.f32 q8, q7
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