gas/testsuite/gas/arm/armv8m.main+fp.dp.d

   1 #name: Valid armv8-m.main+fp.dp
   2 #as: -march=armv8-m.main+fp.dp
   3 #source: fpv5-d16.s
   4 #objdump: -dr --prefix-addresses --show-raw-insn
   5 #skip: *-*-pe *-wince-*
   6
   7 .*: +file format .*arm.*
   8
   9 Disassembly of section .text:
  10 0[0-9a-f]+ <[^>]+> fe00 0a00    vseleq.f32      s0, s0, s0
  11 0[0-9a-f]+ <[^>]+> fe50 0aa0    vselvs.f32      s1, s1, s1
  12 0[0-9a-f]+ <[^>]+> fe2f fa0f    vselge.f32      s30, s30, s30
  13 0[0-9a-f]+ <[^>]+> fe7f faaf    vselgt.f32      s31, s31, s31
  14 0[0-9a-f]+ <[^>]+> fe00 0b00    vseleq.f64      d0, d0, d0
  15 0[0-9a-f]+ <[^>]+> fe18 8b08    vselvs.f64      d8, d8, d8
  16 0[0-9a-f]+ <[^>]+> fe2f fb0f    vselge.f64      d15, d15, d15
  17 0[0-9a-f]+ <[^>]+> fe3a ab0a    vselgt.f64      d10, d10, d10
  18 0[0-9a-f]+ <[^>]+> fe80 0a00    vmaxnm.f32      s0, s0, s0
  19 0[0-9a-f]+ <[^>]+> fec0 0aa0    vmaxnm.f32      s1, s1, s1
  20 0[0-9a-f]+ <[^>]+> fe8f fa0f    vmaxnm.f32      s30, s30, s30
  21 0[0-9a-f]+ <[^>]+> fecf faaf    vmaxnm.f32      s31, s31, s31
  22 0[0-9a-f]+ <[^>]+> fe80 0b00    vmaxnm.f64      d0, d0, d0
  23 0[0-9a-f]+ <[^>]+> fe88 8b08    vmaxnm.f64      d8, d8, d8
  24 0[0-9a-f]+ <[^>]+> fe8f fb0f    vmaxnm.f64      d15, d15, d15
  25 0[0-9a-f]+ <[^>]+> fe8a ab0a    vmaxnm.f64      d10, d10, d10
  26 0[0-9a-f]+ <[^>]+> fe80 0a40    vminnm.f32      s0, s0, s0
  27 0[0-9a-f]+ <[^>]+> fec0 0ae0    vminnm.f32      s1, s1, s1
  28 0[0-9a-f]+ <[^>]+> fe8f fa4f    vminnm.f32      s30, s30, s30
  29 0[0-9a-f]+ <[^>]+> fecf faef    vminnm.f32      s31, s31, s31
  30 0[0-9a-f]+ <[^>]+> fe80 0b40    vminnm.f64      d0, d0, d0
  31 0[0-9a-f]+ <[^>]+> fe88 8b48    vminnm.f64      d8, d8, d8
  32 0[0-9a-f]+ <[^>]+> fe8f fb4f    vminnm.f64      d15, d15, d15
  33 0[0-9a-f]+ <[^>]+> fe8a ab4a    vminnm.f64      d10, d10, d10
  34 0[0-9a-f]+ <[^>]+> febc 0ac0    vcvta.s32.f32   s0, s0
  35 0[0-9a-f]+ <[^>]+> fefd 0ae0    vcvtn.s32.f32   s1, s1
  36 0[0-9a-f]+ <[^>]+> febe fa4f    vcvtp.u32.f32   s30, s30
  37 0[0-9a-f]+ <[^>]+> feff fa6f    vcvtm.u32.f32   s31, s31
  38 0[0-9a-f]+ <[^>]+> febc 0bc0    vcvta.s32.f64   s0, d0
  39 0[0-9a-f]+ <[^>]+> fefd 0bc8    vcvtn.s32.f64   s1, d8
  40 0[0-9a-f]+ <[^>]+> febe fb4f    vcvtp.u32.f64   s30, d15
  41 0[0-9a-f]+ <[^>]+> feff fb4a    vcvtm.u32.f64   s31, d10
  42 0[0-9a-f]+ <[^>]+> eeb6 0ac0    vrintz.f32      s0, s0
  43 0[0-9a-f]+ <[^>]+> eef7 0a60    vrintx.f32      s1, s1
  44 0[0-9a-f]+ <[^>]+> eeb6 fa4f    vrintr.f32      s30, s30
  45 0[0-9a-f]+ <[^>]+> feb8 0a40    vrinta.f32      s0, s0
  46 0[0-9a-f]+ <[^>]+> fef9 0a60    vrintn.f32      s1, s1
  47 0[0-9a-f]+ <[^>]+> feba fa4f    vrintp.f32      s30, s30
  48 0[0-9a-f]+ <[^>]+> fefb fa6f    vrintm.f32      s31, s31
  49 0[0-9a-f]+ <[^>]+> eeb6 0bc0    vrintz.f64      d0, d0
  50 0[0-9a-f]+ <[^>]+> eeb7 1b41    vrintx.f64      d1, d1
  51 0[0-9a-f]+ <[^>]+> eeb6 ab4a    vrintr.f64      d10, d10
  52 0[0-9a-f]+ <[^>]+> feb8 0b40    vrinta.f64      d0, d0
  53 0[0-9a-f]+ <[^>]+> feb9 1b41    vrintn.f64      d1, d1
  54 0[0-9a-f]+ <[^>]+> feba ab4a    vrintp.f64      d10, d10
  55 0[0-9a-f]+ <[^>]+> febb ab4a    vrintm.f64      d10, d10
  56 0[0-9a-f]+ <[^>]+> eeb3 0bc0    vcvtt.f16.f64   s0, d0
  57 0[0-9a-f]+ <[^>]+> eef3 0b48    vcvtb.f16.f64   s1, d8
  58 0[0-9a-f]+ <[^>]+> eeb3 fbcf    vcvtt.f16.f64   s30, d15
  59 0[0-9a-f]+ <[^>]+> eef3 fb4a    vcvtb.f16.f64   s31, d10
  60 0[0-9a-f]+ <[^>]+> eeb2 0bc0    vcvtt.f64.f16   d0, s0
  61 0[0-9a-f]+ <[^>]+> eeb2 8b60    vcvtb.f64.f16   d8, s1
  62 0[0-9a-f]+ <[^>]+> eeb2 fbcf    vcvtt.f64.f16   d15, s30
  63 0[0-9a-f]+ <[^>]+> eeb2 ab6f    vcvtb.f64.f16   d10, s31