gas/testsuite/gas/arm/mve-vaddlv-bad.l

   1 [^:]*: Assembler messages:
   2 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
   3 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
   4 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
   5 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
   6 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
   7 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
   8 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
   9 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
  10 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
  11 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
  12 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
  13 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
  14 [^:]*:13: Error: bad type in SIMD instruction -- `vaddlv.i32 r0,r1,q0'
  15 [^:]*:14: Error: bad type in SIMD instruction -- `vaddlv.f32 r0,r1,q0'
  16 [^:]*:15: Error: bad type in SIMD instruction -- `vaddlv.s8 r0,r1,q0'
  17 [^:]*:16: Error: bad type in SIMD instruction -- `vaddlv.s16 r0,r1,q0'
  18 [^:]*:17: Error: bad type in SIMD instruction -- `vaddlv.s64 r0,r1,q0'
  19 [^:]*:18: Error: bad type in SIMD instruction -- `vaddlv.u8 r0,r1,q0'
  20 [^:]*:19: Error: bad type in SIMD instruction -- `vaddlv.u16 r0,r1,q0'
  21 [^:]*:20: Error: bad type in SIMD instruction -- `vaddlv.u64 r0,r1,q0'
  22 [^:]*:21: Error: bad type in SIMD instruction -- `vaddlva.i32 r0,r1,q0'
  23 [^:]*:22: Error: bad type in SIMD instruction -- `vaddlva.f32 r0,r1,q0'
  24 [^:]*:23: Error: bad type in SIMD instruction -- `vaddlva.s8 r0,r1,q0'
  25 [^:]*:24: Error: bad type in SIMD instruction -- `vaddlva.s16 r0,r1,q0'
  26 [^:]*:25: Error: bad type in SIMD instruction -- `vaddlva.s64 r0,r1,q0'
  27 [^:]*:26: Error: bad type in SIMD instruction -- `vaddlva.u8 r0,r1,q0'
  28 [^:]*:27: Error: bad type in SIMD instruction -- `vaddlva.u16 r0,r1,q0'
  29 [^:]*:28: Error: bad type in SIMD instruction -- `vaddlva.u64 r0,r1,q0'
  30 [^:]*:29: Error: Odd register not allowed here -- `vaddlv.s32 r1,r3,q0'
  31 [^:]*:30: Error: Even register not allowed here -- `vaddlva.s32 r0,r2,q0'
  32 [^:]*:31: Warning: instruction is UNPREDICTABLE with SP operand
  33 [^:]*:33: Error: syntax error -- `vaddlveq.s32 r0,r1,q0'
  34 [^:]*:34: Error: syntax error -- `vaddlveq.s32 r0,r1,q0'
  35 [^:]*:36: Error: syntax error -- `vaddlveq.s32 r0,r1,q0'
  36 [^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vaddlvt.s32 r0,r1,q0'
  37 [^:]*:39: Error: instruction missing MVE vector predication code -- `vaddlv.s32 r0,r1,q0'
  38 [^:]*:41: Error: syntax error -- `vaddlvaeq.s32 r0,r1,q0'
  39 [^:]*:42: Error: syntax error -- `vaddlvaeq.s32 r0,r1,q0'
  40 [^:]*:44: Error: syntax error -- `vaddlvaeq.s32 r0,r1,q0'
  41 [^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vaddlvat.s32 r0,r1,q0'
  42 [^:]*:47: Error: instruction missing MVE vector predication code -- `vaddlva.s32 r0,r1,q0'