4 .macro all_vstr op, imm
5 .irp op1, q0, q1, q2, q4, q7
6 .irp op2, q0, q1, q2, q4, q7
7 \op \op1, [\op2, #\imm]
8 \op \op1, [\op2, #-\imm]
9 \op \op1, [\op2, #\imm]!
10 \op \op1, [\op2, #-\imm]!
15 .irp data, .32, .u32, .s32, .f32
16 .irp imm, 0, 4, 8, 16, 32, 64, 128, 256, 508, 340, 168, 60, 480
17 all_vstr vstrw\data, \imm
21 .irp data, .64, .u64, .s64
22 .irp imm, 0, 8, 16, 32, 64, 128, 256, 512, 1016, 680, 336, 960, 120
23 all_vstr vstrd\data, \imm
29 vstrwt.32 q0, [q1, #4]
30 vstrwe.u32 q1, [q0, #-4]
32 vstrwe.f32 q3, [q4, #-508]
34 vstrdt.64 q4, [q5, #512]
35 vstrde.u64 q5, [q6, #1016]
36 vstrdt.s64 q6, [q7, #-1016]
38 .macro all_vldr_qq op, op1, op2, imm
39 \op \op1, [\op2, #\imm]
40 \op \op1, [\op2, #-\imm]
41 \op \op1, [\op2, #\imm]!
42 \op \op1, [\op2, #-\imm]!
45 .macro all_vldr_q0 op, imm
46 .irp op2, q1, q2, q4, q7
47 all_vldr_qq \op, q0, \op2, \imm
51 .macro all_vldr_q1 op, imm
52 .irp op2, q0, q2, q4, q7
53 all_vldr_qq \op, q1, \op2, \imm
57 .macro all_vldr_q2 op, imm
58 .irp op2, q0, q1, q4, q7
59 all_vldr_qq \op, q2, \op2, \imm
63 .macro all_vldr_q4 op, imm
64 .irp op2, q0, q1, q2, q7
65 all_vldr_qq \op, q4, \op2, \imm
69 .macro all_vldr_q7 op, imm
70 .irp op2, q0, q1, q2, q4
71 all_vldr_qq \op, q7, \op2, \imm
75 .macro all_vldr op, imm
83 .irp data, .32, .u32, .s32, .f32
84 .irp imm, 0, 4, 8, 16, 32, 64, 128, 256, 508, 340, 168, 60, 480
85 all_vldr vldrw\data, \imm
89 .irp data, .64, .u64, .s64
90 .irp imm, 0, 8, 16, 32, 64, 128, 256, 512, 1016, 680, 336, 960, 120
91 all_vldr vldrd\data, \imm
96 vldrwt.32 q0, [q1, #4]
97 vldrwe.u32 q1, [q0, #-4]
99 vldrwe.f32 q3, [q4, #-508]
101 vldrdt.64 q4, [q5, #512]
102 vldrde.u64 q5, [q6, #1016]
103 vldrdt.s64 q6, [q7, #-1016]