gas/testsuite/gas/arm/neon-cov.s

   1 @ Neon tests. Basic bitfield tests, using zero for as many registers/fields as
   2 @ possible, but without causing instructions to be badly-formed.
   3
   4         .arm
   5         .syntax unified
   6         .text
   7
   8         .macro regs3_1 op opq vtype
   9         \op\vtype q0,q0,q0
  10         \opq\vtype q0,q0,q0
  11         \op\vtype d0,d0,d0
  12         .endm
  13
  14         .macro dregs3_1 op vtype
  15         \op\vtype d0,d0,d0
  16         .endm
  17
  18         .macro regn3_1 op operand2 vtype
  19         \op\vtype d0,q0,\operand2
  20         .endm
  21
  22         .macro regl3_1 op operand2 vtype
  23         \op\vtype q0,d0,\operand2
  24         .endm
  25
  26         .macro regw3_1 op operand2 vtype
  27         \op\vtype q0,q0,\operand2
  28         .endm
  29
  30         .macro regs2_1 op opq vtype
  31         \op\vtype q0,q0
  32         \opq\vtype q0,q0
  33         \op\vtype d0,d0
  34         .endm
  35
  36         .macro regs3_su_32 op opq
  37         regs3_1 \op \opq .s8
  38         regs3_1 \op \opq .s16
  39         regs3_1 \op \opq .s32
  40         regs3_1 \op \opq .u8
  41         regs3_1 \op \opq .u16
  42         regs3_1 \op \opq .u32
  43         .endm
  44
  45         regs3_su_32 vaba vabaq
  46         regs3_su_32 vhadd vhaddq
  47         regs3_su_32 vrhadd vrhaddq
  48         regs3_su_32 vhsub vhsubq
  49
  50         .macro regs3_su_64 op opq
  51         regs3_1 \op \opq .s8
  52         regs3_1 \op \opq .s16
  53         regs3_1 \op \opq .s32
  54         regs3_1 \op \opq .s64
  55         regs3_1 \op \opq .u8
  56         regs3_1 \op \opq .u16
  57         regs3_1 \op \opq .u32
  58         regs3_1 \op \opq .u64
  59         .endm
  60
  61         regs3_su_64 vqadd vqaddq
  62         regs3_su_64 vqsub vqsubq
  63         regs3_su_64 vrshl vrshlq
  64         regs3_su_64 vqrshl vqrshlq
  65
  66         regs3_su_64 vshl vshlq
  67         regs3_su_64 vqshl vqshlq
  68
  69         .macro regs2i_1 op opq imm vtype
  70         \op\vtype q0,q0,\imm
  71         \opq\vtype q0,q0,\imm
  72         \op\vtype d0,d0,\imm
  73         .endm
  74
  75         .macro regs2i_su_64 op opq imm
  76         regs2i_1 \op \opq \imm .s8
  77         regs2i_1 \op \opq \imm .s16
  78         regs2i_1 \op \opq \imm .s32
  79         regs2i_1 \op \opq \imm .s64
  80         regs2i_1 \op \opq \imm .u8
  81         regs2i_1 \op \opq \imm .u16
  82         regs2i_1 \op \opq \imm .u32
  83         regs2i_1 \op \opq \imm .u64
  84         .endm
  85
  86         .macro regs2i_i_64 op opq imm
  87         regs2i_1 \op \opq \imm .i8
  88         regs2i_1 \op \opq \imm .i16
  89         regs2i_1 \op \opq \imm .i32
  90         regs2i_1 \op \opq \imm .i64
  91         .endm
  92
  93         regs2i_i_64 vshl vshlq 0
  94         regs2i_su_64 vqshl vqshlq 0
  95
  96         .macro regs3_ntyp op opq
  97         regs3_1 \op \opq .8
  98         .endm
  99
 100         regs3_ntyp vand vandq
 101         regs3_ntyp vbic vbicq
 102         regs3_ntyp vorr vorrq
 103         regs3_ntyp vorn vornq
 104         regs3_ntyp veor veorq
 105
 106         .macro logic_imm_1 op opq imm vtype
 107         \op\vtype q0,\imm
 108         \opq\vtype q0,\imm
 109         \op\vtype d0,\imm
 110         .endm
 111
 112         .macro logic_imm op opq
 113         logic_imm_1 \op \opq 0x000000ff .i32
 114         logic_imm_1 \op \opq 0x0000ff00 .i32
 115         logic_imm_1 \op \opq 0x00ff0000 .i32
 116         logic_imm_1 \op \opq 0xff000000 .i32
 117         logic_imm_1 \op \opq 0x00ff .i16
 118         logic_imm_1 \op \opq 0xff00 .i16
 119         .endm
 120
 121         logic_imm vbic vbicq
 122         logic_imm vorr vorrq
 123
 124         .macro logic_inv_imm op opq
 125         logic_imm_1 \op \opq 0xffffff00 .i32
 126         logic_imm_1 \op \opq 0xffff00ff .i32
 127         logic_imm_1 \op \opq 0xff00ffff .i32
 128         logic_imm_1 \op \opq 0x00ffffff .i32
 129         logic_imm_1 \op \opq 0xff00 .i16
 130         logic_imm_1 \op \opq 0x00ff .i16
 131         .endm
 132
 133         logic_inv_imm vand vandq
 134         logic_inv_imm vorn vornq
 135
 136         regs3_ntyp vbsl vbslq
 137         regs3_ntyp vbit vbitq
 138         regs3_ntyp vbif vbifq
 139
 140         .macro regs3_suf_32 op opq
 141         regs3_1 \op \opq .s8
 142         regs3_1 \op \opq .s16
 143         regs3_1 \op \opq .s32
 144         regs3_1 \op \opq .u8
 145         regs3_1 \op \opq .u16
 146         regs3_1 \op \opq .u32
 147         regs3_1 \op \opq .f32
 148         .endm
 149
 150         .macro regs3_if_32 op opq
 151         regs3_1 \op \opq .i8
 152         regs3_1 \op \opq .i16
 153         regs3_1 \op \opq .i32
 154         regs3_1 \op \opq .f32
 155         .endm
 156
 157         regs3_suf_32 vabd vabdq
 158         regs3_suf_32 vmax vmaxq
 159         regs3_suf_32 vmin vminq
 160
 161         regs3_suf_32 vcge vcgeq
 162         regs3_suf_32 vcgt vcgtq
 163         regs3_suf_32 vcle vcleq
 164         regs3_suf_32 vclt vcltq
 165
 166         regs3_if_32 vceq vceqq
 167
 168         .macro regs2i_sf_0 op opq
 169         regs2i_1 \op \opq 0 .s8
 170         regs2i_1 \op \opq 0 .s16
 171         regs2i_1 \op \opq 0 .s32
 172         regs2i_1 \op \opq 0 .f32
 173         .endm
 174
 175         regs2i_sf_0 vcge vcgeq
 176         regs2i_sf_0 vcgt vcgtq
 177         regs2i_sf_0 vcle vcleq
 178         regs2i_sf_0 vclt vcltq
 179
 180         .macro regs2i_if_0 op opq
 181         regs2i_1 \op \opq 0 .i8
 182         regs2i_1 \op \opq 0 .i16
 183         regs2i_1 \op \opq 0 .i32
 184         regs2i_1 \op \opq 0 .f32
 185         .endm
 186
 187         regs2i_if_0 vceq vceqq
 188
 189         .macro dregs3_suf_32 op
 190         dregs3_1 \op .s8
 191         dregs3_1 \op .s16
 192         dregs3_1 \op .s32
 193         dregs3_1 \op .u8
 194         dregs3_1 \op .u16
 195         dregs3_1 \op .u32
 196         dregs3_1 \op .f32
 197         .endm
 198
 199         dregs3_suf_32 vpmax
 200         dregs3_suf_32 vpmin
 201
 202         .macro sregs3_1 op opq vtype
 203         \op\vtype q0,q0,q0
 204         \opq\vtype q0,q0,q0
 205         \op\vtype d0,d0,d0
 206         .endm
 207
 208         .macro sclr21_1 op opq vtype
 209         \op\vtype q0,q0,d0[0]
 210         \opq\vtype q0,q0,d0[0]
 211         \op\vtype d0,d0,d0[0]
 212         .endm
 213
 214         .macro mul_incl_scalar op opq
 215         regs3_1 \op \opq .i8
 216         regs3_1 \op \opq .i16
 217         regs3_1 \op \opq .i32
 218         regs3_1 \op \opq .f32
 219         sclr21_1 \op \opq .i16
 220         sclr21_1 \op \opq .i32
 221         sclr21_1 \op \opq .f32
 222         .endm
 223
 224         mul_incl_scalar vmla vmlaq
 225         mul_incl_scalar vmls vmlsq
 226
 227         .macro dregs3_if_32 op
 228         dregs3_1 \op .i8
 229         dregs3_1 \op .i16
 230         dregs3_1 \op .i32
 231         dregs3_1 \op .f32
 232         .endm
 233
 234         dregs3_if_32 vpadd
 235
 236         .macro regs3_if_64 op opq
 237         regs3_1 \op \opq .i8
 238         regs3_1 \op \opq .i16
 239         regs3_1 \op \opq .i32
 240         regs3_1 \op \opq .i64
 241         regs3_1 \op \opq .f32
 242         .endm
 243
 244         regs3_if_64 vadd vaddq
 245         regs3_if_64 vsub vsubq
 246
 247         .macro regs3_sz_32 op opq
 248         regs3_1 \op \opq .8
 249         regs3_1 \op \opq .16
 250         regs3_1 \op \opq .32
 251         .endm
 252
 253         regs3_sz_32 vtst vtstq
 254
 255         .macro regs3_ifp_32 op opq
 256         regs3_1 \op \opq .i8
 257         regs3_1 \op \opq .i16
 258         regs3_1 \op \opq .i32
 259         regs3_1 \op \opq .f32
 260         regs3_1 \op \opq .p8
 261         .endm
 262
 263         regs3_ifp_32 vmul vmulq
 264
 265         .macro dqmulhs op opq
 266         regs3_1 \op \opq .s16
 267         regs3_1 \op \opq .s32
 268         sclr21_1 \op \opq .s16
 269         sclr21_1 \op \opq .s32
 270         .endm
 271
 272         dqmulhs vqdmulh vqdmulhq
 273         dqmulhs vqrdmulh vqrdmulhq
 274
 275         regs3_1 vacge vacgeq .f32
 276         regs3_1 vacgt vacgtq .f32
 277         regs3_1 vacle vacleq .f32
 278         regs3_1 vaclt vacltq .f32
 279         regs3_1 vrecps vrecpsq .f32
 280         regs3_1 vrsqrts vrsqrtsq .f32
 281
 282         .macro regs2_sf_32 op opq
 283         regs2_1 \op \opq .s8
 284         regs2_1 \op \opq .s16
 285         regs2_1 \op \opq .s32
 286         regs2_1 \op \opq .f32
 287         .endm
 288
 289         regs2_sf_32 vabs vabsq
 290         regs2_sf_32 vneg vnegq
 291
 292         .macro rshift_imm op opq
 293         regs2i_1 \op \opq 7 .s8
 294         regs2i_1 \op \opq 15 .s16
 295         regs2i_1 \op \opq 31 .s32
 296         regs2i_1 \op \opq 63 .s64
 297         regs2i_1 \op \opq 7 .u8
 298         regs2i_1 \op \opq 15 .u16
 299         regs2i_1 \op \opq 31 .u32
 300         regs2i_1 \op \opq 63 .u64
 301         .endm
 302
 303         rshift_imm vshr vshrq
 304         rshift_imm vrshr vrshrq
 305         rshift_imm vsra vsraq
 306         rshift_imm vrsra vrsraq
 307
 308         regs2i_1 vsli vsliq 0 .8
 309         regs2i_1 vsli vsliq 0 .16
 310         regs2i_1 vsli vsliq 0 .32
 311         regs2i_1 vsli vsliq 0 .64
 312
 313         regs2i_1 vsri vsriq 7 .8
 314         regs2i_1 vsri vsriq 15 .16
 315         regs2i_1 vsri vsriq 31 .32
 316         regs2i_1 vsri vsriq 63 .64
 317
 318         regs2i_1 vqshlu vqshluq 0 .s8
 319         regs2i_1 vqshlu vqshluq 0 .s16
 320         regs2i_1 vqshlu vqshluq 0 .s32
 321         regs2i_1 vqshlu vqshluq 0 .s64
 322
 323         .macro qrshift_imm op
 324         regn3_1 \op 7 .s16
 325         regn3_1 \op 15 .s32
 326         regn3_1 \op 31 .s64
 327         regn3_1 \op 7 .u16
 328         regn3_1 \op 15 .u32
 329         regn3_1 \op 31 .u64
 330         .endm
 331
 332         .macro qrshiftu_imm op
 333         regn3_1 \op 7 .s16
 334         regn3_1 \op 15 .s32
 335         regn3_1 \op 31 .s64
 336         .endm
 337
 338         .macro qrshifti_imm op
 339         regn3_1 \op 7 .i16
 340         regn3_1 \op 15 .i32
 341         regn3_1 \op 31 .i64
 342         .endm
 343
 344         qrshift_imm vqshrn
 345         qrshift_imm vqrshrn
 346         qrshiftu_imm vqshrun
 347         qrshiftu_imm vqrshrun
 348
 349         qrshifti_imm vshrn
 350         qrshifti_imm vrshrn
 351
 352         regl3_1 vshll 1 .s8
 353         regl3_1 vshll 1 .s16
 354         regl3_1 vshll 1 .s32
 355         regl3_1 vshll 1 .u8
 356         regl3_1 vshll 1 .u16
 357         regl3_1 vshll 1 .u32
 358
 359         regl3_1 vshll 8 .i8
 360         regl3_1 vshll 16 .i16
 361         regl3_1 vshll 32 .i32
 362
 363         .macro convert op opr arg="" t1=".s32.f32" t2=".u32.f32" t3=".f32.s32" t4=".f32.u32"
 364         \op\t1 \opr,\opr\arg
 365         \op\t2 \opr,\opr\arg
 366         \op\t3 \opr,\opr\arg
 367         \op\t4 \opr,\opr\arg
 368         .endm
 369
 370         convert vcvt q0
 371         convert vcvtq q0
 372         convert vcvt d0
 373         convert vcvt q0 ",1"
 374         convert vcvtq q0 ",1"
 375         convert vcvt d0 ",1"
 376
 377         vmov q0,q0
 378         vmov d0,d0
 379         vmov.8 d0[0],r0
 380         vmov.16 d0[0],r0
 381         vmov.32 d0[0],r0
 382         vmov d0,r0,r0
 383         vmov.s8 r0,d0[0]
 384         vmov.s16 r0,d0[0]
 385         vmov.u8 r0,d0[0]
 386         vmov.u16 r0,d0[0]
 387         vmov.32 r0,d0[0]
 388         vmov r0,r1,d0
 389
 390         .macro mov_imm op imm vtype
 391         \op\vtype q0,\imm
 392         \op\vtype d0,\imm
 393         .endm
 394
 395         mov_imm vmov 0x00000077 .i32
 396         mov_imm vmvn 0x00000077 .i32
 397         mov_imm vmov 0x00007700 .i32
 398         mov_imm vmvn 0x00007700 .i32
 399         mov_imm vmov 0x00770000 .i32
 400         mov_imm vmvn 0x00770000 .i32
 401         mov_imm vmov 0x77000000 .i32
 402         mov_imm vmvn 0x77000000 .i32
 403         mov_imm vmov 0x0077 .i16
 404         mov_imm vmvn 0x0077 .i16
 405         mov_imm vmov 0x7700 .i16
 406         mov_imm vmvn 0x7700 .i16
 407         mov_imm vmov 0x000077ff .i32
 408         mov_imm vmvn 0x000077ff .i32
 409         mov_imm vmov 0x0077ffff .i32
 410         mov_imm vmvn 0x0077ffff .i32
 411         mov_imm vmov 0x77 .i8
 412         mov_imm vmov 0xff0000ff000000ff .i64
 413         mov_imm vmov 0x40880000 .f32
 414
 415         vmvn q0,q0
 416         vmvnq q0,q0
 417         vmvn d0,d0
 418
 419         .macro long_ops op
 420         regl3_1 \op d0 .s8
 421         regl3_1 \op d0 .s16
 422         regl3_1 \op d0 .s32
 423         regl3_1 \op d0 .u8
 424         regl3_1 \op d0 .u16
 425         regl3_1 \op d0 .u32
 426         .endm
 427
 428         long_ops vabal
 429         long_ops vabdl
 430         long_ops vaddl
 431         long_ops vsubl
 432
 433         .macro long_mac op
 434         regl3_1 \op d0 .s8
 435         regl3_1 \op d0 .s16
 436         regl3_1 \op d0 .s32
 437         regl3_1 \op d0 .u8
 438         regl3_1 \op d0 .u16
 439         regl3_1 \op d0 .u32
 440         regl3_1 \op "d0[0]" .s16
 441         regl3_1 \op "d0[0]" .s32
 442         regl3_1 \op "d0[0]" .u16
 443         regl3_1 \op "d0[0]" .u32
 444         .endm
 445
 446         long_mac vmlal
 447         long_mac vmlsl
 448
 449         .macro wide_ops op
 450         regw3_1 \op d0 .s8
 451         regw3_1 \op d0 .s16
 452         regw3_1 \op d0 .s32
 453         regw3_1 \op d0 .u8
 454         regw3_1 \op d0 .u16
 455         regw3_1 \op d0 .u32
 456         .endm
 457
 458         wide_ops vaddw
 459         wide_ops vsubw
 460
 461         .macro narr_ops op
 462         regn3_1 \op q0 .i16
 463         regn3_1 \op q0 .i32
 464         regn3_1 \op q0 .i64
 465         .endm
 466
 467         narr_ops vaddhn
 468         narr_ops vraddhn
 469         narr_ops vsubhn
 470         narr_ops vrsubhn
 471
 472         .macro long_dmac op
 473         regl3_1 \op d0 .s16
 474         regl3_1 \op d0 .s32
 475         regl3_1 \op "d0[0]" .s16
 476         regl3_1 \op "d0[0]" .s32
 477         .endm
 478
 479         long_dmac vqdmlal
 480         long_dmac vqdmlsl
 481         long_dmac vqdmull
 482
 483         regl3_1 vmull d0 .s8
 484         regl3_1 vmull d0 .s16
 485         regl3_1 vmull d0 .s32
 486         regl3_1 vmull d0 .u8
 487         regl3_1 vmull d0 .u16
 488         regl3_1 vmull d0 .u32
 489         regl3_1 vmull d0 .p8
 490         regl3_1 vmull "d0[0]" .s16
 491         regl3_1 vmull "d0[0]" .s32
 492         regl3_1 vmull "d0[0]" .u16
 493         regl3_1 vmull "d0[0]" .u32
 494
 495         vext.8 q0,q0,q0,0
 496         vextq.8 q0,q0,q0,0
 497         vext.8 d0,d0,d0,0
 498
 499         .macro revs op opq vtype
 500         \op\vtype q0,q0
 501         \opq\vtype q0,q0
 502         \op\vtype d0,d0
 503         .endm
 504
 505         revs vrev64 vrev64q .8
 506         revs vrev64 vrev64q .16
 507         revs vrev64 vrev64q .32
 508         revs vrev32 vrev32q .8
 509         revs vrev32 vrev32q .16
 510         revs vrev16 vrev16q .8
 511
 512         .macro dups op opq vtype
 513         \op\vtype q0,r0
 514         \opq\vtype q0,r0
 515         \op\vtype d0,r0
 516         \op\vtype q0,d0[0]
 517         \opq\vtype q0,d0[0]
 518         \op\vtype d0,d0[0]
 519         .endm
 520
 521         dups vdup vdupq .8
 522         dups vdup vdupq .16
 523         dups vdup vdupq .32
 524
 525         .macro binop_3typ op op1 op2 t1 t2 t3
 526         \op\t1 \op1,\op2
 527         \op\t2 \op1,\op2
 528         \op\t3 \op1,\op2
 529         .endm
 530
 531         binop_3typ vmovl q0 d0 .s8 .s16 .s32
 532         binop_3typ vmovl q0 d0 .u8 .u16 .u32
 533         binop_3typ vmovn d0 q0 .i16 .i32 .i64
 534         binop_3typ vqmovn d0 q0 .s16 .s32 .s64
 535         binop_3typ vqmovn d0 q0 .u16 .u32 .u64
 536         binop_3typ vqmovun d0 q0 .s16 .s32 .s64
 537
 538         .macro binops op opq vtype="" rhs="0"
 539         \op\vtype q0,q\rhs
 540         \opq\vtype q0,q\rhs
 541         \op\vtype d0,d\rhs
 542         .endm
 543
 544         .macro regs2_sz_32 op opq
 545         binops \op \opq .8 1
 546         binops \op \opq .16 1
 547         binops \op \opq .32 1
 548         .endm
 549
 550         regs2_sz_32 vzip vzipq
 551         regs2_sz_32 vuzp vuzpq
 552
 553         .macro regs2_s_32 op opq
 554         binops \op \opq .s8
 555         binops \op \opq .s16
 556         binops \op \opq .s32
 557         .endm
 558
 559         regs2_s_32 vqabs vqabsq
 560         regs2_s_32 vqneg vqnegq
 561
 562         .macro regs2_su_32 op opq
 563         regs2_s_32 \op \opq
 564         binops \op \opq .u8
 565         binops \op \opq .u16
 566         binops \op \opq .u32
 567         .endm
 568
 569         regs2_su_32 vpadal vpadalq
 570         regs2_su_32 vpaddl vpaddlq
 571
 572         binops vrecpe vrecpeq .u32
 573         binops vrecpe vrecpeq .f32
 574         binops vrsqrte vrsqrteq .u32
 575         binops vrsqrte vrsqrteq .f32
 576
 577         regs2_s_32 vcls vclsq
 578
 579         .macro regs2_i_32 op opq
 580         binops \op \opq .i8
 581         binops \op \opq .i16
 582         binops \op \opq .i32
 583         .endm
 584
 585         regs2_i_32 vclz vclzq
 586
 587         binops vcnt vcntq .8
 588
 589         binops vswp vswpq "" 1
 590
 591         regs2_sz_32 vtrn vtrnq
 592
 593         vtbl.8 d0,{d0},d0
 594         vtbx.8 d0,{d0},d0
 595