1 @ VFP Instructions for D variants (Double precision)
5 @ First we test the basic syntax and bit patterns of the opcodes.
6 @ Most of these tests deliberately use d0/r0 to avoid setting
7 @ any more bits than necessary.
9 @ Comparison operations
16 @ Monadic data operations
23 @ Dyadic data operations
35 @ Load/store operations
40 @ Load/store multiple operations
56 @ Conversion operations
69 @ ARM from VFP operations
74 @ VFP From ARM operations
79 @ Now we test that the register fields are updated correctly for
80 @ each class of instruction.
82 @ Single register operations (compare-zero):
88 @ Two register comparison operations:
98 @ Two register data operations (monadic)
108 @ Three register data operations (dyadic)
121 @ Conversion operations
136 @ Move to VFP from ARM
149 @ Move to ARM from VFP
162 @ Load/store operations
168 fldd d0, [r0, #-1020]
172 fstd d12, [r12, #804]
174 @ Load/store multiple operations
184 fldmiad r0, {d14-d15}
188 @ Check that we assemble all the register names correctly
207 @ Now we check the placement of the conditional execution substring.
208 @ On VFP this is always at the end of the instruction.
210 @ Comparison operations
217 @ Monadic data operations
224 @ Dyadic data operations
236 @ Load/store operations
241 @ Load/store multiple operations
253 fstmeadeq r10!, {d12}
254 fstmdbdeq r11!, {d11}
255 fstmfddeq r12!, {d10}
257 @ Conversion operations
270 @ ARM from VFP operations
275 @ VFP From ARM operations
280 # Add three nop instructions to ensure that the
281 # output is 32-byte aligned as required for arm-aout.