1 @ VFP Instructions for v1xD variants (Single precision only)
5 @ First we test the basic syntax and bit patterns of the opcodes.
6 @ Most of these tests deliberatly use s0/r0 to avoid setting
7 @ any more bits than necessary.
9 @ Comparison operations
18 @ Monadic data operations
25 @ Dyadic data operations
37 @ Load/store operations
42 @ Load/store multiple operations
72 @ Conversion operations
82 @ ARM from VFP operations
89 @ VFP From ARM operations
96 @ Now we test that the register fields are updated correctly for
97 @ each class of instruction.
99 @ Single register operations (compare-zero):
105 @ Two register comparison operations:
115 @ Two register data operations (monadic)
125 @ Three register data operations (dyadic)
138 @ Conversion operations
154 @ Move to VFP from ARM
167 @ Move to ARM from VFP
180 @ Load/store operations
186 flds s0, [r0, #-1020]
190 fsts s21, [r12, #804]
192 @ Load/store multiple operations
202 fldmias r0, {s30-s31}
214 fstmiax r0, {d14-d15}
218 @ Check that we assemble all the register names correctly
253 @ Now we check the placement of the conditional execution substring.
254 @ On VFP this is always at the end of the instruction.
255 @ We use different register numbers here to check for correct
258 @ Comparison operations
267 @ Monadic data operations
274 @ Dyadic data operations
278 fmacseq s31, s30, s29
279 fmscseq s28, s27, s26
280 fmulseq s25, s24, s23
281 fnmacseq s22, s21, s20
282 fnmscseq s19, s18, s17
283 fnmulseq s16, s15, s14
284 fsubseq s13, s12, s11
286 @ Load/store operations
291 @ Load/store multiple operations
319 fstmfdxeq r10!, {d12}
321 @ Conversion operations
330 @ ARM from VFP operations
335 @ VFP From ARM operations