1 @ Test file for ARM/GAS -- vldr reg, =... expressions.
6 # test both low and high index of the
7 # Advanced SIMD and Floating-point reg.
8 .macro vlxr regtype const
9 .irp regindex, 0, 14, 28, 31
10 vldr \regtype\regindex, \const
14 .macro vlxreq regtype const
15 .irp regindex, 0, 14, 28, 31
16 vldreq \regtype\regindex, \const
20 .macro vlxrmi regtype const
21 .irp regindex, 0, 14, 28, 31
22 vldrmi \regtype\regindex, \const
39 vlxreq s "=0x0000ff00"
40 vlxreq s "=0xffff00ff"
41 vlxreq s "=0x000fff00"
45 vlxrmi s "=0x000000ff"
46 vlxrmi s "=0xffffff00"
47 vlxrmi s "=0x0000fff0"
63 vlxreq d "=0x0000ff00"
64 vlxreq d "=0xffff00ff"
65 vlxreq d "=0x000fff00"
69 vlxrmi d "=0x000000ff"
70 vlxrmi d "=0xffffff00"
71 vlxrmi d "=0x0000ffff"
75 vlxr d "=0xff00000000000000"
77 vlxr d "=0x0fff000000000000"
81 vlxr d "=0x00ff00000000000"
82 vlxr d "=0xff00ffff0000000"
83 vlxr d "=0x00fff0000000000"
87 vlxreq d "=0x0000ff0000000000"
88 vlxreq d "=0xffff00ff00000000"
89 vlxreq d "=0x000fff0000000000"
93 vlxrmi d "=0x000000ff00000000"
94 vlxrmi d "=0xffffff0000000000"
95 vlxrmi d "=0x0000fff000000000"
98 # pool should be aligned to 8-byte.
100 vldr d1, =0x0000fff000000000
103 # no error when code is align already.
106 vldr d1, =0x0000fff000000000
110 vldr d1, =0x0000fff000000000
113 vldr d3, =0x0000fff000000001
114 # reuse padding slot A
117 vldr d5, =0x0000fff000000001
119 vldr d6, =0x0000fff000000002
121 vldr d7, =0x0000fff000000003
125 vldr d9, =0x0000fff000000004
126 # reuse padding slot B
127 vldr s10, =0xff000003
129 vldr d11, =0x0000fff000000005
131 vldr s12, =0xff000004
133 vldr s13, =0xff000005
134 # reuse value of s4 in pool
135 vldr s14, =0xff000001
136 # reuse high part of d1 in pool
137 vldr s15, =0x0000fff0
138 # 8-byte entry reuse two 4-byte entries.
139 # this reuse should only happen for
142 vldr d16, =0xff000005ff000004
143 # d17 should not reuse high part of d11 and s12.
144 # because the it's align 8-byte aligned.
145 vldr d17, =0xff0000040000fff0