Add support for a __gcc_isr pseudo isntruction to the AVR assembler.
[deliverable/binutils-gdb.git] / gas / testsuite / gas / avr / gccisr-01.d
1 #name: gccisr-01: __gcc_isr pseudo instruction
2 #as: -mgcc-isr -mavr4
3 #objdump: -dz
4 #target: avr-*-*
5
6 .*: +file format elf32-avr
7
8
9 Disassembly of section \.text:
10
11 00000000 <__start1>:
12 0: 68 94 set
13
14 00000002 <__vec1_start>:
15 2: 0f 92 push r0
16 4: 0f b6 in r0, 0x3f ; 63
17 6: 0f 92 push r0
18 8: 01 30 cpi r16, 0x01 ; 1
19 a: 0f 90 pop r0
20 c: 0f be out 0x3f, r0 ; 63
21 e: 0f 90 pop r0
22 10: e8 94 clt
23
24 00000012 <__data1>:
25 12: 00 e0 ldi r16, 0x00 ; 0
26 14: 08 00 \.word 0x0008 ; \?\?\?\?
27
28 00000016 <__start2>:
29 16: 68 94 set
30
31 00000018 <__vec2_start>:
32 18: e1 e0 ldi r30, 0x01 ; 1
33 1a: f0 91 00 00 lds r31, 0x0000 ; 0x800000 <__data6\+0x7fff40>
34 1e: f0 93 00 00 sts 0x0000, r31 ; 0x800000 <__data6\+0x7fff40>
35 22: 12 01 movw r2, r4
36 24: 12 95 swap r17
37 26: 18 95 reti
38 28: 78 10 cpse r7, r8
39 2a: 78 94 sei
40 2c: f8 94 cli
41 2e: af b6 in r10, 0x3f ; 63
42 30: af be out 0x3f, r10 ; 63
43 32: 18 95 reti
44 34: e8 94 clt
45
46 00000036 <__data2>:
47 36: 00 e0 ldi r16, 0x00 ; 0
48 38: 0f 00 \.word 0x000f ; \?\?\?\?
49
50 0000003a <__start3>:
51 3a: 68 94 set
52
53 0000003c <__vec3_start>:
54 3c: 1f 92 push r1
55 3e: 1f b6 in r1, 0x3f ; 63
56 40: 1f 92 push r1
57 42: 11 24 eor r1, r1
58 44: 8f 93 push r24
59 46: 8f 91 pop r24
60 48: 1f 90 pop r1
61 4a: 1f be out 0x3f, r1 ; 63
62 4c: 1f 90 pop r1
63 4e: 18 95 reti
64 50: 8f 91 pop r24
65 52: 1f 90 pop r1
66 54: 1f be out 0x3f, r1 ; 63
67 56: 1f 90 pop r1
68 58: 18 95 reti
69 5a: 13 94 inc r1
70 5c: e8 94 clt
71
72 0000005e <__data3>:
73 5e: 00 e0 ldi r16, 0x00 ; 0
74 60: 11 00 \.word 0x0011 ; \?\?\?\?
75
76 00000062 <__start4>:
77 62: 68 94 set
78
79 00000064 <__vec4_start>:
80 64: 0f 92 push r0
81 66: 0f b6 in r0, 0x3f ; 63
82 68: 0f 92 push r0
83 6a: 1f 92 push r1
84 6c: 11 24 eor r1, r1
85 6e: 8f 93 push r24
86 70: 8f 91 pop r24
87 72: 1f 90 pop r1
88 74: 0f 90 pop r0
89 76: 0f be out 0x3f, r0 ; 63
90 78: 0f 90 pop r0
91 7a: 18 95 reti
92 7c: 8f 91 pop r24
93 7e: 1f 90 pop r1
94 80: 0f 90 pop r0
95 82: 0f be out 0x3f, r0 ; 63
96 84: 0f 90 pop r0
97 86: 18 95 reti
98 88: 01 9f mul r16, r17
99 8a: e8 94 clt
100
101 0000008c <__data4>:
102 8c: 00 e0 ldi r16, 0x00 ; 0
103 8e: 14 00 \.word 0x0014 ; \?\?\?\?
104
105 00000090 <__start5>:
106 90: 68 94 set
107
108 00000092 <__vec5_start>:
109 92: 0f 92 push r0
110 94: c8 95 lpm
111 96: 0f 90 pop r0
112 98: 18 95 reti
113 9a: 0f 90 pop r0
114 9c: 18 95 reti
115 9e: e8 94 clt
116
117 000000a0 <__data5>:
118 a0: 00 e0 ldi r16, 0x00 ; 0
119 a2: 07 00 \.word 0x0007 ; \?\?\?\?
120
121 000000a4 <__start6>:
122 a4: 68 94 set
123
124 000000a6 <__vec6_start>:
125 a6: af 93 push r26
126 a8: af b7 in r26, 0x3f ; 63
127 aa: af 93 push r26
128 ac: af 91 pop r26
129 ae: af bf out 0x3f, r26 ; 63
130 b0: af 91 pop r26
131 b2: 18 95 reti
132 b4: af 91 pop r26
133 b6: af bf out 0x3f, r26 ; 63
134 b8: af 91 pop r26
135 ba: 18 95 reti
136 bc: 88 94 clc
137 be: e8 94 clt
138
139 000000c0 <__data6>:
140 c0: 00 e0 ldi r16, 0x00 ; 0
141 c2: 0d 00 \.word 0x000d ; \?\?\?\?
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