1 #name: gccisr-01: __gcc_isr pseudo instruction
6 .*: +file format elf32-avr
9 Disassembly of section \.text:
14 00000002 <__vec1_start>:
16 4: 0f b6 in r0, 0x3f ; 63
18 8: 01 30 cpi r16, 0x01 ; 1
20 c: 0f be out 0x3f, r0 ; 63
25 12: 00 e0 ldi r16, 0x00 ; 0
26 14: 08 00 \.word 0x0008 ; \?\?\?\?
31 00000018 <__vec2_start>:
32 18: e1 e0 ldi r30, 0x01 ; 1
33 1a: f0 91 00 00 lds r31, 0x0000 ; 0x800000 <__data6\+0x7fff40>
34 1e: f0 93 00 00 sts 0x0000, r31 ; 0x800000 <__data6\+0x7fff40>
41 2e: af b6 in r10, 0x3f ; 63
42 30: af be out 0x3f, r10 ; 63
47 36: 00 e0 ldi r16, 0x00 ; 0
48 38: 0f 00 \.word 0x000f ; \?\?\?\?
53 0000003c <__vec3_start>:
55 3e: 1f b6 in r1, 0x3f ; 63
61 4a: 1f be out 0x3f, r1 ; 63
66 54: 1f be out 0x3f, r1 ; 63
73 5e: 00 e0 ldi r16, 0x00 ; 0
74 60: 11 00 \.word 0x0011 ; \?\?\?\?
79 00000064 <__vec4_start>:
81 66: 0f b6 in r0, 0x3f ; 63
89 76: 0f be out 0x3f, r0 ; 63
95 82: 0f be out 0x3f, r0 ; 63
98 88: 01 9f mul r16, r17
102 8c: 00 e0 ldi r16, 0x00 ; 0
103 8e: 14 00 \.word 0x0014 ; \?\?\?\?
108 00000092 <__vec5_start>:
118 a0: 00 e0 ldi r16, 0x00 ; 0
119 a2: 07 00 \.word 0x0007 ; \?\?\?\?
124 000000a6 <__vec6_start>:
126 a8: af b7 in r26, 0x3f ; 63
129 ae: af bf out 0x3f, r26 ; 63
133 b6: af bf out 0x3f, r26 ; 63
140 c0: 00 e0 ldi r16, 0x00 ; 0
141 c2: 0d 00 \.word 0x000d ; \?\?\?\?