[ARC] Don't allow pc-rel relocations for J* instructions.
[deliverable/binutils-gdb.git] / gas / testsuite / gas / cris / rd-v10_32o-2.d
1 #as: --underscore --em=criself --march=common_v10_v32
2 #objdump: -dr
3
4 # Check that branch offsets are computed as for v32. The
5 # compiler is supposed to generate four nop-type insns after
6 # every label to make sure the offset-by-2 or 4 doesn't matter.
7
8 .*: file format elf32-us-cris
9
10 Disassembly of section \.text:
11
12 00000000 <a>:
13 0: ffed ff7f ba .*
14 4: 0000 bcc \.\+2
15 \.\.\.
16
17 00007fff <b1>:
18 7fff: ffed 0201 ba .*
19 8003: fee0 ba .*
20 8005: 0000 bcc \.\+2
21 \.\.\.
22
23 00008101 <b2>:
24 \.\.\.
25 8201: 01e0 ba .*
26 8203: ffed fefe ba .*
27
28 00008207 <b3>:
29 \.\.\.
30 10203: ffed 0480 ba .*
31
32 00010207 <b4>:
33 10207: b005 setf
34
35 00010209 <aa>:
36 10209: ff3d ff7f beq .*
37 1020d: 0000 bcc \.\+2
38 \.\.\.
39
40 00018208 <bb1>:
41 18208: ff3d 0201 beq .*
42 1820c: fe30 beq .*
43 1820e: 0000 bcc \.\+2
44 \.\.\.
45
46 0001830a <bb2>:
47 \.\.\.
48 1840a: 0130 beq .*
49 1840c: ff3d fefe beq .*
50
51 00018410 <bb3>:
52 \.\.\.
53 2040c: ff3d 0480 beq .*
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