1 # D30V parallel optimization test
19 # one uses and one changes C flag
51 # should be serial because of conditional execution
76 # serial because of the r4 dependency
84 # serial because ld2w loads r5
88 # serial because ld2w loads r5
92 # parallel even though ld2w uses r6 and adds changes it
104 # parallel even though st2w uses r5 and adds modifies it
108 # parallel, both use but don't modify r5
112 # parallel even though st2w uses r6 and adds changes it
124 # test memory dependencies
126 # always serial because one could overwrite the other
134 # reads can happen in parallel but the current architecture
139 # test post increment and decrement dependencies
145 # parallel, modification to r6 happens last
161 # if the first instruction is a jmp, don't parallelize
176 # Explicitly prohibited from parallel execution.
177 # The labels are here to prevent instruction pairs
178 # from being merged with following pairs.
185 subhllh r10, r11, r12
187 ld2w r14, @(r14, r15)
188 mulhxhl r16, r17, r18
196 # Insertion of NOPs required to prevent pipeline clashes.
207 ldw r10, @(r11, r0) <- mul r7,r8,r9
209 mul r12,r13,r14 -> ldw r15, @(r16, r0)
214 ldw r10, @(r11, r0) <- mac0 r7,r8,r9