gas/testsuite/gas/m32r/m32r2.d

   1 #as: -m32r2
   2 #objdump: -dr
   3 #name: m32r2
   4
   5 .*: +file format .*
   6
   7 Disassembly of section .text:
   8
   9 0+0000 <setpsw>:
  10    0:   71 c1 71 ff     setpsw #0xc1 -> setpsw #0xff
  11
  12 0+0004 <clrpsw>:
  13    4:   72 c1 72 ff     clrpsw #0xc1 -> clrpsw #0xff
  14
  15 0+0008 <bset>:
  16    8:   a0 61 00 04     bset #0x0,@\(4,r1\)
  17    c:   a1 61 00 04     bset #0x1,@\(4,r1\)
  18   10:   a7 61 00 04     bset #0x7,@\(4,r1\)
  19
  20 0+0014 <bclr>:
  21   14:   a0 71 00 04     bclr #0x0,@\(4,r1\)
  22   18:   a1 71 00 04     bclr #0x1,@\(4,r1\)
  23   1c:   a7 71 00 04     bclr #0x7,@\(4,r1\)
  24
  25 0+0020 <btst>:
  26   20:   00 fd 01 fd     btst #0x0,fp -> btst #0x1,fp
  27   24:   07 fd f0 00     btst #0x7,fp \|\| nop
  28   28:   01 fd 90 82     btst #0x1,fp \|\| mv r0,r2
  29   2c:   01 fd 90 82     btst #0x1,fp \|\| mv r0,r2
  30
  31 0+0030 <divuh>:
  32   30:   9d 1d 00 10     divuh fp,fp
  33
  34 0+0034 <divb>:
  35   34:   9d 0d 00 18     divb fp,fp
  36
  37 0+0038 <divub>:
  38   38:   9d 1d 00 18     divub fp,fp
  39
  40 0+003c <remh>:
  41   3c:   9d 2d 00 10     remh fp,fp
  42
  43 0+0040 <remuh>:
  44   40:   9d 3d 00 10     remuh fp,fp
  45
  46 0+0044 <remb>:
  47   44:   9d 2d 00 18     remb fp,fp
  48
  49 0+0048 <remub>:
  50   48:   9d 3d 00 18     remub fp,fp
  51
  52 0+004c <sll>:
  53   4c:   10 41 92 43     sll r0,r1 \|\| sll r2,r3
  54   50:   12 43 90 61     sll r2,r3 \|\| mul r0,r1
  55   54:   10 41 92 63     sll r0,r1 \|\| mul r2,r3
  56   58:   60 01 92 43     ldi r0,#1 \|\| sll r2,r3
  57   5c:   10 41 e2 01     sll r0,r1 \|\| ldi r2,#1
  58
  59 0+0060 <slli>:
  60   60:   50 41 d2 5f     slli r0,#0x1 \|\| slli r2,#0x1f
  61   64:   52 5f 90 61     slli r2,#0x1f \|\| mul r0,r1
  62   68:   50 41 92 63     slli r0,#0x1 \|\| mul r2,r3
  63   6c:   60 01 d2 5f     ldi r0,#1 \|\| slli r2,#0x1f
  64   70:   50 41 e2 01     slli r0,#0x1 \|\| ldi r2,#1
  65
  66 0+0074 <sra>:
  67   74:   10 21 92 23     sra r0,r1 \|\| sra r2,r3
  68   78:   12 23 90 61     sra r2,r3 \|\| mul r0,r1
  69   7c:   10 21 92 63     sra r0,r1 \|\| mul r2,r3
  70   80:   60 01 92 23     ldi r0,#1 \|\| sra r2,r3
  71   84:   10 21 e2 01     sra r0,r1 \|\| ldi r2,#1
  72
  73 0+0088 <srai>:
  74   88:   50 21 d2 3f     srai r0,#0x1 \|\| srai r2,#0x1f
  75   8c:   52 3f 90 61     srai r2,#0x1f \|\| mul r0,r1
  76   90:   50 21 92 63     srai r0,#0x1 \|\| mul r2,r3
  77   94:   60 01 d2 3f     ldi r0,#1 \|\| srai r2,#0x1f
  78   98:   50 21 e2 01     srai r0,#0x1 \|\| ldi r2,#1
  79
  80 0+009c <srl>:
  81   9c:   10 01 92 03     srl r0,r1 \|\| srl r2,r3
  82   a0:   12 03 90 61     srl r2,r3 \|\| mul r0,r1
  83   a4:   10 01 92 63     srl r0,r1 \|\| mul r2,r3
  84   a8:   60 01 92 03     ldi r0,#1 \|\| srl r2,r3
  85   ac:   10 01 e2 01     srl r0,r1 \|\| ldi r2,#1
  86
  87 0+00b0 <srli>:
  88   b0:   50 01 d2 1f     srli r0,#0x1 \|\| srli r2,#0x1f
  89   b4:   52 1f 90 61     srli r2,#0x1f \|\| mul r0,r1
  90   b8:   50 01 92 63     srli r0,#0x1 \|\| mul r2,r3
  91   bc:   60 01 d2 1f     ldi r0,#1 \|\| srli r2,#0x1f
  92   c0:   50 01 e2 01     srli r0,#0x1 \|\| ldi r2,#1