1 #objdump: -dz --prefix-addresses -m mips:4120
2 #as: -32 -march=vr4120 -mfix-vr4120
3 #name: MIPS vr4120 workarounds
5 .*: +file format .*mips.*
7 Disassembly of section .text:
8 .* <[^>]*> macc a0,a1,a2
10 .* <[^>]*> div zero,a3,t0
11 .* <[^>]*> or a0,a0,a1
12 .* <[^>]*> dmacc a0,a1,a2
14 .* <[^>]*> div zero,a3,t0
15 .* <[^>]*> or a0,a0,a1
16 .* <[^>]*> macc a0,a1,a2
18 .* <[^>]*> divu zero,a3,t0
19 .* <[^>]*> or a0,a0,a1
20 .* <[^>]*> dmacc a0,a1,a2
22 .* <[^>]*> divu zero,a3,t0
23 .* <[^>]*> or a0,a0,a1
24 .* <[^>]*> macc a0,a1,a2
26 .* <[^>]*> ddiv zero,a3,t0
27 .* <[^>]*> or a0,a0,a1
28 .* <[^>]*> dmacc a0,a1,a2
30 .* <[^>]*> ddiv zero,a3,t0
31 .* <[^>]*> or a0,a0,a1
32 .* <[^>]*> macc a0,a1,a2
34 .* <[^>]*> ddivu zero,a3,t0
35 .* <[^>]*> or a0,a0,a1
36 .* <[^>]*> dmacc a0,a1,a2
38 .* <[^>]*> ddivu zero,a3,t0
39 .* <[^>]*> or a0,a0,a1
40 .* <[^>]*> dmult a0,a1
42 .* <[^>]*> dmult a2,a3
43 .* <[^>]*> or a0,a0,a1
44 .* <[^>]*> dmultu a0,a1
46 .* <[^>]*> dmultu a2,a3
47 .* <[^>]*> or a0,a0,a1
48 .* <[^>]*> dmacc a0,a1,a2
50 .* <[^>]*> dmacc a2,a3,t0
51 .* <[^>]*> or a0,a0,a1
52 .* <[^>]*> dmult a0,a1
54 .* <[^>]*> dmacc a2,a3,t0
55 .* <[^>]*> or a0,a0,a1
56 .* <[^>]*> macc a0,a1,a2
59 .* <[^>]*> dmacc a0,a1,a2
62 .* <[^>]*> macc a0,a1,a2
65 .* <[^>]*> dmacc a0,a1,a2
71 .* <[^>]*> macc a0,a1,a2
74 .* <[^>]*> or a0,a0,a1
76 .* <[^>]*> macc a0,a1,a2
78 .* <[^>]*> multu a0,a1
79 .* <[^>]*> or a0,a0,a1
81 .* <[^>]*> macc a0,a1,a2
83 .* <[^>]*> dmult a0,a1
84 .* <[^>]*> or a0,a0,a1
86 .* <[^>]*> macc a0,a1,a2
88 .* <[^>]*> dmultu a0,a1
89 .* <[^>]*> or a0,a0,a1
91 .* <[^>]*> dmacc a0,a1,a2
94 .* <[^>]*> or a0,a0,a1
96 .* <[^>]*> dmacc a0,a1,a2
98 .* <[^>]*> multu a0,a1
99 .* <[^>]*> or a0,a0,a1
101 .* <[^>]*> dmacc a0,a1,a2
103 .* <[^>]*> dmult a0,a1
104 .* <[^>]*> or a0,a0,a1
106 .* <[^>]*> dmacc a0,a1,a2
108 .* <[^>]*> dmultu a0,a1
109 .* <[^>]*> or a0,a0,a1
113 .* <[^>]*> dmult a0,a1
115 .* <[^>]*> macc a0,a1,a2
116 .* <[^>]*> or a0,a0,a1
118 .* <[^>]*> dmultu a0,a1
120 .* <[^>]*> macc a0,a1,a2
121 .* <[^>]*> or a0,a0,a1
123 .* <[^>]*> div zero,a0,a1
125 .* <[^>]*> macc a0,a1,a2
126 .* <[^>]*> or a0,a0,a1
128 .* <[^>]*> divu zero,a0,a1
130 .* <[^>]*> macc a0,a1,a2
131 .* <[^>]*> or a0,a0,a1
133 .* <[^>]*> ddiv zero,a0,a1
135 .* <[^>]*> macc a0,a1,a2
136 .* <[^>]*> or a0,a0,a1
138 .* <[^>]*> ddivu zero,a0,a1
140 .* <[^>]*> macc a0,a1,a2
141 .* <[^>]*> or a0,a0,a1
143 .* <[^>]*> dmult a0,a1
145 .* <[^>]*> dmacc a0,a1,a2
146 .* <[^>]*> or a0,a0,a1
148 .* <[^>]*> dmultu a0,a1
150 .* <[^>]*> dmacc a0,a1,a2
151 .* <[^>]*> or a0,a0,a1
153 .* <[^>]*> div zero,a0,a1
155 .* <[^>]*> dmacc a0,a1,a2
156 .* <[^>]*> or a0,a0,a1
158 .* <[^>]*> divu zero,a0,a1
160 .* <[^>]*> dmacc a0,a1,a2
161 .* <[^>]*> or a0,a0,a1
163 .* <[^>]*> ddiv zero,a0,a1
165 .* <[^>]*> dmacc a0,a1,a2
166 .* <[^>]*> or a0,a0,a1
168 .* <[^>]*> ddivu zero,a0,a1
170 .* <[^>]*> dmacc a0,a1,a2
171 .* <[^>]*> or a0,a0,a1