5 /* Integer instructions. */
27 dror $4,$5,57 /* Should expand to dror32 $4,$5,25. */
32 /* Prefetch instructions. */
33 # We don't test pref because currently the disassembler will
34 # disassemble it as lwc3. lwc3 is correct for mips1 to mips3,
35 # while pref is correct for mips4. Unfortunately, the
36 # disassembler does not know which architecture it is
42 /* Debug instructions. */
49 /* Coprocessor 0 instructions, minus standard ISA 3 ones.
50 That leaves just the performance monitoring registers. */
57 /* Miscellaneous instructions. */
60 wait 0 # disassembles without code
76 /* Align to 16-byte boundary. */