4 .*: +file format elf32-powerpc
6 Disassembly of section \.text:
14 c: 48 00 00 04 b 10 <apfour>
17 10: 48 00 00 08 b 18 <apfour\+0x8>
18 14: 48 00 00 00 b 14 <apfour\+0x4>
20 18: 48 00 00 04 b 1c <apfour\+0xc>
21 18: R_PPC_REL24 \.data\+0x4
22 1c: 48 00 00 00 b 1c <apfour\+0xc>
24 20: 48 00 00 14 b 34 <apfour\+0x24>
25 20: R_PPC_REL24 z\+0x14
26 24: 48 00 00 04 b 28 <apfour\+0x18>
27 28: 48 00 00 00 b 28 <apfour\+0x18>
29 2c: 4b ff ff e4 b 10 <apfour>
30 30: 48 00 00 04 b 34 <apfour\+0x24>
31 30: R_PPC_REL24 a\+0x4
32 34: 4b ff ff e0 b 14 <apfour\+0x4>
33 38: 48 00 00 00 b 38 <apfour\+0x28>
35 3c: 4b ff ff d4 b 10 <apfour>
37 40: 00 00 00 40 \.long 0x40
38 40: R_PPC_ADDR32 \.text\+0x40
40 44: 00 00 00 4c \.long 0x4c
41 44: R_PPC_ADDR32 \.text\+0x4c
42 48: 00 00 00 00 \.long 0x0
44 4c: 00 00 00 04 \.long 0x4
45 4c: R_PPC_REL32 x\+0x4
52 64: ff ff ff fc fnmsub f31,f31,f31,f31
53 64: R_PPC_ADDR32 x\+0xf+ffffffc
54 68: ff ff ff fc fnmsub f31,f31,f31,f31
55 68: R_PPC_ADDR32 y\+0xf+ffffffc
56 6c: ff ff ff fc fnmsub f31,f31,f31,f31
57 6c: R_PPC_ADDR32 z\+0xf+ffffffc
58 70: ff ff ff 9c \.long 0xffffff9c
59 74: ff ff ff 9c \.long 0xffffff9c
63 80: R_PPC_ADDR32 apfour
64 84: ff ff ff fc fnmsub f31,f31,f31,f31
65 88: 00 00 00 02 \.long 0x2
66 88: R_PPC_ADDR32 apfour\+0x2
67 8c: 00 00 00 00 \.long 0x0
68 Disassembly of section \.data:
71 0: 00 00 00 00 \.long 0x0
74 4: 00 00 00 00 \.long 0x0