5 .global _opcodes, _opcodes_end
11 add *ar0+, a ; Smem, src
12 add *ar1+, ts, a ; Smem, TS, src
13 add *ar2+, 16, a ; Smem, 16, src [,dst]
14 add *ar3+, a, b ; Smem [,SHIFT], src [,dst] (-16<=SHIFT<=15)
16 add *ar4+, 1, a ; Xmem, SHFT, src (0<=SHFT<=15)
17 add *ar3+, *ar4+, a ; Xmem, Ymem, dst
18 add #-32768, a ; #lk [,SHFT], src [,dst] (-32768<=lk<=32767)
20 add #0,16,a,b ; #lk, 16, src, [,dst]
22 add a,-16,b ; src [,SHIFT][,dst]
23 add a,asm,b ; src, ASM [,dst]
28 and *ar3+,a ; Smem,src
29 and #1,1,a,b ; #lk[,SHFT],src[,dst]
31 and #1,#16,a,b ; #lk,16,src[,dst]
33 and a ; src[,SHIFT][,dst]
47 banz _opcodes_end,*ar1+
49 banzd _opcodes_end,*ar2+
53 bc _opcodes_end, AEQ,AOV
55 bcd _opcodes_end, BIO,C,TC
95 firs *ar3+,*ar4+,_opcodes_end
100 ld *ar0+,a ; Smem,dst
101 ld *ar1+,ts,a ; Smem,TS,dst
102 ld *ar2+,16,a ; Smem,16,dst
103 ld *ar3+,1,a ; Smem[,SHIFT],dst
105 ld *ar4+,1,a ; Xmem,SHFT,dst
107 ld #32767,1,a ; #lk,[,SHFT],dst
109 ld #32767,16,a ; #lk,16,dst
111 ld a,asm,b ; src,ASM[,dst]
112 ld a,1,b ; src[,SHIFT],dst
115 ld #_opcodes_end,dp ; FIXME try to print label on disasm
116 ; note: TI assembler doesn't shift
117 ; the address encoding.
122 ld *ar2+,a || mac *ar3+,b ; single-line parallell
123 ld *ar4+,b || macr *ar5+,a ; with optional DST_ specified
124 ld *ar2+,a ; double-line parallel
126 ld *ar4+,b ; parallel spans
141 maca *ar1+ ; *ar6+,b (valid)
143 macd *ar2+,_opcodes_end,a
145 macp *ar3+,_opcodes_end,a
153 masa *ar6+ ; *ar6+,b (valid)
172 mvdp *ar6+,_opcodes_end
179 mvpd _opcodes_end,*ar3+