1 /* Native-dependent code for GNU/Linux AArch64.
3 Copyright (C) 2011-2013 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "linux-nat.h"
27 #include "target-descriptions.h"
30 #include "aarch64-tdep.h"
31 #include "aarch64-linux-tdep.h"
32 #include "elf/common.h"
34 #include <sys/ptrace.h>
35 #include <sys/utsname.h>
39 #include "features/aarch64.c"
41 /* Defines ps_err_e, struct ps_prochandle. */
42 #include "gdb_proc_service.h"
45 #define TRAP_HWBKPT 0x0004
48 /* On GNU/Linux, threads are implemented as pseudo-processes, in which
49 case we may be tracing more than one process at a time. In that
50 case, inferior_ptid will contain the main process ID and the
51 individual thread (process) ID. get_thread_id () is used to get
52 the thread id if it's available, and the process id otherwise. */
55 get_thread_id (ptid_t ptid
)
57 int tid
= ptid_get_lwp (ptid
);
60 tid
= ptid_get_pid (ptid
);
64 /* Macro definitions, data structures, and code for the hardware
65 breakpoint and hardware watchpoint support follow. We use the
66 following abbreviations throughout the code:
72 /* Maximum number of hardware breakpoint and watchpoint registers.
73 Neither of these values may exceed the width of dr_changed_t
76 #define AARCH64_HBP_MAX_NUM 16
77 #define AARCH64_HWP_MAX_NUM 16
79 /* Alignment requirement in bytes for addresses written to
80 hardware breakpoint and watchpoint value registers.
82 A ptrace call attempting to set an address that does not meet the
83 alignment criteria will fail. Limited support has been provided in
84 this port for unaligned watchpoints, such that from a GDB user
85 perspective, an unaligned watchpoint may be requested.
87 This is achieved by minimally enlarging the watched area to meet the
88 alignment requirement, and if necessary, splitting the watchpoint
89 over several hardware watchpoint registers. */
91 #define AARCH64_HBP_ALIGNMENT 4
92 #define AARCH64_HWP_ALIGNMENT 8
94 /* The maximum length of a memory region that can be watched by one
95 hardware watchpoint register. */
97 #define AARCH64_HWP_MAX_LEN_PER_REG 8
99 /* ptrace hardware breakpoint resource info is formatted as follows:
102 +---------------+--------------+---------------+---------------+
103 | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
104 +---------------+--------------+---------------+---------------+ */
107 /* Macros to extract fields from the hardware debug information word. */
108 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
109 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
111 /* Macro for the expected version of the ARMv8-A debug architecture. */
112 #define AARCH64_DEBUG_ARCH_V8 0x6
114 /* Number of hardware breakpoints/watchpoints the target supports.
115 They are initialized with values obtained via the ptrace calls
116 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
118 static int aarch64_num_bp_regs
;
119 static int aarch64_num_wp_regs
;
121 /* Debugging of hardware breakpoint/watchpoint support. */
123 static int debug_hw_points
;
125 /* Each bit of a variable of this type is used to indicate whether a
126 hardware breakpoint or watchpoint setting has been changed since
129 Bit N corresponds to the Nth hardware breakpoint or watchpoint
130 setting which is managed in aarch64_debug_reg_state, where N is
131 valid between 0 and the total number of the hardware breakpoint or
132 watchpoint debug registers minus 1.
134 When bit N is 1, the corresponding breakpoint or watchpoint setting
135 has changed, and therefore the corresponding hardware debug
136 register needs to be updated via the ptrace interface.
138 In the per-thread arch-specific data area, we define two such
139 variables for per-thread hardware breakpoint and watchpoint
140 settings respectively.
142 This type is part of the mechanism which helps reduce the number of
143 ptrace calls to the kernel, i.e. avoid asking the kernel to write
144 to the debug registers with unchanged values. */
146 typedef unsigned LONGEST dr_changed_t
;
148 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
150 #define DR_MARK_ALL_CHANGED(x, m) \
153 gdb_assert (sizeof ((x)) * 8 >= (m)); \
154 (x) = (((dr_changed_t)1 << (m)) - 1); \
157 #define DR_MARK_N_CHANGED(x, n) \
160 (x) |= ((dr_changed_t)1 << (n)); \
163 #define DR_CLEAR_CHANGED(x) \
169 #define DR_HAS_CHANGED(x) ((x) != 0)
170 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
172 /* Structure for managing the hardware breakpoint/watchpoint resources.
173 DR_ADDR_* stores the address, DR_CTRL_* stores the control register
174 content, and DR_REF_COUNT_* counts the numbers of references to the
175 corresponding bp/wp, by which way the limited hardware resources
176 are not wasted on duplicated bp/wp settings (though so far gdb has
177 done a good job by not sending duplicated bp/wp requests). */
179 struct aarch64_debug_reg_state
181 /* hardware breakpoint */
182 CORE_ADDR dr_addr_bp
[AARCH64_HBP_MAX_NUM
];
183 unsigned int dr_ctrl_bp
[AARCH64_HBP_MAX_NUM
];
184 unsigned int dr_ref_count_bp
[AARCH64_HBP_MAX_NUM
];
186 /* hardware watchpoint */
187 CORE_ADDR dr_addr_wp
[AARCH64_HWP_MAX_NUM
];
188 unsigned int dr_ctrl_wp
[AARCH64_HWP_MAX_NUM
];
189 unsigned int dr_ref_count_wp
[AARCH64_HWP_MAX_NUM
];
192 /* Per-process data. We don't bind this to a per-inferior registry
193 because of targets like x86 GNU/Linux that need to keep track of
194 processes that aren't bound to any inferior (e.g., fork children,
197 struct aarch64_process_info
200 struct aarch64_process_info
*next
;
202 /* The process identifier. */
205 /* Copy of aarch64 hardware debug registers. */
206 struct aarch64_debug_reg_state state
;
209 static struct aarch64_process_info
*aarch64_process_list
= NULL
;
211 /* Find process data for process PID. */
213 static struct aarch64_process_info
*
214 aarch64_find_process_pid (pid_t pid
)
216 struct aarch64_process_info
*proc
;
218 for (proc
= aarch64_process_list
; proc
; proc
= proc
->next
)
219 if (proc
->pid
== pid
)
225 /* Add process data for process PID. Returns newly allocated info
228 static struct aarch64_process_info
*
229 aarch64_add_process (pid_t pid
)
231 struct aarch64_process_info
*proc
;
233 proc
= xcalloc (1, sizeof (*proc
));
236 proc
->next
= aarch64_process_list
;
237 aarch64_process_list
= proc
;
242 /* Get data specific info for process PID, creating it if necessary.
243 Never returns NULL. */
245 static struct aarch64_process_info
*
246 aarch64_process_info_get (pid_t pid
)
248 struct aarch64_process_info
*proc
;
250 proc
= aarch64_find_process_pid (pid
);
252 proc
= aarch64_add_process (pid
);
257 /* Called whenever GDB is no longer debugging process PID. It deletes
258 data structures that keep track of debug register state. */
261 aarch64_forget_process (pid_t pid
)
263 struct aarch64_process_info
*proc
, **proc_link
;
265 proc
= aarch64_process_list
;
266 proc_link
= &aarch64_process_list
;
270 if (proc
->pid
== pid
)
272 *proc_link
= proc
->next
;
278 proc_link
= &proc
->next
;
283 /* Get debug registers state for process PID. */
285 static struct aarch64_debug_reg_state
*
286 aarch64_get_debug_reg_state (pid_t pid
)
288 return &aarch64_process_info_get (pid
)->state
;
291 /* Per-thread arch-specific data we want to keep. */
295 /* When bit N is 1, it indicates the Nth hardware breakpoint or
296 watchpoint register pair needs to be updated when the thread is
297 resumed; see aarch64_linux_prepare_to_resume. */
298 dr_changed_t dr_changed_bp
;
299 dr_changed_t dr_changed_wp
;
302 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
303 registers with data from *STATE. */
306 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state
*state
,
307 int tid
, int watchpoint
)
311 struct user_hwdebug_state regs
;
312 const CORE_ADDR
*addr
;
313 const unsigned int *ctrl
;
315 memset (®s
, 0, sizeof (regs
));
316 iov
.iov_base
= ®s
;
317 count
= watchpoint
? aarch64_num_wp_regs
: aarch64_num_bp_regs
;
318 addr
= watchpoint
? state
->dr_addr_wp
: state
->dr_addr_bp
;
319 ctrl
= watchpoint
? state
->dr_ctrl_wp
: state
->dr_ctrl_bp
;
322 iov
.iov_len
= (offsetof (struct user_hwdebug_state
, dbg_regs
[count
- 1])
323 + sizeof (regs
.dbg_regs
[count
- 1]));
325 for (i
= 0; i
< count
; i
++)
327 regs
.dbg_regs
[i
].addr
= addr
[i
];
328 regs
.dbg_regs
[i
].ctrl
= ctrl
[i
];
331 if (ptrace (PTRACE_SETREGSET
, tid
,
332 watchpoint
? NT_ARM_HW_WATCH
: NT_ARM_HW_BREAK
,
334 error (_("Unexpected error setting hardware debug registers"));
337 struct aarch64_dr_update_callback_param
343 /* Callback for iterate_over_lwps. Records the
344 information about the change of one hardware breakpoint/watchpoint
345 setting for the thread LWP.
346 The information is passed in via PTR.
347 N.B. The actual updating of hardware debug registers is not
348 carried out until the moment the thread is resumed. */
351 debug_reg_change_callback (struct lwp_info
*lwp
, void *ptr
)
353 struct aarch64_dr_update_callback_param
*param_p
354 = (struct aarch64_dr_update_callback_param
*) ptr
;
355 int pid
= get_thread_id (lwp
->ptid
);
356 int idx
= param_p
->idx
;
357 int is_watchpoint
= param_p
->is_watchpoint
;
358 struct arch_lwp_info
*info
= lwp
->arch_private
;
359 dr_changed_t
*dr_changed_ptr
;
360 dr_changed_t dr_changed
;
363 info
= lwp
->arch_private
= XCNEW (struct arch_lwp_info
);
367 fprintf_unfiltered (gdb_stdlog
,
368 "debug_reg_change_callback: \n\tOn entry:\n");
369 fprintf_unfiltered (gdb_stdlog
,
370 "\tpid%d, dr_changed_bp=0x%s, "
371 "dr_changed_wp=0x%s\n",
372 pid
, phex (info
->dr_changed_bp
, 8),
373 phex (info
->dr_changed_wp
, 8));
376 dr_changed_ptr
= is_watchpoint
? &info
->dr_changed_wp
377 : &info
->dr_changed_bp
;
378 dr_changed
= *dr_changed_ptr
;
381 && (idx
<= (is_watchpoint
? aarch64_num_wp_regs
382 : aarch64_num_bp_regs
)));
384 /* The actual update is done later just before resuming the lwp,
385 we just mark that one register pair needs updating. */
386 DR_MARK_N_CHANGED (dr_changed
, idx
);
387 *dr_changed_ptr
= dr_changed
;
389 /* If the lwp isn't stopped, force it to momentarily pause, so
390 we can update its debug registers. */
392 linux_stop_lwp (lwp
);
396 fprintf_unfiltered (gdb_stdlog
,
397 "\tOn exit:\n\tpid%d, dr_changed_bp=0x%s, "
398 "dr_changed_wp=0x%s\n",
399 pid
, phex (info
->dr_changed_bp
, 8),
400 phex (info
->dr_changed_wp
, 8));
403 /* Continue the iteration. */
407 /* Notify each thread that their IDXth breakpoint/watchpoint register
408 pair needs to be updated. The message will be recorded in each
409 thread's arch-specific data area, the actual updating will be done
410 when the thread is resumed. */
413 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state
*state
,
414 int is_watchpoint
, unsigned int idx
)
416 struct aarch64_dr_update_callback_param param
;
417 ptid_t pid_ptid
= pid_to_ptid (ptid_get_pid (inferior_ptid
));
419 param
.is_watchpoint
= is_watchpoint
;
422 iterate_over_lwps (pid_ptid
, debug_reg_change_callback
, (void *) ¶m
);
425 /* Print the values of the cached breakpoint/watchpoint registers. */
428 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state
*state
,
429 const char *func
, CORE_ADDR addr
,
434 fprintf_unfiltered (gdb_stdlog
, "%s", func
);
436 fprintf_unfiltered (gdb_stdlog
, " (addr=0x%08lx, len=%d, type=%s)",
437 (unsigned long) addr
, len
,
438 type
== hw_write
? "hw-write-watchpoint"
439 : (type
== hw_read
? "hw-read-watchpoint"
440 : (type
== hw_access
? "hw-access-watchpoint"
441 : (type
== hw_execute
? "hw-breakpoint"
443 fprintf_unfiltered (gdb_stdlog
, ":\n");
445 fprintf_unfiltered (gdb_stdlog
, "\tBREAKPOINTs:\n");
446 for (i
= 0; i
< aarch64_num_bp_regs
; i
++)
447 fprintf_unfiltered (gdb_stdlog
,
448 "\tBP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
449 i
, state
->dr_addr_bp
[i
],
450 state
->dr_ctrl_bp
[i
], state
->dr_ref_count_bp
[i
]);
452 fprintf_unfiltered (gdb_stdlog
, "\tWATCHPOINTs:\n");
453 for (i
= 0; i
< aarch64_num_wp_regs
; i
++)
454 fprintf_unfiltered (gdb_stdlog
,
455 "\tWP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
456 i
, state
->dr_addr_wp
[i
],
457 state
->dr_ctrl_wp
[i
], state
->dr_ref_count_wp
[i
]);
460 /* Fill GDB's register array with the general-purpose register values
461 from the current thread. */
464 fetch_gregs_from_thread (struct regcache
*regcache
)
470 tid
= get_thread_id (inferior_ptid
);
472 iovec
.iov_base
= ®s
;
473 iovec
.iov_len
= sizeof (regs
);
475 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_PRSTATUS
, &iovec
);
477 perror_with_name (_("Unable to fetch general registers."));
479 for (regno
= AARCH64_X0_REGNUM
; regno
<= AARCH64_CPSR_REGNUM
; regno
++)
480 regcache_raw_supply (regcache
, regno
,
481 (char *) ®s
[regno
- AARCH64_X0_REGNUM
]);
484 /* Store to the current thread the valid general-purpose register
485 values in the GDB's register array. */
488 store_gregs_to_thread (const struct regcache
*regcache
)
494 tid
= get_thread_id (inferior_ptid
);
496 iovec
.iov_base
= ®s
;
497 iovec
.iov_len
= sizeof (regs
);
499 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_PRSTATUS
, &iovec
);
501 perror_with_name (_("Unable to fetch general registers."));
503 for (regno
= AARCH64_X0_REGNUM
; regno
<= AARCH64_CPSR_REGNUM
; regno
++)
504 if (REG_VALID
== regcache_register_status (regcache
, regno
))
505 regcache_raw_collect (regcache
, regno
,
506 (char *) ®s
[regno
- AARCH64_X0_REGNUM
]);
508 ret
= ptrace (PTRACE_SETREGSET
, tid
, NT_PRSTATUS
, &iovec
);
510 perror_with_name (_("Unable to store general registers."));
513 /* Fill GDB's register array with the fp/simd register values
514 from the current thread. */
517 fetch_fpregs_from_thread (struct regcache
*regcache
)
523 tid
= get_thread_id (inferior_ptid
);
525 iovec
.iov_base
= ®s
;
526 iovec
.iov_len
= sizeof (regs
);
528 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_FPREGSET
, &iovec
);
530 perror_with_name (_("Unable to fetch FP/SIMD registers."));
532 for (regno
= AARCH64_V0_REGNUM
; regno
<= AARCH64_V31_REGNUM
; regno
++)
533 regcache_raw_supply (regcache
, regno
,
534 (char *) ®s
.vregs
[regno
- AARCH64_V0_REGNUM
]);
536 regcache_raw_supply (regcache
, AARCH64_FPSR_REGNUM
, (char *) ®s
.fpsr
);
537 regcache_raw_supply (regcache
, AARCH64_FPCR_REGNUM
, (char *) ®s
.fpcr
);
540 /* Store to the current thread the valid fp/simd register
541 values in the GDB's register array. */
544 store_fpregs_to_thread (const struct regcache
*regcache
)
550 tid
= get_thread_id (inferior_ptid
);
552 iovec
.iov_base
= ®s
;
553 iovec
.iov_len
= sizeof (regs
);
555 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_FPREGSET
, &iovec
);
557 perror_with_name (_("Unable to fetch FP/SIMD registers."));
559 for (regno
= AARCH64_V0_REGNUM
; regno
<= AARCH64_V31_REGNUM
; regno
++)
560 if (REG_VALID
== regcache_register_status (regcache
, regno
))
561 regcache_raw_collect (regcache
, regno
,
562 (char *) ®s
.vregs
[regno
- AARCH64_V0_REGNUM
]);
564 if (REG_VALID
== regcache_register_status (regcache
, AARCH64_FPSR_REGNUM
))
565 regcache_raw_collect (regcache
, AARCH64_FPSR_REGNUM
, (char *) ®s
.fpsr
);
566 if (REG_VALID
== regcache_register_status (regcache
, AARCH64_FPCR_REGNUM
))
567 regcache_raw_collect (regcache
, AARCH64_FPCR_REGNUM
, (char *) ®s
.fpcr
);
569 ret
= ptrace (PTRACE_SETREGSET
, tid
, NT_FPREGSET
, &iovec
);
571 perror_with_name (_("Unable to store FP/SIMD registers."));
574 /* Implement the "to_fetch_register" target_ops method. */
577 aarch64_linux_fetch_inferior_registers (struct target_ops
*ops
,
578 struct regcache
*regcache
,
583 fetch_gregs_from_thread (regcache
);
584 fetch_fpregs_from_thread (regcache
);
586 else if (regno
< AARCH64_V0_REGNUM
)
587 fetch_gregs_from_thread (regcache
);
589 fetch_fpregs_from_thread (regcache
);
592 /* Implement the "to_store_register" target_ops method. */
595 aarch64_linux_store_inferior_registers (struct target_ops
*ops
,
596 struct regcache
*regcache
,
601 store_gregs_to_thread (regcache
);
602 store_fpregs_to_thread (regcache
);
604 else if (regno
< AARCH64_V0_REGNUM
)
605 store_gregs_to_thread (regcache
);
607 store_fpregs_to_thread (regcache
);
610 /* Fill register REGNO (if it is a general-purpose register) in
611 *GREGSETPS with the value in GDB's register array. If REGNO is -1,
612 do this for all registers. */
615 fill_gregset (const struct regcache
*regcache
,
616 gdb_gregset_t
*gregsetp
, int regno
)
618 gdb_byte
*gregs_buf
= (gdb_byte
*) gregsetp
;
621 for (i
= AARCH64_X0_REGNUM
; i
<= AARCH64_CPSR_REGNUM
; i
++)
622 if (regno
== -1 || regno
== i
)
623 regcache_raw_collect (regcache
, i
,
624 gregs_buf
+ X_REGISTER_SIZE
625 * (i
- AARCH64_X0_REGNUM
));
628 /* Fill GDB's register array with the general-purpose register values
632 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
634 aarch64_linux_supply_gregset (regcache
, (const gdb_byte
*) gregsetp
);
637 /* Fill register REGNO (if it is a floating-point register) in
638 *FPREGSETP with the value in GDB's register array. If REGNO is -1,
639 do this for all registers. */
642 fill_fpregset (const struct regcache
*regcache
,
643 gdb_fpregset_t
*fpregsetp
, int regno
)
645 gdb_byte
*fpregs_buf
= (gdb_byte
*) fpregsetp
;
648 for (i
= AARCH64_V0_REGNUM
; i
<= AARCH64_V31_REGNUM
; i
++)
649 if (regno
== -1 || regno
== i
)
650 regcache_raw_collect (regcache
, i
,
651 fpregs_buf
+ V_REGISTER_SIZE
652 * (i
- AARCH64_V0_REGNUM
));
654 if (regno
== -1 || regno
== AARCH64_FPSR_REGNUM
)
655 regcache_raw_collect (regcache
, AARCH64_FPSR_REGNUM
,
656 fpregs_buf
+ V_REGISTER_SIZE
* 32);
658 if (regno
== -1 || regno
== AARCH64_FPCR_REGNUM
)
659 regcache_raw_collect (regcache
, AARCH64_FPCR_REGNUM
,
660 fpregs_buf
+ V_REGISTER_SIZE
* 32 + 4);
663 /* Fill GDB's register array with the floating-point register values
667 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
*fpregsetp
)
669 aarch64_linux_supply_fpregset (regcache
, (const gdb_byte
*) fpregsetp
);
672 /* Called when resuming a thread.
673 The hardware debug registers are updated when there is any change. */
676 aarch64_linux_prepare_to_resume (struct lwp_info
*lwp
)
678 struct arch_lwp_info
*info
= lwp
->arch_private
;
680 /* NULL means this is the main thread still going through the shell,
681 or, no watchpoint has been set yet. In that case, there's
686 if (DR_HAS_CHANGED (info
->dr_changed_bp
)
687 || DR_HAS_CHANGED (info
->dr_changed_wp
))
689 int tid
= ptid_get_lwp (lwp
->ptid
);
690 struct aarch64_debug_reg_state
*state
691 = aarch64_get_debug_reg_state (ptid_get_pid (lwp
->ptid
));
694 fprintf_unfiltered (gdb_stdlog
, "prepare_to_resume thread %d\n", tid
);
697 if (DR_HAS_CHANGED (info
->dr_changed_wp
))
699 aarch64_linux_set_debug_regs (state
, tid
, 1);
700 DR_CLEAR_CHANGED (info
->dr_changed_wp
);
704 if (DR_HAS_CHANGED (info
->dr_changed_bp
))
706 aarch64_linux_set_debug_regs (state
, tid
, 0);
707 DR_CLEAR_CHANGED (info
->dr_changed_bp
);
713 aarch64_linux_new_thread (struct lwp_info
*lp
)
715 struct arch_lwp_info
*info
= XCNEW (struct arch_lwp_info
);
717 /* Mark that all the hardware breakpoint/watchpoint register pairs
718 for this thread need to be initialized. */
719 DR_MARK_ALL_CHANGED (info
->dr_changed_bp
, aarch64_num_bp_regs
);
720 DR_MARK_ALL_CHANGED (info
->dr_changed_wp
, aarch64_num_wp_regs
);
722 lp
->arch_private
= info
;
725 /* linux_nat_new_fork hook. */
728 aarch64_linux_new_fork (struct lwp_info
*parent
, pid_t child_pid
)
731 struct aarch64_debug_reg_state
*parent_state
;
732 struct aarch64_debug_reg_state
*child_state
;
734 /* NULL means no watchpoint has ever been set in the parent. In
735 that case, there's nothing to do. */
736 if (parent
->arch_private
== NULL
)
739 /* GDB core assumes the child inherits the watchpoints/hw
740 breakpoints of the parent, and will remove them all from the
741 forked off process. Copy the debug registers mirrors into the
742 new process so that all breakpoints and watchpoints can be
745 parent_pid
= ptid_get_pid (parent
->ptid
);
746 parent_state
= aarch64_get_debug_reg_state (parent_pid
);
747 child_state
= aarch64_get_debug_reg_state (child_pid
);
748 *child_state
= *parent_state
;
752 /* Called by libthread_db. Returns a pointer to the thread local
753 storage (or its descriptor). */
756 ps_get_thread_area (const struct ps_prochandle
*ph
,
757 lwpid_t lwpid
, int idx
, void **base
)
762 iovec
.iov_base
= ®
;
763 iovec
.iov_len
= sizeof (reg
);
765 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
768 /* IDX is the bias from the thread pointer to the beginning of the
769 thread descriptor. It has to be subtracted due to implementation
770 quirks in libthread_db. */
771 *base
= (void *) (reg
- idx
);
777 /* Get the hardware debug register capacity information. */
780 aarch64_linux_get_debug_reg_capacity (void)
784 struct user_hwdebug_state dreg_state
;
786 tid
= get_thread_id (inferior_ptid
);
787 iov
.iov_base
= &dreg_state
;
788 iov
.iov_len
= sizeof (dreg_state
);
790 /* Get hardware watchpoint register info. */
791 if (ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_HW_WATCH
, &iov
) == 0
792 && AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
)
794 aarch64_num_wp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
795 if (aarch64_num_wp_regs
> AARCH64_HWP_MAX_NUM
)
797 warning (_("Unexpected number of hardware watchpoint registers"
798 " reported by ptrace, got %d, expected %d."),
799 aarch64_num_wp_regs
, AARCH64_HWP_MAX_NUM
);
800 aarch64_num_wp_regs
= AARCH64_HWP_MAX_NUM
;
805 warning (_("Unable to determine the number of hardware watchpoints"
807 aarch64_num_wp_regs
= 0;
810 /* Get hardware breakpoint register info. */
811 if (ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_HW_BREAK
, &iov
) == 0
812 && AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
)
814 aarch64_num_bp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
815 if (aarch64_num_bp_regs
> AARCH64_HBP_MAX_NUM
)
817 warning (_("Unexpected number of hardware breakpoint registers"
818 " reported by ptrace, got %d, expected %d."),
819 aarch64_num_bp_regs
, AARCH64_HBP_MAX_NUM
);
820 aarch64_num_bp_regs
= AARCH64_HBP_MAX_NUM
;
825 warning (_("Unable to determine the number of hardware breakpoints"
827 aarch64_num_bp_regs
= 0;
831 static void (*super_post_startup_inferior
) (ptid_t ptid
);
833 /* Implement the "to_post_startup_inferior" target_ops method. */
836 aarch64_linux_child_post_startup_inferior (ptid_t ptid
)
838 aarch64_forget_process (ptid_get_pid (ptid
));
839 aarch64_linux_get_debug_reg_capacity ();
840 super_post_startup_inferior (ptid
);
843 /* Implement the "to_read_description" target_ops method. */
845 static const struct target_desc
*
846 aarch64_linux_read_description (struct target_ops
*ops
)
848 initialize_tdesc_aarch64 ();
849 return tdesc_aarch64
;
852 /* Given the (potentially unaligned) watchpoint address in ADDR and
853 length in LEN, return the aligned address and aligned length in
854 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
855 aligned address and length will be valid values to write to the
856 hardware watchpoint value and control registers.
858 The given watchpoint may get truncated if more than one hardware
859 register is needed to cover the watched region. *NEXT_ADDR_P
860 and *NEXT_LEN_P, if non-NULL, will return the address and length
861 of the remaining part of the watchpoint (which can be processed
862 by calling this routine again to generate another aligned address
865 See the comment above the function of the same name in
866 gdbserver/linux-aarch64-low.c for more information. */
869 aarch64_align_watchpoint (CORE_ADDR addr
, int len
, CORE_ADDR
*aligned_addr_p
,
870 int *aligned_len_p
, CORE_ADDR
*next_addr_p
,
875 CORE_ADDR aligned_addr
;
876 const unsigned int alignment
= AARCH64_HWP_ALIGNMENT
;
877 const unsigned int max_wp_len
= AARCH64_HWP_MAX_LEN_PER_REG
;
879 /* As assumed by the algorithm. */
880 gdb_assert (alignment
== max_wp_len
);
885 /* Address to be put into the hardware watchpoint value register
887 offset
= addr
& (alignment
- 1);
888 aligned_addr
= addr
- offset
;
890 gdb_assert (offset
>= 0 && offset
< alignment
);
891 gdb_assert (aligned_addr
>= 0 && aligned_addr
<= addr
);
892 gdb_assert (offset
+ len
> 0);
894 if (offset
+ len
>= max_wp_len
)
896 /* Need more than one watchpoint registers; truncate it at the
897 alignment boundary. */
898 aligned_len
= max_wp_len
;
899 len
-= (max_wp_len
- offset
);
900 addr
+= (max_wp_len
- offset
);
901 gdb_assert ((addr
& (alignment
- 1)) == 0);
905 /* Find the smallest valid length that is large enough to
906 accommodate this watchpoint. */
907 static const unsigned char
908 aligned_len_array
[AARCH64_HWP_MAX_LEN_PER_REG
] =
909 { 1, 2, 4, 4, 8, 8, 8, 8 };
911 aligned_len
= aligned_len_array
[offset
+ len
- 1];
917 *aligned_addr_p
= aligned_addr
;
919 *aligned_len_p
= aligned_len
;
926 /* Returns the number of hardware watchpoints of type TYPE that we can
927 set. Value is positive if we can set CNT watchpoints, zero if
928 setting watchpoints of type TYPE is not supported, and negative if
929 CNT is more than the maximum number of watchpoints of type TYPE
930 that we can support. TYPE is one of bp_hardware_watchpoint,
931 bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint.
932 CNT is the number of such watchpoints used so far (including this
933 one). OTHERTYPE is non-zero if other types of watchpoints are
936 We always return 1 here because we don't have enough information
937 about possible overlap of addresses that they want to watch. As an
938 extreme example, consider the case where all the watchpoints watch
939 the same address and the same region length: then we can handle a
940 virtually unlimited number of watchpoints, due to debug register
941 sharing implemented via reference counts. */
944 aarch64_linux_can_use_hw_breakpoint (int type
, int cnt
, int othertype
)
949 /* ptrace expects control registers to be formatted as follows:
952 +--------------------------------+----------+------+------+----+
953 | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
954 +--------------------------------+----------+------+------+----+
956 The TYPE field is ignored for breakpoints. */
958 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
959 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
961 /* Utility function that returns the length in bytes of a watchpoint
962 according to the content of a hardware debug control register CTRL.
963 Note that the kernel currently only supports the following Byte
964 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
965 that for a hardware watchpoint, its valid length can only be 1
966 byte, 2 bytes, 4 bytes or 8 bytes. */
968 static inline unsigned int
969 aarch64_watchpoint_length (unsigned int ctrl
)
971 switch (DR_CONTROL_LENGTH (ctrl
))
986 /* Given the hardware breakpoint or watchpoint type TYPE and its
987 length LEN, return the expected encoding for a hardware
988 breakpoint/watchpoint control register. */
991 aarch64_point_encode_ctrl_reg (int type
, int len
)
993 unsigned int ctrl
, ttype
;
1011 perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
1015 /* length bitmask */
1016 ctrl
|= ((1 << len
) - 1) << 5;
1017 /* enabled at el0 */
1018 ctrl
|= (2 << 1) | 1;
1023 /* Addresses to be written to the hardware breakpoint and watchpoint
1024 value registers need to be aligned; the alignment is 4-byte and
1025 8-type respectively. Linux kernel rejects any non-aligned address
1026 it receives from the related ptrace call. Furthermore, the kernel
1027 currently only supports the following Byte Address Select (BAS)
1028 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
1029 watchpoint to be accepted by the kernel (via ptrace call), its
1030 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
1031 Despite these limitations, the unaligned watchpoint is supported in
1034 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
1037 aarch64_point_is_aligned (int is_watchpoint
, CORE_ADDR addr
, int len
)
1039 unsigned int alignment
= is_watchpoint
? AARCH64_HWP_ALIGNMENT
1040 : AARCH64_HBP_ALIGNMENT
;
1042 if (addr
& (alignment
- 1))
1045 if (len
!= 8 && len
!= 4 && len
!= 2 && len
!= 1)
1051 /* Record the insertion of one breakpoint/watchpoint, as represented
1052 by ADDR and CTRL, in the cached debug register state area *STATE. */
1055 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state
*state
,
1056 int type
, CORE_ADDR addr
, int len
)
1058 int i
, idx
, num_regs
, is_watchpoint
;
1059 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
1060 CORE_ADDR
*dr_addr_p
;
1062 /* Set up state pointers. */
1063 is_watchpoint
= (type
!= hw_execute
);
1064 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
1067 num_regs
= aarch64_num_wp_regs
;
1068 dr_addr_p
= state
->dr_addr_wp
;
1069 dr_ctrl_p
= state
->dr_ctrl_wp
;
1070 dr_ref_count
= state
->dr_ref_count_wp
;
1074 num_regs
= aarch64_num_bp_regs
;
1075 dr_addr_p
= state
->dr_addr_bp
;
1076 dr_ctrl_p
= state
->dr_ctrl_bp
;
1077 dr_ref_count
= state
->dr_ref_count_bp
;
1080 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
1082 /* Find an existing or free register in our cache. */
1084 for (i
= 0; i
< num_regs
; ++i
)
1086 if ((dr_ctrl_p
[i
] & 1) == 0)
1088 gdb_assert (dr_ref_count
[i
] == 0);
1090 /* no break; continue hunting for an existing one. */
1092 else if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
1094 gdb_assert (dr_ref_count
[i
] != 0);
1104 /* Update our cache. */
1105 if ((dr_ctrl_p
[idx
] & 1) == 0)
1108 dr_addr_p
[idx
] = addr
;
1109 dr_ctrl_p
[idx
] = ctrl
;
1110 dr_ref_count
[idx
] = 1;
1111 /* Notify the change. */
1112 aarch64_notify_debug_reg_change (state
, is_watchpoint
, idx
);
1116 /* existing entry */
1117 dr_ref_count
[idx
]++;
1123 /* Record the removal of one breakpoint/watchpoint, as represented by
1124 ADDR and CTRL, in the cached debug register state area *STATE. */
1127 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state
*state
,
1128 int type
, CORE_ADDR addr
, int len
)
1130 int i
, num_regs
, is_watchpoint
;
1131 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
1132 CORE_ADDR
*dr_addr_p
;
1134 /* Set up state pointers. */
1135 is_watchpoint
= (type
!= hw_execute
);
1136 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
1139 num_regs
= aarch64_num_wp_regs
;
1140 dr_addr_p
= state
->dr_addr_wp
;
1141 dr_ctrl_p
= state
->dr_ctrl_wp
;
1142 dr_ref_count
= state
->dr_ref_count_wp
;
1146 num_regs
= aarch64_num_bp_regs
;
1147 dr_addr_p
= state
->dr_addr_bp
;
1148 dr_ctrl_p
= state
->dr_ctrl_bp
;
1149 dr_ref_count
= state
->dr_ref_count_bp
;
1152 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
1154 /* Find the entry that matches the ADDR and CTRL. */
1155 for (i
= 0; i
< num_regs
; ++i
)
1156 if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
1158 gdb_assert (dr_ref_count
[i
] != 0);
1166 /* Clear our cache. */
1167 if (--dr_ref_count
[i
] == 0)
1169 /* Clear the enable bit. */
1172 dr_ctrl_p
[i
] = ctrl
;
1173 /* Notify the change. */
1174 aarch64_notify_debug_reg_change (state
, is_watchpoint
, i
);
1180 /* Implement insertion and removal of a single breakpoint. */
1183 aarch64_handle_breakpoint (int type
, CORE_ADDR addr
, int len
, int is_insert
)
1185 struct aarch64_debug_reg_state
*state
;
1187 /* The hardware breakpoint on AArch64 should always be 4-byte
1189 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr
, len
))
1192 state
= aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid
));
1195 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
1197 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
1200 /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address.
1201 Return 0 on success, -1 on failure. */
1204 aarch64_linux_insert_hw_breakpoint (struct gdbarch
*gdbarch
,
1205 struct bp_target_info
*bp_tgt
)
1208 CORE_ADDR addr
= bp_tgt
->placed_address
;
1210 const int type
= hw_execute
;
1212 if (debug_hw_points
)
1215 "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
1216 (unsigned long) addr
, len
);
1218 ret
= aarch64_handle_breakpoint (type
, addr
, len
, 1 /* is_insert */);
1220 if (debug_hw_points
> 1)
1222 struct aarch64_debug_reg_state
*state
1223 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid
));
1225 aarch64_show_debug_reg_state (state
,
1226 "insert_hw_watchpoint", addr
, len
, type
);
1232 /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address.
1233 Return 0 on success, -1 on failure. */
1236 aarch64_linux_remove_hw_breakpoint (struct gdbarch
*gdbarch
,
1237 struct bp_target_info
*bp_tgt
)
1240 CORE_ADDR addr
= bp_tgt
->placed_address
;
1242 const int type
= hw_execute
;
1244 if (debug_hw_points
)
1246 (gdb_stdlog
, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
1247 (unsigned long) addr
, len
);
1249 ret
= aarch64_handle_breakpoint (type
, addr
, len
, 0 /* is_insert */);
1251 if (debug_hw_points
> 1)
1253 struct aarch64_debug_reg_state
*state
1254 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid
));
1256 aarch64_show_debug_reg_state (state
,
1257 "remove_hw_watchpoint", addr
, len
, type
);
1263 /* This is essentially the same as aarch64_handle_breakpoint, apart
1264 from that it is an aligned watchpoint to be handled. */
1267 aarch64_handle_aligned_watchpoint (int type
, CORE_ADDR addr
, int len
,
1270 struct aarch64_debug_reg_state
*state
1271 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid
));
1274 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
1276 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
1279 /* Insert/remove unaligned watchpoint by calling
1280 aarch64_align_watchpoint repeatedly until the whole watched region,
1281 as represented by ADDR and LEN, has been properly aligned and ready
1282 to be written to one or more hardware watchpoint registers.
1283 IS_INSERT indicates whether this is an insertion or a deletion.
1284 Return 0 if succeed. */
1287 aarch64_handle_unaligned_watchpoint (int type
, CORE_ADDR addr
, int len
,
1290 struct aarch64_debug_reg_state
*state
1291 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid
));
1295 CORE_ADDR aligned_addr
;
1296 int aligned_len
, ret
;
1298 aarch64_align_watchpoint (addr
, len
, &aligned_addr
, &aligned_len
,
1302 ret
= aarch64_dr_state_insert_one_point (state
, type
, aligned_addr
,
1305 ret
= aarch64_dr_state_remove_one_point (state
, type
, aligned_addr
,
1308 if (debug_hw_points
)
1309 fprintf_unfiltered (gdb_stdlog
,
1310 "handle_unaligned_watchpoint: is_insert: %d\n"
1311 " aligned_addr: 0x%08lx, aligned_len: %d\n"
1312 " next_addr: 0x%08lx, next_len: %d\n",
1313 is_insert
, aligned_addr
, aligned_len
, addr
, len
);
1322 /* Implements insertion and removal of a single watchpoint. */
1325 aarch64_handle_watchpoint (int type
, CORE_ADDR addr
, int len
, int is_insert
)
1327 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr
, len
))
1328 return aarch64_handle_aligned_watchpoint (type
, addr
, len
, is_insert
);
1330 return aarch64_handle_unaligned_watchpoint (type
, addr
, len
, is_insert
);
1333 /* Implement the "to_insert_watchpoint" target_ops method.
1335 Insert a watchpoint to watch a memory region which starts at
1336 address ADDR and whose length is LEN bytes. Watch memory accesses
1337 of the type TYPE. Return 0 on success, -1 on failure. */
1340 aarch64_linux_insert_watchpoint (CORE_ADDR addr
, int len
, int type
,
1341 struct expression
*cond
)
1345 if (debug_hw_points
)
1346 fprintf_unfiltered (gdb_stdlog
,
1347 "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n",
1348 (unsigned long) addr
, len
);
1350 gdb_assert (type
!= hw_execute
);
1352 ret
= aarch64_handle_watchpoint (type
, addr
, len
, 1 /* is_insert */);
1354 if (debug_hw_points
> 1)
1356 struct aarch64_debug_reg_state
*state
1357 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid
));
1359 aarch64_show_debug_reg_state (state
,
1360 "insert_watchpoint", addr
, len
, type
);
1366 /* Implement the "to_remove_watchpoint" target_ops method.
1367 Remove a watchpoint that watched the memory region which starts at
1368 address ADDR, whose length is LEN bytes, and for accesses of the
1369 type TYPE. Return 0 on success, -1 on failure. */
1372 aarch64_linux_remove_watchpoint (CORE_ADDR addr
, int len
, int type
,
1373 struct expression
*cond
)
1377 if (debug_hw_points
)
1378 fprintf_unfiltered (gdb_stdlog
,
1379 "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n",
1380 (unsigned long) addr
, len
);
1382 gdb_assert (type
!= hw_execute
);
1384 ret
= aarch64_handle_watchpoint (type
, addr
, len
, 0 /* is_insert */);
1386 if (debug_hw_points
> 1)
1388 struct aarch64_debug_reg_state
*state
1389 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid
));
1391 aarch64_show_debug_reg_state (state
,
1392 "remove_watchpoint", addr
, len
, type
);
1398 /* Implement the "to_region_ok_for_hw_watchpoint" target_ops method. */
1401 aarch64_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr
, int len
)
1403 CORE_ADDR aligned_addr
;
1405 /* Can not set watchpoints for zero or negative lengths. */
1409 /* Must have hardware watchpoint debug register(s). */
1410 if (aarch64_num_wp_regs
== 0)
1413 /* We support unaligned watchpoint address and arbitrary length,
1414 as long as the size of the whole watched area after alignment
1415 doesn't exceed size of the total area that all watchpoint debug
1416 registers can watch cooperatively.
1418 This is a very relaxed rule, but unfortunately there are
1419 limitations, e.g. false-positive hits, due to limited support of
1420 hardware debug registers in the kernel. See comment above
1421 aarch64_align_watchpoint for more information. */
1423 aligned_addr
= addr
& ~(AARCH64_HWP_MAX_LEN_PER_REG
- 1);
1424 if (aligned_addr
+ aarch64_num_wp_regs
* AARCH64_HWP_MAX_LEN_PER_REG
1428 /* All tests passed so we are likely to be able to set the watchpoint.
1429 The reason that it is 'likely' rather than 'must' is because
1430 we don't check the current usage of the watchpoint registers, and
1431 there may not be enough registers available for this watchpoint.
1432 Ideally we should check the cached debug register state, however
1433 the checking is costly. */
1437 /* Implement the "to_stopped_data_address" target_ops method. */
1440 aarch64_linux_stopped_data_address (struct target_ops
*target
,
1445 struct aarch64_debug_reg_state
*state
;
1447 if (!linux_nat_get_siginfo (inferior_ptid
, &siginfo
))
1450 /* This must be a hardware breakpoint. */
1451 if (siginfo
.si_signo
!= SIGTRAP
1452 || (siginfo
.si_code
& 0xffff) != TRAP_HWBKPT
)
1455 /* Check if the address matches any watched address. */
1456 state
= aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid
));
1457 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
1459 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
1460 const CORE_ADDR addr_trap
= (CORE_ADDR
) siginfo
.si_addr
;
1461 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
];
1463 if (state
->dr_ref_count_wp
[i
]
1464 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
1465 && addr_trap
>= addr_watch
1466 && addr_trap
< addr_watch
+ len
)
1468 *addr_p
= addr_trap
;
1476 /* Implement the "to_stopped_by_watchpoint" target_ops method. */
1479 aarch64_linux_stopped_by_watchpoint (void)
1483 return aarch64_linux_stopped_data_address (¤t_target
, &addr
);
1486 /* Implement the "to_watchpoint_addr_within_range" target_ops method. */
1489 aarch64_linux_watchpoint_addr_within_range (struct target_ops
*target
,
1491 CORE_ADDR start
, int length
)
1493 return start
<= addr
&& start
+ length
- 1 >= addr
;
1496 /* Define AArch64 maintenance commands. */
1499 add_show_debug_regs_command (void)
1501 /* A maintenance command to enable printing the internal DRi mirror
1503 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance
,
1504 &debug_hw_points
, _("\
1505 Set whether to show variables that mirror the AArch64 debug registers."), _("\
1506 Show whether to show variables that mirror the AArch64 debug registers."), _("\
1507 Use \"on\" to enable, \"off\" to disable.\n\
1508 If enabled, the debug registers values are shown when GDB inserts\n\
1509 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
1510 triggers a breakpoint or watchpoint."),
1513 &maintenance_set_cmdlist
,
1514 &maintenance_show_cmdlist
);
1517 /* -Wmissing-prototypes. */
1518 void _initialize_aarch64_linux_nat (void);
1521 _initialize_aarch64_linux_nat (void)
1523 struct target_ops
*t
;
1525 /* Fill in the generic GNU/Linux methods. */
1526 t
= linux_target ();
1528 add_show_debug_regs_command ();
1530 /* Add our register access methods. */
1531 t
->to_fetch_registers
= aarch64_linux_fetch_inferior_registers
;
1532 t
->to_store_registers
= aarch64_linux_store_inferior_registers
;
1534 t
->to_read_description
= aarch64_linux_read_description
;
1536 t
->to_can_use_hw_breakpoint
= aarch64_linux_can_use_hw_breakpoint
;
1537 t
->to_insert_hw_breakpoint
= aarch64_linux_insert_hw_breakpoint
;
1538 t
->to_remove_hw_breakpoint
= aarch64_linux_remove_hw_breakpoint
;
1539 t
->to_region_ok_for_hw_watchpoint
=
1540 aarch64_linux_region_ok_for_hw_watchpoint
;
1541 t
->to_insert_watchpoint
= aarch64_linux_insert_watchpoint
;
1542 t
->to_remove_watchpoint
= aarch64_linux_remove_watchpoint
;
1543 t
->to_stopped_by_watchpoint
= aarch64_linux_stopped_by_watchpoint
;
1544 t
->to_stopped_data_address
= aarch64_linux_stopped_data_address
;
1545 t
->to_watchpoint_addr_within_range
=
1546 aarch64_linux_watchpoint_addr_within_range
;
1548 /* Override the GNU/Linux inferior startup hook. */
1549 super_post_startup_inferior
= t
->to_post_startup_inferior
;
1550 t
->to_post_startup_inferior
= aarch64_linux_child_post_startup_inferior
;
1552 /* Register the target. */
1553 linux_nat_add_target (t
);
1554 linux_nat_set_new_thread (t
, aarch64_linux_new_thread
);
1555 linux_nat_set_new_fork (t
, aarch64_linux_new_fork
);
1556 linux_nat_set_forget_process (t
, aarch64_forget_process
);
1557 linux_nat_set_prepare_to_resume (t
, aarch64_linux_prepare_to_resume
);