1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "reggroups.h"
31 #include "arch-utils.h"
33 #include "frame-unwind.h"
34 #include "frame-base.h"
35 #include "trad-frame.h"
37 #include "dwarf2-frame.h"
39 #include "prologue-value.h"
40 #include "target-descriptions.h"
41 #include "user-regs.h"
48 #include "aarch64-tdep.h"
51 #include "elf/aarch64.h"
56 #include "record-full.h"
57 #include "arch/aarch64-insn.h"
59 #include "opcode/aarch64.h"
62 #define submask(x) ((1L << ((x) + 1)) - 1)
63 #define bit(obj,st) (((obj) >> (st)) & 1)
64 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
66 /* Pseudo register base numbers. */
67 #define AARCH64_Q0_REGNUM 0
68 #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT)
69 #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
70 #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
71 #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
72 #define AARCH64_SVE_V0_REGNUM (AARCH64_B0_REGNUM + 32)
74 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
76 #define HA_MAX_NUM_FLDS 4
78 /* All possible aarch64 target descriptors. */
79 struct target_desc
*tdesc_aarch64_list
[AARCH64_MAX_SVE_VQ
+ 1];
81 /* The standard register names, and all the valid aliases for them. */
84 const char *const name
;
86 } aarch64_register_aliases
[] =
88 /* 64-bit register names. */
89 {"fp", AARCH64_FP_REGNUM
},
90 {"lr", AARCH64_LR_REGNUM
},
91 {"sp", AARCH64_SP_REGNUM
},
93 /* 32-bit register names. */
94 {"w0", AARCH64_X0_REGNUM
+ 0},
95 {"w1", AARCH64_X0_REGNUM
+ 1},
96 {"w2", AARCH64_X0_REGNUM
+ 2},
97 {"w3", AARCH64_X0_REGNUM
+ 3},
98 {"w4", AARCH64_X0_REGNUM
+ 4},
99 {"w5", AARCH64_X0_REGNUM
+ 5},
100 {"w6", AARCH64_X0_REGNUM
+ 6},
101 {"w7", AARCH64_X0_REGNUM
+ 7},
102 {"w8", AARCH64_X0_REGNUM
+ 8},
103 {"w9", AARCH64_X0_REGNUM
+ 9},
104 {"w10", AARCH64_X0_REGNUM
+ 10},
105 {"w11", AARCH64_X0_REGNUM
+ 11},
106 {"w12", AARCH64_X0_REGNUM
+ 12},
107 {"w13", AARCH64_X0_REGNUM
+ 13},
108 {"w14", AARCH64_X0_REGNUM
+ 14},
109 {"w15", AARCH64_X0_REGNUM
+ 15},
110 {"w16", AARCH64_X0_REGNUM
+ 16},
111 {"w17", AARCH64_X0_REGNUM
+ 17},
112 {"w18", AARCH64_X0_REGNUM
+ 18},
113 {"w19", AARCH64_X0_REGNUM
+ 19},
114 {"w20", AARCH64_X0_REGNUM
+ 20},
115 {"w21", AARCH64_X0_REGNUM
+ 21},
116 {"w22", AARCH64_X0_REGNUM
+ 22},
117 {"w23", AARCH64_X0_REGNUM
+ 23},
118 {"w24", AARCH64_X0_REGNUM
+ 24},
119 {"w25", AARCH64_X0_REGNUM
+ 25},
120 {"w26", AARCH64_X0_REGNUM
+ 26},
121 {"w27", AARCH64_X0_REGNUM
+ 27},
122 {"w28", AARCH64_X0_REGNUM
+ 28},
123 {"w29", AARCH64_X0_REGNUM
+ 29},
124 {"w30", AARCH64_X0_REGNUM
+ 30},
127 {"ip0", AARCH64_X0_REGNUM
+ 16},
128 {"ip1", AARCH64_X0_REGNUM
+ 17}
131 /* The required core 'R' registers. */
132 static const char *const aarch64_r_register_names
[] =
134 /* These registers must appear in consecutive RAW register number
135 order and they must begin with AARCH64_X0_REGNUM! */
136 "x0", "x1", "x2", "x3",
137 "x4", "x5", "x6", "x7",
138 "x8", "x9", "x10", "x11",
139 "x12", "x13", "x14", "x15",
140 "x16", "x17", "x18", "x19",
141 "x20", "x21", "x22", "x23",
142 "x24", "x25", "x26", "x27",
143 "x28", "x29", "x30", "sp",
147 /* The FP/SIMD 'V' registers. */
148 static const char *const aarch64_v_register_names
[] =
150 /* These registers must appear in consecutive RAW register number
151 order and they must begin with AARCH64_V0_REGNUM! */
152 "v0", "v1", "v2", "v3",
153 "v4", "v5", "v6", "v7",
154 "v8", "v9", "v10", "v11",
155 "v12", "v13", "v14", "v15",
156 "v16", "v17", "v18", "v19",
157 "v20", "v21", "v22", "v23",
158 "v24", "v25", "v26", "v27",
159 "v28", "v29", "v30", "v31",
164 /* The SVE 'Z' and 'P' registers. */
165 static const char *const aarch64_sve_register_names
[] =
167 /* These registers must appear in consecutive RAW register number
168 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
169 "z0", "z1", "z2", "z3",
170 "z4", "z5", "z6", "z7",
171 "z8", "z9", "z10", "z11",
172 "z12", "z13", "z14", "z15",
173 "z16", "z17", "z18", "z19",
174 "z20", "z21", "z22", "z23",
175 "z24", "z25", "z26", "z27",
176 "z28", "z29", "z30", "z31",
178 "p0", "p1", "p2", "p3",
179 "p4", "p5", "p6", "p7",
180 "p8", "p9", "p10", "p11",
181 "p12", "p13", "p14", "p15",
185 /* AArch64 prologue cache structure. */
186 struct aarch64_prologue_cache
188 /* The program counter at the start of the function. It is used to
189 identify this frame as a prologue frame. */
192 /* The program counter at the time this frame was created; i.e. where
193 this function was called from. It is used to identify this frame as a
197 /* The stack pointer at the time this frame was created; i.e. the
198 caller's stack pointer when this function was called. It is used
199 to identify this frame. */
202 /* Is the target available to read from? */
205 /* The frame base for this frame is just prev_sp - frame size.
206 FRAMESIZE is the distance from the frame pointer to the
207 initial stack pointer. */
210 /* The register used to hold the frame pointer for this frame. */
213 /* Saved register offsets. */
214 struct trad_frame_saved_reg
*saved_regs
;
218 show_aarch64_debug (struct ui_file
*file
, int from_tty
,
219 struct cmd_list_element
*c
, const char *value
)
221 fprintf_filtered (file
, _("AArch64 debugging is %s.\n"), value
);
226 /* Abstract instruction reader. */
228 class abstract_instruction_reader
231 /* Read in one instruction. */
232 virtual ULONGEST
read (CORE_ADDR memaddr
, int len
,
233 enum bfd_endian byte_order
) = 0;
236 /* Instruction reader from real target. */
238 class instruction_reader
: public abstract_instruction_reader
241 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
244 return read_code_unsigned_integer (memaddr
, len
, byte_order
);
250 /* Analyze a prologue, looking for a recognizable stack frame
251 and frame pointer. Scan until we encounter a store that could
252 clobber the stack frame unexpectedly, or an unknown instruction. */
255 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
256 CORE_ADDR start
, CORE_ADDR limit
,
257 struct aarch64_prologue_cache
*cache
,
258 abstract_instruction_reader
& reader
)
260 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
262 /* Track X registers and D registers in prologue. */
263 pv_t regs
[AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
];
265 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
; i
++)
266 regs
[i
] = pv_register (i
, 0);
267 pv_area
stack (AARCH64_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
269 for (; start
< limit
; start
+= 4)
274 insn
= reader
.read (start
, 4, byte_order_for_code
);
276 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
279 if (inst
.opcode
->iclass
== addsub_imm
280 && (inst
.opcode
->op
== OP_ADD
281 || strcmp ("sub", inst
.opcode
->name
) == 0))
283 unsigned rd
= inst
.operands
[0].reg
.regno
;
284 unsigned rn
= inst
.operands
[1].reg
.regno
;
286 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 3);
287 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd_SP
);
288 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn_SP
);
289 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_AIMM
);
291 if (inst
.opcode
->op
== OP_ADD
)
293 regs
[rd
] = pv_add_constant (regs
[rn
],
294 inst
.operands
[2].imm
.value
);
298 regs
[rd
] = pv_add_constant (regs
[rn
],
299 -inst
.operands
[2].imm
.value
);
302 else if (inst
.opcode
->iclass
== pcreladdr
303 && inst
.operands
[1].type
== AARCH64_OPND_ADDR_ADRP
)
305 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
306 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
308 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
310 else if (inst
.opcode
->iclass
== branch_imm
)
312 /* Stop analysis on branch. */
315 else if (inst
.opcode
->iclass
== condbranch
)
317 /* Stop analysis on branch. */
320 else if (inst
.opcode
->iclass
== branch_reg
)
322 /* Stop analysis on branch. */
325 else if (inst
.opcode
->iclass
== compbranch
)
327 /* Stop analysis on branch. */
330 else if (inst
.opcode
->op
== OP_MOVZ
)
332 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
333 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
335 else if (inst
.opcode
->iclass
== log_shift
336 && strcmp (inst
.opcode
->name
, "orr") == 0)
338 unsigned rd
= inst
.operands
[0].reg
.regno
;
339 unsigned rn
= inst
.operands
[1].reg
.regno
;
340 unsigned rm
= inst
.operands
[2].reg
.regno
;
342 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
343 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn
);
344 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_Rm_SFT
);
346 if (inst
.operands
[2].shifter
.amount
== 0
347 && rn
== AARCH64_SP_REGNUM
)
353 debug_printf ("aarch64: prologue analysis gave up "
354 "addr=%s opcode=0x%x (orr x register)\n",
355 core_addr_to_string_nz (start
), insn
);
360 else if (inst
.opcode
->op
== OP_STUR
)
362 unsigned rt
= inst
.operands
[0].reg
.regno
;
363 unsigned rn
= inst
.operands
[1].addr
.base_regno
;
365 = (aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
) == 8);
367 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
368 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
);
369 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_ADDR_SIMM9
);
370 gdb_assert (!inst
.operands
[1].addr
.offset
.is_reg
);
372 stack
.store (pv_add_constant (regs
[rn
],
373 inst
.operands
[1].addr
.offset
.imm
),
374 is64
? 8 : 4, regs
[rt
]);
376 else if ((inst
.opcode
->iclass
== ldstpair_off
377 || (inst
.opcode
->iclass
== ldstpair_indexed
378 && inst
.operands
[2].addr
.preind
))
379 && strcmp ("stp", inst
.opcode
->name
) == 0)
381 /* STP with addressing mode Pre-indexed and Base register. */
384 unsigned rn
= inst
.operands
[2].addr
.base_regno
;
385 int32_t imm
= inst
.operands
[2].addr
.offset
.imm
;
387 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
388 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
389 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rt2
390 || inst
.operands
[1].type
== AARCH64_OPND_Ft2
);
391 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_ADDR_SIMM7
);
392 gdb_assert (!inst
.operands
[2].addr
.offset
.is_reg
);
394 /* If recording this store would invalidate the store area
395 (perhaps because rn is not known) then we should abandon
396 further prologue analysis. */
397 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
)))
400 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
+ 8)))
403 rt1
= inst
.operands
[0].reg
.regno
;
404 rt2
= inst
.operands
[1].reg
.regno
;
405 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
407 /* Only bottom 64-bit of each V register (D register) need
409 gdb_assert (inst
.operands
[0].qualifier
== AARCH64_OPND_QLF_S_D
);
410 rt1
+= AARCH64_X_REGISTER_COUNT
;
411 rt2
+= AARCH64_X_REGISTER_COUNT
;
414 stack
.store (pv_add_constant (regs
[rn
], imm
), 8,
416 stack
.store (pv_add_constant (regs
[rn
], imm
+ 8), 8,
419 if (inst
.operands
[2].addr
.writeback
)
420 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
423 else if ((inst
.opcode
->iclass
== ldst_imm9
/* Signed immediate. */
424 || (inst
.opcode
->iclass
== ldst_pos
/* Unsigned immediate. */
425 && (inst
.opcode
->op
== OP_STR_POS
426 || inst
.opcode
->op
== OP_STRF_POS
)))
427 && inst
.operands
[1].addr
.base_regno
== AARCH64_SP_REGNUM
428 && strcmp ("str", inst
.opcode
->name
) == 0)
430 /* STR (immediate) */
431 unsigned int rt
= inst
.operands
[0].reg
.regno
;
432 int32_t imm
= inst
.operands
[1].addr
.offset
.imm
;
433 unsigned int rn
= inst
.operands
[1].addr
.base_regno
;
435 = (aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
) == 8);
436 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
437 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
439 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
441 /* Only bottom 64-bit of each V register (D register) need
443 gdb_assert (inst
.operands
[0].qualifier
== AARCH64_OPND_QLF_S_D
);
444 rt
+= AARCH64_X_REGISTER_COUNT
;
447 stack
.store (pv_add_constant (regs
[rn
], imm
),
448 is64
? 8 : 4, regs
[rt
]);
449 if (inst
.operands
[1].addr
.writeback
)
450 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
452 else if (inst
.opcode
->iclass
== testbranch
)
454 /* Stop analysis on branch. */
461 debug_printf ("aarch64: prologue analysis gave up addr=%s"
463 core_addr_to_string_nz (start
), insn
);
472 if (pv_is_register (regs
[AARCH64_FP_REGNUM
], AARCH64_SP_REGNUM
))
474 /* Frame pointer is fp. Frame size is constant. */
475 cache
->framereg
= AARCH64_FP_REGNUM
;
476 cache
->framesize
= -regs
[AARCH64_FP_REGNUM
].k
;
478 else if (pv_is_register (regs
[AARCH64_SP_REGNUM
], AARCH64_SP_REGNUM
))
480 /* Try the stack pointer. */
481 cache
->framesize
= -regs
[AARCH64_SP_REGNUM
].k
;
482 cache
->framereg
= AARCH64_SP_REGNUM
;
486 /* We're just out of luck. We don't know where the frame is. */
487 cache
->framereg
= -1;
488 cache
->framesize
= 0;
491 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
495 if (stack
.find_reg (gdbarch
, i
, &offset
))
496 cache
->saved_regs
[i
].addr
= offset
;
499 for (i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
501 int regnum
= gdbarch_num_regs (gdbarch
);
504 if (stack
.find_reg (gdbarch
, i
+ AARCH64_X_REGISTER_COUNT
,
506 cache
->saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
= offset
;
513 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
514 CORE_ADDR start
, CORE_ADDR limit
,
515 struct aarch64_prologue_cache
*cache
)
517 instruction_reader reader
;
519 return aarch64_analyze_prologue (gdbarch
, start
, limit
, cache
,
525 namespace selftests
{
527 /* Instruction reader from manually cooked instruction sequences. */
529 class instruction_reader_test
: public abstract_instruction_reader
532 template<size_t SIZE
>
533 explicit instruction_reader_test (const uint32_t (&insns
)[SIZE
])
534 : m_insns (insns
), m_insns_size (SIZE
)
537 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
540 SELF_CHECK (len
== 4);
541 SELF_CHECK (memaddr
% 4 == 0);
542 SELF_CHECK (memaddr
/ 4 < m_insns_size
);
544 return m_insns
[memaddr
/ 4];
548 const uint32_t *m_insns
;
553 aarch64_analyze_prologue_test (void)
555 struct gdbarch_info info
;
557 gdbarch_info_init (&info
);
558 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
560 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
561 SELF_CHECK (gdbarch
!= NULL
);
563 /* Test the simple prologue in which frame pointer is used. */
565 struct aarch64_prologue_cache cache
;
566 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
568 static const uint32_t insns
[] = {
569 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
570 0x910003fd, /* mov x29, sp */
571 0x97ffffe6, /* bl 0x400580 */
573 instruction_reader_test
reader (insns
);
575 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
576 SELF_CHECK (end
== 4 * 2);
578 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
579 SELF_CHECK (cache
.framesize
== 272);
581 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
583 if (i
== AARCH64_FP_REGNUM
)
584 SELF_CHECK (cache
.saved_regs
[i
].addr
== -272);
585 else if (i
== AARCH64_LR_REGNUM
)
586 SELF_CHECK (cache
.saved_regs
[i
].addr
== -264);
588 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
591 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
593 int regnum
= gdbarch_num_regs (gdbarch
);
595 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
600 /* Test a prologue in which STR is used and frame pointer is not
603 struct aarch64_prologue_cache cache
;
604 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
606 static const uint32_t insns
[] = {
607 0xf81d0ff3, /* str x19, [sp, #-48]! */
608 0xb9002fe0, /* str w0, [sp, #44] */
609 0xf90013e1, /* str x1, [sp, #32]*/
610 0xfd000fe0, /* str d0, [sp, #24] */
611 0xaa0203f3, /* mov x19, x2 */
612 0xf94013e0, /* ldr x0, [sp, #32] */
614 instruction_reader_test
reader (insns
);
616 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
618 SELF_CHECK (end
== 4 * 5);
620 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
621 SELF_CHECK (cache
.framesize
== 48);
623 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
626 SELF_CHECK (cache
.saved_regs
[i
].addr
== -16);
628 SELF_CHECK (cache
.saved_regs
[i
].addr
== -48);
630 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
633 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
635 int regnum
= gdbarch_num_regs (gdbarch
);
638 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
641 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
646 } // namespace selftests
647 #endif /* GDB_SELF_TEST */
649 /* Implement the "skip_prologue" gdbarch method. */
652 aarch64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
654 CORE_ADDR func_addr
, limit_pc
;
656 /* See if we can determine the end of the prologue via the symbol
657 table. If so, then return either PC, or the PC after the
658 prologue, whichever is greater. */
659 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
661 CORE_ADDR post_prologue_pc
662 = skip_prologue_using_sal (gdbarch
, func_addr
);
664 if (post_prologue_pc
!= 0)
665 return std::max (pc
, post_prologue_pc
);
668 /* Can't determine prologue from the symbol table, need to examine
671 /* Find an upper limit on the function prologue using the debug
672 information. If the debug information could not be used to
673 provide that bound, then use an arbitrary large number as the
675 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
677 limit_pc
= pc
+ 128; /* Magic. */
679 /* Try disassembling prologue. */
680 return aarch64_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
683 /* Scan the function prologue for THIS_FRAME and populate the prologue
687 aarch64_scan_prologue (struct frame_info
*this_frame
,
688 struct aarch64_prologue_cache
*cache
)
690 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
691 CORE_ADDR prologue_start
;
692 CORE_ADDR prologue_end
;
693 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
694 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
696 cache
->prev_pc
= prev_pc
;
698 /* Assume we do not find a frame. */
699 cache
->framereg
= -1;
700 cache
->framesize
= 0;
702 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
705 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
709 /* No line info so use the current PC. */
710 prologue_end
= prev_pc
;
712 else if (sal
.end
< prologue_end
)
714 /* The next line begins after the function end. */
715 prologue_end
= sal
.end
;
718 prologue_end
= std::min (prologue_end
, prev_pc
);
719 aarch64_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
725 frame_loc
= get_frame_register_unsigned (this_frame
, AARCH64_FP_REGNUM
);
729 cache
->framereg
= AARCH64_FP_REGNUM
;
730 cache
->framesize
= 16;
731 cache
->saved_regs
[29].addr
= 0;
732 cache
->saved_regs
[30].addr
= 8;
736 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
737 function may throw an exception if the inferior's registers or memory is
741 aarch64_make_prologue_cache_1 (struct frame_info
*this_frame
,
742 struct aarch64_prologue_cache
*cache
)
744 CORE_ADDR unwound_fp
;
747 aarch64_scan_prologue (this_frame
, cache
);
749 if (cache
->framereg
== -1)
752 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
756 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
758 /* Calculate actual addresses of saved registers using offsets
759 determined by aarch64_analyze_prologue. */
760 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
761 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
762 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
764 cache
->func
= get_frame_func (this_frame
);
766 cache
->available_p
= 1;
769 /* Allocate and fill in *THIS_CACHE with information about the prologue of
770 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
771 Return a pointer to the current aarch64_prologue_cache in
774 static struct aarch64_prologue_cache
*
775 aarch64_make_prologue_cache (struct frame_info
*this_frame
, void **this_cache
)
777 struct aarch64_prologue_cache
*cache
;
779 if (*this_cache
!= NULL
)
780 return (struct aarch64_prologue_cache
*) *this_cache
;
782 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
783 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
788 aarch64_make_prologue_cache_1 (this_frame
, cache
);
790 CATCH (ex
, RETURN_MASK_ERROR
)
792 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
793 throw_exception (ex
);
800 /* Implement the "stop_reason" frame_unwind method. */
802 static enum unwind_stop_reason
803 aarch64_prologue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
806 struct aarch64_prologue_cache
*cache
807 = aarch64_make_prologue_cache (this_frame
, this_cache
);
809 if (!cache
->available_p
)
810 return UNWIND_UNAVAILABLE
;
812 /* Halt the backtrace at "_start". */
813 if (cache
->prev_pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
814 return UNWIND_OUTERMOST
;
816 /* We've hit a wall, stop. */
817 if (cache
->prev_sp
== 0)
818 return UNWIND_OUTERMOST
;
820 return UNWIND_NO_REASON
;
823 /* Our frame ID for a normal frame is the current function's starting
824 PC and the caller's SP when we were called. */
827 aarch64_prologue_this_id (struct frame_info
*this_frame
,
828 void **this_cache
, struct frame_id
*this_id
)
830 struct aarch64_prologue_cache
*cache
831 = aarch64_make_prologue_cache (this_frame
, this_cache
);
833 if (!cache
->available_p
)
834 *this_id
= frame_id_build_unavailable_stack (cache
->func
);
836 *this_id
= frame_id_build (cache
->prev_sp
, cache
->func
);
839 /* Implement the "prev_register" frame_unwind method. */
841 static struct value
*
842 aarch64_prologue_prev_register (struct frame_info
*this_frame
,
843 void **this_cache
, int prev_regnum
)
845 struct aarch64_prologue_cache
*cache
846 = aarch64_make_prologue_cache (this_frame
, this_cache
);
848 /* If we are asked to unwind the PC, then we need to return the LR
849 instead. The prologue may save PC, but it will point into this
850 frame's prologue, not the next frame's resume location. */
851 if (prev_regnum
== AARCH64_PC_REGNUM
)
855 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
856 return frame_unwind_got_constant (this_frame
, prev_regnum
, lr
);
859 /* SP is generally not saved to the stack, but this frame is
860 identified by the next frame's stack pointer at the time of the
861 call. The value was already reconstructed into PREV_SP. */
874 if (prev_regnum
== AARCH64_SP_REGNUM
)
875 return frame_unwind_got_constant (this_frame
, prev_regnum
,
878 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
882 /* AArch64 prologue unwinder. */
883 struct frame_unwind aarch64_prologue_unwind
=
886 aarch64_prologue_frame_unwind_stop_reason
,
887 aarch64_prologue_this_id
,
888 aarch64_prologue_prev_register
,
890 default_frame_sniffer
893 /* Allocate and fill in *THIS_CACHE with information about the prologue of
894 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
895 Return a pointer to the current aarch64_prologue_cache in
898 static struct aarch64_prologue_cache
*
899 aarch64_make_stub_cache (struct frame_info
*this_frame
, void **this_cache
)
901 struct aarch64_prologue_cache
*cache
;
903 if (*this_cache
!= NULL
)
904 return (struct aarch64_prologue_cache
*) *this_cache
;
906 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
907 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
912 cache
->prev_sp
= get_frame_register_unsigned (this_frame
,
914 cache
->prev_pc
= get_frame_pc (this_frame
);
915 cache
->available_p
= 1;
917 CATCH (ex
, RETURN_MASK_ERROR
)
919 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
920 throw_exception (ex
);
927 /* Implement the "stop_reason" frame_unwind method. */
929 static enum unwind_stop_reason
930 aarch64_stub_frame_unwind_stop_reason (struct frame_info
*this_frame
,
933 struct aarch64_prologue_cache
*cache
934 = aarch64_make_stub_cache (this_frame
, this_cache
);
936 if (!cache
->available_p
)
937 return UNWIND_UNAVAILABLE
;
939 return UNWIND_NO_REASON
;
942 /* Our frame ID for a stub frame is the current SP and LR. */
945 aarch64_stub_this_id (struct frame_info
*this_frame
,
946 void **this_cache
, struct frame_id
*this_id
)
948 struct aarch64_prologue_cache
*cache
949 = aarch64_make_stub_cache (this_frame
, this_cache
);
951 if (cache
->available_p
)
952 *this_id
= frame_id_build (cache
->prev_sp
, cache
->prev_pc
);
954 *this_id
= frame_id_build_unavailable_stack (cache
->prev_pc
);
957 /* Implement the "sniffer" frame_unwind method. */
960 aarch64_stub_unwind_sniffer (const struct frame_unwind
*self
,
961 struct frame_info
*this_frame
,
962 void **this_prologue_cache
)
964 CORE_ADDR addr_in_block
;
967 addr_in_block
= get_frame_address_in_block (this_frame
);
968 if (in_plt_section (addr_in_block
)
969 /* We also use the stub winder if the target memory is unreadable
970 to avoid having the prologue unwinder trying to read it. */
971 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
977 /* AArch64 stub unwinder. */
978 struct frame_unwind aarch64_stub_unwind
=
981 aarch64_stub_frame_unwind_stop_reason
,
982 aarch64_stub_this_id
,
983 aarch64_prologue_prev_register
,
985 aarch64_stub_unwind_sniffer
988 /* Return the frame base address of *THIS_FRAME. */
991 aarch64_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
993 struct aarch64_prologue_cache
*cache
994 = aarch64_make_prologue_cache (this_frame
, this_cache
);
996 return cache
->prev_sp
- cache
->framesize
;
999 /* AArch64 default frame base information. */
1000 struct frame_base aarch64_normal_base
=
1002 &aarch64_prologue_unwind
,
1003 aarch64_normal_frame_base
,
1004 aarch64_normal_frame_base
,
1005 aarch64_normal_frame_base
1008 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1009 dummy frame. The frame ID's base needs to match the TOS value
1010 saved by save_dummy_frame_tos () and returned from
1011 aarch64_push_dummy_call, and the PC needs to match the dummy
1012 frame's breakpoint. */
1014 static struct frame_id
1015 aarch64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1017 return frame_id_build (get_frame_register_unsigned (this_frame
,
1019 get_frame_pc (this_frame
));
1022 /* Implement the "unwind_pc" gdbarch method. */
1025 aarch64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1028 = frame_unwind_register_unsigned (this_frame
, AARCH64_PC_REGNUM
);
1033 /* Implement the "unwind_sp" gdbarch method. */
1036 aarch64_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1038 return frame_unwind_register_unsigned (this_frame
, AARCH64_SP_REGNUM
);
1041 /* Return the value of the REGNUM register in the previous frame of
1044 static struct value
*
1045 aarch64_dwarf2_prev_register (struct frame_info
*this_frame
,
1046 void **this_cache
, int regnum
)
1052 case AARCH64_PC_REGNUM
:
1053 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1054 return frame_unwind_got_constant (this_frame
, regnum
, lr
);
1057 internal_error (__FILE__
, __LINE__
,
1058 _("Unexpected register %d"), regnum
);
1062 /* Implement the "init_reg" dwarf2_frame_ops method. */
1065 aarch64_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1066 struct dwarf2_frame_state_reg
*reg
,
1067 struct frame_info
*this_frame
)
1071 case AARCH64_PC_REGNUM
:
1072 reg
->how
= DWARF2_FRAME_REG_FN
;
1073 reg
->loc
.fn
= aarch64_dwarf2_prev_register
;
1075 case AARCH64_SP_REGNUM
:
1076 reg
->how
= DWARF2_FRAME_REG_CFA
;
1081 /* When arguments must be pushed onto the stack, they go on in reverse
1082 order. The code below implements a FILO (stack) to do this. */
1086 /* Value to pass on stack. It can be NULL if this item is for stack
1088 const gdb_byte
*data
;
1090 /* Size in bytes of value to pass on stack. */
1094 DEF_VEC_O (stack_item_t
);
1096 /* Return the alignment (in bytes) of the given type. */
1099 aarch64_type_align (struct type
*t
)
1105 t
= check_typedef (t
);
1106 switch (TYPE_CODE (t
))
1109 /* Should never happen. */
1110 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1114 case TYPE_CODE_ENUM
:
1118 case TYPE_CODE_RANGE
:
1119 case TYPE_CODE_BITSTRING
:
1121 case TYPE_CODE_RVALUE_REF
:
1122 case TYPE_CODE_CHAR
:
1123 case TYPE_CODE_BOOL
:
1124 return TYPE_LENGTH (t
);
1126 case TYPE_CODE_ARRAY
:
1127 if (TYPE_VECTOR (t
))
1129 /* Use the natural alignment for vector types (the same for
1130 scalar type), but the maximum alignment is 128-bit. */
1131 if (TYPE_LENGTH (t
) > 16)
1134 return TYPE_LENGTH (t
);
1137 return aarch64_type_align (TYPE_TARGET_TYPE (t
));
1138 case TYPE_CODE_COMPLEX
:
1139 return aarch64_type_align (TYPE_TARGET_TYPE (t
));
1141 case TYPE_CODE_STRUCT
:
1142 case TYPE_CODE_UNION
:
1144 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1146 falign
= aarch64_type_align (TYPE_FIELD_TYPE (t
, n
));
1154 /* Return 1 if *TY is a homogeneous floating-point aggregate or
1155 homogeneous short-vector aggregate as defined in the AAPCS64 ABI
1156 document; otherwise return 0. */
1159 is_hfa_or_hva (struct type
*ty
)
1161 switch (TYPE_CODE (ty
))
1163 case TYPE_CODE_ARRAY
:
1165 struct type
*target_ty
= TYPE_TARGET_TYPE (ty
);
1167 if (TYPE_VECTOR (ty
))
1170 if (TYPE_LENGTH (ty
) <= 4 /* HFA or HVA has at most 4 members. */
1171 && (TYPE_CODE (target_ty
) == TYPE_CODE_FLT
/* HFA */
1172 || (TYPE_CODE (target_ty
) == TYPE_CODE_ARRAY
/* HVA */
1173 && TYPE_VECTOR (target_ty
))))
1178 case TYPE_CODE_UNION
:
1179 case TYPE_CODE_STRUCT
:
1181 /* HFA or HVA has at most four members. */
1182 if (TYPE_NFIELDS (ty
) > 0 && TYPE_NFIELDS (ty
) <= 4)
1184 struct type
*member0_type
;
1186 member0_type
= check_typedef (TYPE_FIELD_TYPE (ty
, 0));
1187 if (TYPE_CODE (member0_type
) == TYPE_CODE_FLT
1188 || (TYPE_CODE (member0_type
) == TYPE_CODE_ARRAY
1189 && TYPE_VECTOR (member0_type
)))
1193 for (i
= 0; i
< TYPE_NFIELDS (ty
); i
++)
1195 struct type
*member1_type
;
1197 member1_type
= check_typedef (TYPE_FIELD_TYPE (ty
, i
));
1198 if (TYPE_CODE (member0_type
) != TYPE_CODE (member1_type
)
1199 || (TYPE_LENGTH (member0_type
)
1200 != TYPE_LENGTH (member1_type
)))
1216 /* Worker function for aapcs_is_vfp_call_or_return_candidate.
1218 Return the number of register required, or -1 on failure.
1220 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1221 to the element, else fail if the type of this element does not match the
1225 aapcs_is_vfp_call_or_return_candidate_1 (struct type
*type
,
1226 struct type
**fundamental_type
)
1228 if (type
== nullptr)
1231 switch (TYPE_CODE (type
))
1234 if (TYPE_LENGTH (type
) > 16)
1237 if (*fundamental_type
== nullptr)
1238 *fundamental_type
= type
;
1239 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1240 || TYPE_CODE (type
) != TYPE_CODE (*fundamental_type
))
1245 case TYPE_CODE_COMPLEX
:
1247 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
1248 if (TYPE_LENGTH (target_type
) > 16)
1251 if (*fundamental_type
== nullptr)
1252 *fundamental_type
= target_type
;
1253 else if (TYPE_LENGTH (target_type
) != TYPE_LENGTH (*fundamental_type
)
1254 || TYPE_CODE (target_type
) != TYPE_CODE (*fundamental_type
))
1260 case TYPE_CODE_ARRAY
:
1262 if (TYPE_VECTOR (type
))
1264 if (TYPE_LENGTH (type
) != 8 && TYPE_LENGTH (type
) != 16)
1267 if (*fundamental_type
== nullptr)
1268 *fundamental_type
= type
;
1269 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1270 || TYPE_CODE (type
) != TYPE_CODE (*fundamental_type
))
1277 struct type
*target_type
= TYPE_TARGET_TYPE (type
);
1278 int count
= aapcs_is_vfp_call_or_return_candidate_1
1279 (target_type
, fundamental_type
);
1284 count
*= TYPE_LENGTH (type
);
1289 case TYPE_CODE_STRUCT
:
1290 case TYPE_CODE_UNION
:
1294 for (int i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1296 struct type
*member
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
1298 int sub_count
= aapcs_is_vfp_call_or_return_candidate_1
1299 (member
, fundamental_type
);
1300 if (sub_count
== -1)
1314 /* Return true if an argument, whose type is described by TYPE, can be passed or
1315 returned in simd/fp registers, providing enough parameter passing registers
1316 are available. This is as described in the AAPCS64.
1318 Upon successful return, *COUNT returns the number of needed registers,
1319 *FUNDAMENTAL_TYPE contains the type of those registers.
1321 Candidate as per the AAPCS64 5.4.2.C is either a:
1324 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1325 all the members are floats and has at most 4 members.
1326 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1327 all the members are short vectors and has at most 4 members.
1330 Note that HFAs and HVAs can include nested structures and arrays. */
1333 aapcs_is_vfp_call_or_return_candidate (struct type
*type
, int *count
,
1334 struct type
**fundamental_type
)
1336 if (type
== nullptr)
1339 *fundamental_type
= nullptr;
1341 int ag_count
= aapcs_is_vfp_call_or_return_candidate_1 (type
,
1344 if (ag_count
> 0 && ag_count
<= HA_MAX_NUM_FLDS
)
1353 /* AArch64 function call information structure. */
1354 struct aarch64_call_info
1356 /* the current argument number. */
1359 /* The next general purpose register number, equivalent to NGRN as
1360 described in the AArch64 Procedure Call Standard. */
1363 /* The next SIMD and floating point register number, equivalent to
1364 NSRN as described in the AArch64 Procedure Call Standard. */
1367 /* The next stacked argument address, equivalent to NSAA as
1368 described in the AArch64 Procedure Call Standard. */
1371 /* Stack item vector. */
1372 VEC(stack_item_t
) *si
;
1375 /* Pass a value in a sequence of consecutive X registers. The caller
1376 is responsbile for ensuring sufficient registers are available. */
1379 pass_in_x (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1380 struct aarch64_call_info
*info
, struct type
*type
,
1383 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1384 int len
= TYPE_LENGTH (type
);
1385 enum type_code typecode
= TYPE_CODE (type
);
1386 int regnum
= AARCH64_X0_REGNUM
+ info
->ngrn
;
1387 const bfd_byte
*buf
= value_contents (arg
);
1393 int partial_len
= len
< X_REGISTER_SIZE
? len
: X_REGISTER_SIZE
;
1394 CORE_ADDR regval
= extract_unsigned_integer (buf
, partial_len
,
1398 /* Adjust sub-word struct/union args when big-endian. */
1399 if (byte_order
== BFD_ENDIAN_BIG
1400 && partial_len
< X_REGISTER_SIZE
1401 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1402 regval
<<= ((X_REGISTER_SIZE
- partial_len
) * TARGET_CHAR_BIT
);
1406 debug_printf ("arg %d in %s = 0x%s\n", info
->argnum
,
1407 gdbarch_register_name (gdbarch
, regnum
),
1408 phex (regval
, X_REGISTER_SIZE
));
1410 regcache_cooked_write_unsigned (regcache
, regnum
, regval
);
1417 /* Attempt to marshall a value in a V register. Return 1 if
1418 successful, or 0 if insufficient registers are available. This
1419 function, unlike the equivalent pass_in_x() function does not
1420 handle arguments spread across multiple registers. */
1423 pass_in_v (struct gdbarch
*gdbarch
,
1424 struct regcache
*regcache
,
1425 struct aarch64_call_info
*info
,
1426 int len
, const bfd_byte
*buf
)
1430 int regnum
= AARCH64_V0_REGNUM
+ info
->nsrn
;
1431 gdb_byte reg
[V_REGISTER_SIZE
];
1436 memset (reg
, 0, sizeof (reg
));
1437 /* PCS C.1, the argument is allocated to the least significant
1438 bits of V register. */
1439 memcpy (reg
, buf
, len
);
1440 regcache
->cooked_write (regnum
, reg
);
1444 debug_printf ("arg %d in %s\n", info
->argnum
,
1445 gdbarch_register_name (gdbarch
, regnum
));
1453 /* Marshall an argument onto the stack. */
1456 pass_on_stack (struct aarch64_call_info
*info
, struct type
*type
,
1459 const bfd_byte
*buf
= value_contents (arg
);
1460 int len
= TYPE_LENGTH (type
);
1466 align
= aarch64_type_align (type
);
1468 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1469 Natural alignment of the argument's type. */
1470 align
= align_up (align
, 8);
1472 /* The AArch64 PCS requires at most doubleword alignment. */
1478 debug_printf ("arg %d len=%d @ sp + %d\n", info
->argnum
, len
,
1484 VEC_safe_push (stack_item_t
, info
->si
, &item
);
1487 if (info
->nsaa
& (align
- 1))
1489 /* Push stack alignment padding. */
1490 int pad
= align
- (info
->nsaa
& (align
- 1));
1495 VEC_safe_push (stack_item_t
, info
->si
, &item
);
1500 /* Marshall an argument into a sequence of one or more consecutive X
1501 registers or, if insufficient X registers are available then onto
1505 pass_in_x_or_stack (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1506 struct aarch64_call_info
*info
, struct type
*type
,
1509 int len
= TYPE_LENGTH (type
);
1510 int nregs
= (len
+ X_REGISTER_SIZE
- 1) / X_REGISTER_SIZE
;
1512 /* PCS C.13 - Pass in registers if we have enough spare */
1513 if (info
->ngrn
+ nregs
<= 8)
1515 pass_in_x (gdbarch
, regcache
, info
, type
, arg
);
1516 info
->ngrn
+= nregs
;
1521 pass_on_stack (info
, type
, arg
);
1525 /* Pass a value in a V register, or on the stack if insufficient are
1529 pass_in_v_or_stack (struct gdbarch
*gdbarch
,
1530 struct regcache
*regcache
,
1531 struct aarch64_call_info
*info
,
1535 if (!pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (type
),
1536 value_contents (arg
)))
1537 pass_on_stack (info
, type
, arg
);
1540 /* Implement the "push_dummy_call" gdbarch method. */
1543 aarch64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1544 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1546 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1547 CORE_ADDR struct_addr
)
1550 struct aarch64_call_info info
;
1551 struct type
*func_type
;
1552 struct type
*return_type
;
1553 int lang_struct_return
;
1555 memset (&info
, 0, sizeof (info
));
1557 /* We need to know what the type of the called function is in order
1558 to determine the number of named/anonymous arguments for the
1559 actual argument placement, and the return type in order to handle
1560 return value correctly.
1562 The generic code above us views the decision of return in memory
1563 or return in registers as a two stage processes. The language
1564 handler is consulted first and may decide to return in memory (eg
1565 class with copy constructor returned by value), this will cause
1566 the generic code to allocate space AND insert an initial leading
1569 If the language code does not decide to pass in memory then the
1570 target code is consulted.
1572 If the language code decides to pass in memory we want to move
1573 the pointer inserted as the initial argument from the argument
1574 list and into X8, the conventional AArch64 struct return pointer
1577 This is slightly awkward, ideally the flag "lang_struct_return"
1578 would be passed to the targets implementation of push_dummy_call.
1579 Rather that change the target interface we call the language code
1580 directly ourselves. */
1582 func_type
= check_typedef (value_type (function
));
1584 /* Dereference function pointer types. */
1585 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
1586 func_type
= TYPE_TARGET_TYPE (func_type
);
1588 gdb_assert (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
1589 || TYPE_CODE (func_type
) == TYPE_CODE_METHOD
);
1591 /* If language_pass_by_reference () returned true we will have been
1592 given an additional initial argument, a hidden pointer to the
1593 return slot in memory. */
1594 return_type
= TYPE_TARGET_TYPE (func_type
);
1595 lang_struct_return
= language_pass_by_reference (return_type
);
1597 /* Set the return address. For the AArch64, the return breakpoint
1598 is always at BP_ADDR. */
1599 regcache_cooked_write_unsigned (regcache
, AARCH64_LR_REGNUM
, bp_addr
);
1601 /* If we were given an initial argument for the return slot because
1602 lang_struct_return was true, lose it. */
1603 if (lang_struct_return
)
1609 /* The struct_return pointer occupies X8. */
1610 if (struct_return
|| lang_struct_return
)
1614 debug_printf ("struct return in %s = 0x%s\n",
1615 gdbarch_register_name (gdbarch
,
1616 AARCH64_STRUCT_RETURN_REGNUM
),
1617 paddress (gdbarch
, struct_addr
));
1619 regcache_cooked_write_unsigned (regcache
, AARCH64_STRUCT_RETURN_REGNUM
,
1623 for (argnum
= 0; argnum
< nargs
; argnum
++)
1625 struct value
*arg
= args
[argnum
];
1626 struct type
*arg_type
;
1629 arg_type
= check_typedef (value_type (arg
));
1630 len
= TYPE_LENGTH (arg_type
);
1632 switch (TYPE_CODE (arg_type
))
1635 case TYPE_CODE_BOOL
:
1636 case TYPE_CODE_CHAR
:
1637 case TYPE_CODE_RANGE
:
1638 case TYPE_CODE_ENUM
:
1641 /* Promote to 32 bit integer. */
1642 if (TYPE_UNSIGNED (arg_type
))
1643 arg_type
= builtin_type (gdbarch
)->builtin_uint32
;
1645 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
1646 arg
= value_cast (arg_type
, arg
);
1648 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1651 case TYPE_CODE_COMPLEX
:
1654 const bfd_byte
*buf
= value_contents (arg
);
1655 struct type
*target_type
=
1656 check_typedef (TYPE_TARGET_TYPE (arg_type
));
1658 pass_in_v (gdbarch
, regcache
, &info
,
1659 TYPE_LENGTH (target_type
), buf
);
1660 pass_in_v (gdbarch
, regcache
, &info
,
1661 TYPE_LENGTH (target_type
),
1662 buf
+ TYPE_LENGTH (target_type
));
1667 pass_on_stack (&info
, arg_type
, arg
);
1671 pass_in_v_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1674 case TYPE_CODE_STRUCT
:
1675 case TYPE_CODE_ARRAY
:
1676 case TYPE_CODE_UNION
:
1677 if (is_hfa_or_hva (arg_type
))
1679 int elements
= TYPE_NFIELDS (arg_type
);
1681 /* Homogeneous Aggregates */
1682 if (info
.nsrn
+ elements
< 8)
1686 for (i
= 0; i
< elements
; i
++)
1688 /* We know that we have sufficient registers
1689 available therefore this will never fallback
1691 struct value
*field
=
1692 value_primitive_field (arg
, 0, i
, arg_type
);
1693 struct type
*field_type
=
1694 check_typedef (value_type (field
));
1696 pass_in_v_or_stack (gdbarch
, regcache
, &info
,
1703 pass_on_stack (&info
, arg_type
, arg
);
1706 else if (TYPE_CODE (arg_type
) == TYPE_CODE_ARRAY
1707 && TYPE_VECTOR (arg_type
) && (len
== 16 || len
== 8))
1709 /* Short vector types are passed in V registers. */
1710 pass_in_v_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1714 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1715 invisible reference. */
1717 /* Allocate aligned storage. */
1718 sp
= align_down (sp
- len
, 16);
1720 /* Write the real data into the stack. */
1721 write_memory (sp
, value_contents (arg
), len
);
1723 /* Construct the indirection. */
1724 arg_type
= lookup_pointer_type (arg_type
);
1725 arg
= value_from_pointer (arg_type
, sp
);
1726 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1729 /* PCS C.15 / C.18 multiple values pass. */
1730 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1734 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1739 /* Make sure stack retains 16 byte alignment. */
1741 sp
-= 16 - (info
.nsaa
& 15);
1743 while (!VEC_empty (stack_item_t
, info
.si
))
1745 stack_item_t
*si
= VEC_last (stack_item_t
, info
.si
);
1748 if (si
->data
!= NULL
)
1749 write_memory (sp
, si
->data
, si
->len
);
1750 VEC_pop (stack_item_t
, info
.si
);
1753 VEC_free (stack_item_t
, info
.si
);
1755 /* Finally, update the SP register. */
1756 regcache_cooked_write_unsigned (regcache
, AARCH64_SP_REGNUM
, sp
);
1761 /* Implement the "frame_align" gdbarch method. */
1764 aarch64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1766 /* Align the stack to sixteen bytes. */
1767 return sp
& ~(CORE_ADDR
) 15;
1770 /* Return the type for an AdvSISD Q register. */
1772 static struct type
*
1773 aarch64_vnq_type (struct gdbarch
*gdbarch
)
1775 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1777 if (tdep
->vnq_type
== NULL
)
1782 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1785 elem
= builtin_type (gdbarch
)->builtin_uint128
;
1786 append_composite_type_field (t
, "u", elem
);
1788 elem
= builtin_type (gdbarch
)->builtin_int128
;
1789 append_composite_type_field (t
, "s", elem
);
1794 return tdep
->vnq_type
;
1797 /* Return the type for an AdvSISD D register. */
1799 static struct type
*
1800 aarch64_vnd_type (struct gdbarch
*gdbarch
)
1802 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1804 if (tdep
->vnd_type
== NULL
)
1809 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1812 elem
= builtin_type (gdbarch
)->builtin_double
;
1813 append_composite_type_field (t
, "f", elem
);
1815 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1816 append_composite_type_field (t
, "u", elem
);
1818 elem
= builtin_type (gdbarch
)->builtin_int64
;
1819 append_composite_type_field (t
, "s", elem
);
1824 return tdep
->vnd_type
;
1827 /* Return the type for an AdvSISD S register. */
1829 static struct type
*
1830 aarch64_vns_type (struct gdbarch
*gdbarch
)
1832 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1834 if (tdep
->vns_type
== NULL
)
1839 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
1842 elem
= builtin_type (gdbarch
)->builtin_float
;
1843 append_composite_type_field (t
, "f", elem
);
1845 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1846 append_composite_type_field (t
, "u", elem
);
1848 elem
= builtin_type (gdbarch
)->builtin_int32
;
1849 append_composite_type_field (t
, "s", elem
);
1854 return tdep
->vns_type
;
1857 /* Return the type for an AdvSISD H register. */
1859 static struct type
*
1860 aarch64_vnh_type (struct gdbarch
*gdbarch
)
1862 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1864 if (tdep
->vnh_type
== NULL
)
1869 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
1872 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1873 append_composite_type_field (t
, "u", elem
);
1875 elem
= builtin_type (gdbarch
)->builtin_int16
;
1876 append_composite_type_field (t
, "s", elem
);
1881 return tdep
->vnh_type
;
1884 /* Return the type for an AdvSISD B register. */
1886 static struct type
*
1887 aarch64_vnb_type (struct gdbarch
*gdbarch
)
1889 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1891 if (tdep
->vnb_type
== NULL
)
1896 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
1899 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1900 append_composite_type_field (t
, "u", elem
);
1902 elem
= builtin_type (gdbarch
)->builtin_int8
;
1903 append_composite_type_field (t
, "s", elem
);
1908 return tdep
->vnb_type
;
1911 /* Return the type for an AdvSISD V register. */
1913 static struct type
*
1914 aarch64_vnv_type (struct gdbarch
*gdbarch
)
1916 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1918 if (tdep
->vnv_type
== NULL
)
1920 struct type
*t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnv",
1923 append_composite_type_field (t
, "d", aarch64_vnd_type (gdbarch
));
1924 append_composite_type_field (t
, "s", aarch64_vns_type (gdbarch
));
1925 append_composite_type_field (t
, "h", aarch64_vnh_type (gdbarch
));
1926 append_composite_type_field (t
, "b", aarch64_vnb_type (gdbarch
));
1927 append_composite_type_field (t
, "q", aarch64_vnq_type (gdbarch
));
1932 return tdep
->vnv_type
;
1935 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1938 aarch64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1940 if (reg
>= AARCH64_DWARF_X0
&& reg
<= AARCH64_DWARF_X0
+ 30)
1941 return AARCH64_X0_REGNUM
+ reg
- AARCH64_DWARF_X0
;
1943 if (reg
== AARCH64_DWARF_SP
)
1944 return AARCH64_SP_REGNUM
;
1946 if (reg
>= AARCH64_DWARF_V0
&& reg
<= AARCH64_DWARF_V0
+ 31)
1947 return AARCH64_V0_REGNUM
+ reg
- AARCH64_DWARF_V0
;
1949 if (reg
== AARCH64_DWARF_SVE_VG
)
1950 return AARCH64_SVE_VG_REGNUM
;
1952 if (reg
== AARCH64_DWARF_SVE_FFR
)
1953 return AARCH64_SVE_FFR_REGNUM
;
1955 if (reg
>= AARCH64_DWARF_SVE_P0
&& reg
<= AARCH64_DWARF_SVE_P0
+ 15)
1956 return AARCH64_SVE_P0_REGNUM
+ reg
- AARCH64_DWARF_SVE_P0
;
1958 if (reg
>= AARCH64_DWARF_SVE_Z0
&& reg
<= AARCH64_DWARF_SVE_Z0
+ 15)
1959 return AARCH64_SVE_Z0_REGNUM
+ reg
- AARCH64_DWARF_SVE_Z0
;
1964 /* Implement the "print_insn" gdbarch method. */
1967 aarch64_gdb_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
1969 info
->symbols
= NULL
;
1970 return default_print_insn (memaddr
, info
);
1973 /* AArch64 BRK software debug mode instruction.
1974 Note that AArch64 code is always little-endian.
1975 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
1976 constexpr gdb_byte aarch64_default_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
1978 typedef BP_MANIPULATION (aarch64_default_breakpoint
) aarch64_breakpoint
;
1980 /* Extract from an array REGS containing the (raw) register state a
1981 function return value of type TYPE, and copy that, in virtual
1982 format, into VALBUF. */
1985 aarch64_extract_return_value (struct type
*type
, struct regcache
*regs
,
1988 struct gdbarch
*gdbarch
= regs
->arch ();
1989 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1991 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1993 bfd_byte buf
[V_REGISTER_SIZE
];
1994 int len
= TYPE_LENGTH (type
);
1996 regs
->cooked_read (AARCH64_V0_REGNUM
, buf
);
1997 memcpy (valbuf
, buf
, len
);
1999 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2000 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2001 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2002 || TYPE_CODE (type
) == TYPE_CODE_PTR
2003 || TYPE_IS_REFERENCE (type
)
2004 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2006 /* If the the type is a plain integer, then the access is
2007 straight-forward. Otherwise we have to play around a bit
2009 int len
= TYPE_LENGTH (type
);
2010 int regno
= AARCH64_X0_REGNUM
;
2015 /* By using store_unsigned_integer we avoid having to do
2016 anything special for small big-endian values. */
2017 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2018 store_unsigned_integer (valbuf
,
2019 (len
> X_REGISTER_SIZE
2020 ? X_REGISTER_SIZE
: len
), byte_order
, tmp
);
2021 len
-= X_REGISTER_SIZE
;
2022 valbuf
+= X_REGISTER_SIZE
;
2025 else if (TYPE_CODE (type
) == TYPE_CODE_COMPLEX
)
2027 int regno
= AARCH64_V0_REGNUM
;
2028 bfd_byte buf
[V_REGISTER_SIZE
];
2029 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
2030 int len
= TYPE_LENGTH (target_type
);
2032 regs
->cooked_read (regno
, buf
);
2033 memcpy (valbuf
, buf
, len
);
2035 regs
->cooked_read (regno
+ 1, buf
);
2036 memcpy (valbuf
, buf
, len
);
2039 else if (is_hfa_or_hva (type
))
2041 int elements
= TYPE_NFIELDS (type
);
2042 struct type
*member_type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2043 int len
= TYPE_LENGTH (member_type
);
2046 for (i
= 0; i
< elements
; i
++)
2048 int regno
= AARCH64_V0_REGNUM
+ i
;
2049 bfd_byte buf
[V_REGISTER_SIZE
];
2053 debug_printf ("read HFA or HVA return value element %d from %s\n",
2055 gdbarch_register_name (gdbarch
, regno
));
2057 regs
->cooked_read (regno
, buf
);
2059 memcpy (valbuf
, buf
, len
);
2063 else if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)
2064 && (TYPE_LENGTH (type
) == 16 || TYPE_LENGTH (type
) == 8))
2066 /* Short vector is returned in V register. */
2067 gdb_byte buf
[V_REGISTER_SIZE
];
2069 regs
->cooked_read (AARCH64_V0_REGNUM
, buf
);
2070 memcpy (valbuf
, buf
, TYPE_LENGTH (type
));
2074 /* For a structure or union the behaviour is as if the value had
2075 been stored to word-aligned memory and then loaded into
2076 registers with 64-bit load instruction(s). */
2077 int len
= TYPE_LENGTH (type
);
2078 int regno
= AARCH64_X0_REGNUM
;
2079 bfd_byte buf
[X_REGISTER_SIZE
];
2083 regs
->cooked_read (regno
++, buf
);
2084 memcpy (valbuf
, buf
, len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2085 len
-= X_REGISTER_SIZE
;
2086 valbuf
+= X_REGISTER_SIZE
;
2092 /* Will a function return an aggregate type in memory or in a
2093 register? Return 0 if an aggregate type can be returned in a
2094 register, 1 if it must be returned in memory. */
2097 aarch64_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2099 type
= check_typedef (type
);
2101 if (is_hfa_or_hva (type
))
2103 /* v0-v7 are used to return values and one register is allocated
2104 for one member. However, HFA or HVA has at most four members. */
2108 if (TYPE_LENGTH (type
) > 16)
2110 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2111 invisible reference. */
2119 /* Write into appropriate registers a function return value of type
2120 TYPE, given in virtual format. */
2123 aarch64_store_return_value (struct type
*type
, struct regcache
*regs
,
2124 const gdb_byte
*valbuf
)
2126 struct gdbarch
*gdbarch
= regs
->arch ();
2127 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2129 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2131 bfd_byte buf
[V_REGISTER_SIZE
];
2132 int len
= TYPE_LENGTH (type
);
2134 memcpy (buf
, valbuf
, len
> V_REGISTER_SIZE
? V_REGISTER_SIZE
: len
);
2135 regs
->cooked_write (AARCH64_V0_REGNUM
, buf
);
2137 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2138 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2139 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2140 || TYPE_CODE (type
) == TYPE_CODE_PTR
2141 || TYPE_IS_REFERENCE (type
)
2142 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2144 if (TYPE_LENGTH (type
) <= X_REGISTER_SIZE
)
2146 /* Values of one word or less are zero/sign-extended and
2148 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2149 LONGEST val
= unpack_long (type
, valbuf
);
2151 store_signed_integer (tmpbuf
, X_REGISTER_SIZE
, byte_order
, val
);
2152 regs
->cooked_write (AARCH64_X0_REGNUM
, tmpbuf
);
2156 /* Integral values greater than one word are stored in
2157 consecutive registers starting with r0. This will always
2158 be a multiple of the regiser size. */
2159 int len
= TYPE_LENGTH (type
);
2160 int regno
= AARCH64_X0_REGNUM
;
2164 regs
->cooked_write (regno
++, valbuf
);
2165 len
-= X_REGISTER_SIZE
;
2166 valbuf
+= X_REGISTER_SIZE
;
2170 else if (is_hfa_or_hva (type
))
2172 int elements
= TYPE_NFIELDS (type
);
2173 struct type
*member_type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2174 int len
= TYPE_LENGTH (member_type
);
2177 for (i
= 0; i
< elements
; i
++)
2179 int regno
= AARCH64_V0_REGNUM
+ i
;
2180 bfd_byte tmpbuf
[V_REGISTER_SIZE
];
2184 debug_printf ("write HFA or HVA return value element %d to %s\n",
2186 gdbarch_register_name (gdbarch
, regno
));
2189 memcpy (tmpbuf
, valbuf
, len
);
2190 regs
->cooked_write (regno
, tmpbuf
);
2194 else if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)
2195 && (TYPE_LENGTH (type
) == 8 || TYPE_LENGTH (type
) == 16))
2198 gdb_byte buf
[V_REGISTER_SIZE
];
2200 memcpy (buf
, valbuf
, TYPE_LENGTH (type
));
2201 regs
->cooked_write (AARCH64_V0_REGNUM
, buf
);
2205 /* For a structure or union the behaviour is as if the value had
2206 been stored to word-aligned memory and then loaded into
2207 registers with 64-bit load instruction(s). */
2208 int len
= TYPE_LENGTH (type
);
2209 int regno
= AARCH64_X0_REGNUM
;
2210 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2214 memcpy (tmpbuf
, valbuf
,
2215 len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2216 regs
->cooked_write (regno
++, tmpbuf
);
2217 len
-= X_REGISTER_SIZE
;
2218 valbuf
+= X_REGISTER_SIZE
;
2223 /* Implement the "return_value" gdbarch method. */
2225 static enum return_value_convention
2226 aarch64_return_value (struct gdbarch
*gdbarch
, struct value
*func_value
,
2227 struct type
*valtype
, struct regcache
*regcache
,
2228 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2231 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2232 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2233 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2235 if (aarch64_return_in_memory (gdbarch
, valtype
))
2238 debug_printf ("return value in memory\n");
2239 return RETURN_VALUE_STRUCT_CONVENTION
;
2244 aarch64_store_return_value (valtype
, regcache
, writebuf
);
2247 aarch64_extract_return_value (valtype
, regcache
, readbuf
);
2250 debug_printf ("return value in registers\n");
2252 return RETURN_VALUE_REGISTER_CONVENTION
;
2255 /* Implement the "get_longjmp_target" gdbarch method. */
2258 aarch64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2261 gdb_byte buf
[X_REGISTER_SIZE
];
2262 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2263 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2264 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2266 jb_addr
= get_frame_register_unsigned (frame
, AARCH64_X0_REGNUM
);
2268 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2272 *pc
= extract_unsigned_integer (buf
, X_REGISTER_SIZE
, byte_order
);
2276 /* Implement the "gen_return_address" gdbarch method. */
2279 aarch64_gen_return_address (struct gdbarch
*gdbarch
,
2280 struct agent_expr
*ax
, struct axs_value
*value
,
2283 value
->type
= register_type (gdbarch
, AARCH64_LR_REGNUM
);
2284 value
->kind
= axs_lvalue_register
;
2285 value
->u
.reg
= AARCH64_LR_REGNUM
;
2289 /* Return the pseudo register name corresponding to register regnum. */
2292 aarch64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
2294 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2296 static const char *const q_name
[] =
2298 "q0", "q1", "q2", "q3",
2299 "q4", "q5", "q6", "q7",
2300 "q8", "q9", "q10", "q11",
2301 "q12", "q13", "q14", "q15",
2302 "q16", "q17", "q18", "q19",
2303 "q20", "q21", "q22", "q23",
2304 "q24", "q25", "q26", "q27",
2305 "q28", "q29", "q30", "q31",
2308 static const char *const d_name
[] =
2310 "d0", "d1", "d2", "d3",
2311 "d4", "d5", "d6", "d7",
2312 "d8", "d9", "d10", "d11",
2313 "d12", "d13", "d14", "d15",
2314 "d16", "d17", "d18", "d19",
2315 "d20", "d21", "d22", "d23",
2316 "d24", "d25", "d26", "d27",
2317 "d28", "d29", "d30", "d31",
2320 static const char *const s_name
[] =
2322 "s0", "s1", "s2", "s3",
2323 "s4", "s5", "s6", "s7",
2324 "s8", "s9", "s10", "s11",
2325 "s12", "s13", "s14", "s15",
2326 "s16", "s17", "s18", "s19",
2327 "s20", "s21", "s22", "s23",
2328 "s24", "s25", "s26", "s27",
2329 "s28", "s29", "s30", "s31",
2332 static const char *const h_name
[] =
2334 "h0", "h1", "h2", "h3",
2335 "h4", "h5", "h6", "h7",
2336 "h8", "h9", "h10", "h11",
2337 "h12", "h13", "h14", "h15",
2338 "h16", "h17", "h18", "h19",
2339 "h20", "h21", "h22", "h23",
2340 "h24", "h25", "h26", "h27",
2341 "h28", "h29", "h30", "h31",
2344 static const char *const b_name
[] =
2346 "b0", "b1", "b2", "b3",
2347 "b4", "b5", "b6", "b7",
2348 "b8", "b9", "b10", "b11",
2349 "b12", "b13", "b14", "b15",
2350 "b16", "b17", "b18", "b19",
2351 "b20", "b21", "b22", "b23",
2352 "b24", "b25", "b26", "b27",
2353 "b28", "b29", "b30", "b31",
2356 regnum
-= gdbarch_num_regs (gdbarch
);
2358 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2359 return q_name
[regnum
- AARCH64_Q0_REGNUM
];
2361 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2362 return d_name
[regnum
- AARCH64_D0_REGNUM
];
2364 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2365 return s_name
[regnum
- AARCH64_S0_REGNUM
];
2367 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2368 return h_name
[regnum
- AARCH64_H0_REGNUM
];
2370 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2371 return b_name
[regnum
- AARCH64_B0_REGNUM
];
2373 if (tdep
->has_sve ())
2375 static const char *const sve_v_name
[] =
2377 "v0", "v1", "v2", "v3",
2378 "v4", "v5", "v6", "v7",
2379 "v8", "v9", "v10", "v11",
2380 "v12", "v13", "v14", "v15",
2381 "v16", "v17", "v18", "v19",
2382 "v20", "v21", "v22", "v23",
2383 "v24", "v25", "v26", "v27",
2384 "v28", "v29", "v30", "v31",
2387 if (regnum
>= AARCH64_SVE_V0_REGNUM
2388 && regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2389 return sve_v_name
[regnum
- AARCH64_SVE_V0_REGNUM
];
2392 internal_error (__FILE__
, __LINE__
,
2393 _("aarch64_pseudo_register_name: bad register number %d"),
2397 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2399 static struct type
*
2400 aarch64_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2402 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2404 regnum
-= gdbarch_num_regs (gdbarch
);
2406 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2407 return aarch64_vnq_type (gdbarch
);
2409 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2410 return aarch64_vnd_type (gdbarch
);
2412 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2413 return aarch64_vns_type (gdbarch
);
2415 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2416 return aarch64_vnh_type (gdbarch
);
2418 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2419 return aarch64_vnb_type (gdbarch
);
2421 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2422 && regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2423 return aarch64_vnv_type (gdbarch
);
2425 internal_error (__FILE__
, __LINE__
,
2426 _("aarch64_pseudo_register_type: bad register number %d"),
2430 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2433 aarch64_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2434 struct reggroup
*group
)
2436 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2438 regnum
-= gdbarch_num_regs (gdbarch
);
2440 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2441 return group
== all_reggroup
|| group
== vector_reggroup
;
2442 else if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2443 return (group
== all_reggroup
|| group
== vector_reggroup
2444 || group
== float_reggroup
);
2445 else if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2446 return (group
== all_reggroup
|| group
== vector_reggroup
2447 || group
== float_reggroup
);
2448 else if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2449 return group
== all_reggroup
|| group
== vector_reggroup
;
2450 else if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2451 return group
== all_reggroup
|| group
== vector_reggroup
;
2452 else if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2453 && regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2454 return group
== all_reggroup
|| group
== vector_reggroup
;
2456 return group
== all_reggroup
;
2459 /* Helper for aarch64_pseudo_read_value. */
2461 static struct value
*
2462 aarch64_pseudo_read_value_1 (struct gdbarch
*gdbarch
,
2463 readable_regcache
*regcache
, int regnum_offset
,
2464 int regsize
, struct value
*result_value
)
2466 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2468 /* Enough space for a full vector register. */
2469 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2470 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2472 if (regcache
->raw_read (v_regnum
, reg_buf
) != REG_VALID
)
2473 mark_value_bytes_unavailable (result_value
, 0,
2474 TYPE_LENGTH (value_type (result_value
)));
2476 memcpy (value_contents_raw (result_value
), reg_buf
, regsize
);
2478 return result_value
;
2481 /* Implement the "pseudo_register_read_value" gdbarch method. */
2483 static struct value
*
2484 aarch64_pseudo_read_value (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2487 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2488 struct value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
2490 VALUE_LVAL (result_value
) = lval_register
;
2491 VALUE_REGNUM (result_value
) = regnum
;
2493 regnum
-= gdbarch_num_regs (gdbarch
);
2495 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2496 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2497 regnum
- AARCH64_Q0_REGNUM
,
2498 Q_REGISTER_SIZE
, result_value
);
2500 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2501 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2502 regnum
- AARCH64_D0_REGNUM
,
2503 D_REGISTER_SIZE
, result_value
);
2505 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2506 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2507 regnum
- AARCH64_S0_REGNUM
,
2508 S_REGISTER_SIZE
, result_value
);
2510 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2511 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2512 regnum
- AARCH64_H0_REGNUM
,
2513 H_REGISTER_SIZE
, result_value
);
2515 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2516 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2517 regnum
- AARCH64_B0_REGNUM
,
2518 B_REGISTER_SIZE
, result_value
);
2520 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2521 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2522 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2523 regnum
- AARCH64_SVE_V0_REGNUM
,
2524 V_REGISTER_SIZE
, result_value
);
2526 gdb_assert_not_reached ("regnum out of bound");
2529 /* Helper for aarch64_pseudo_write. */
2532 aarch64_pseudo_write_1 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2533 int regnum_offset
, int regsize
, const gdb_byte
*buf
)
2535 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2537 /* Enough space for a full vector register. */
2538 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2539 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2541 /* Ensure the register buffer is zero, we want gdb writes of the
2542 various 'scalar' pseudo registers to behavior like architectural
2543 writes, register width bytes are written the remainder are set to
2545 memset (reg_buf
, 0, register_size (gdbarch
, AARCH64_V0_REGNUM
));
2547 memcpy (reg_buf
, buf
, regsize
);
2548 regcache
->raw_write (v_regnum
, reg_buf
);
2551 /* Implement the "pseudo_register_write" gdbarch method. */
2554 aarch64_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2555 int regnum
, const gdb_byte
*buf
)
2557 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2558 regnum
-= gdbarch_num_regs (gdbarch
);
2560 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2561 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2562 regnum
- AARCH64_Q0_REGNUM
, Q_REGISTER_SIZE
,
2565 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2566 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2567 regnum
- AARCH64_D0_REGNUM
, D_REGISTER_SIZE
,
2570 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2571 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2572 regnum
- AARCH64_S0_REGNUM
, S_REGISTER_SIZE
,
2575 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2576 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2577 regnum
- AARCH64_H0_REGNUM
, H_REGISTER_SIZE
,
2580 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2581 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2582 regnum
- AARCH64_B0_REGNUM
, B_REGISTER_SIZE
,
2585 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2586 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2587 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2588 regnum
- AARCH64_SVE_V0_REGNUM
,
2589 V_REGISTER_SIZE
, buf
);
2591 gdb_assert_not_reached ("regnum out of bound");
2594 /* Callback function for user_reg_add. */
2596 static struct value
*
2597 value_of_aarch64_user_reg (struct frame_info
*frame
, const void *baton
)
2599 const int *reg_p
= (const int *) baton
;
2601 return value_of_register (*reg_p
, frame
);
2605 /* Implement the "software_single_step" gdbarch method, needed to
2606 single step through atomic sequences on AArch64. */
2608 static std::vector
<CORE_ADDR
>
2609 aarch64_software_single_step (struct regcache
*regcache
)
2611 struct gdbarch
*gdbarch
= regcache
->arch ();
2612 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2613 const int insn_size
= 4;
2614 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2615 CORE_ADDR pc
= regcache_read_pc (regcache
);
2616 CORE_ADDR breaks
[2] = { CORE_ADDR_MAX
, CORE_ADDR_MAX
};
2618 CORE_ADDR closing_insn
= 0;
2619 uint32_t insn
= read_memory_unsigned_integer (loc
, insn_size
,
2620 byte_order_for_code
);
2623 int bc_insn_count
= 0; /* Conditional branch instruction count. */
2624 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2627 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2630 /* Look for a Load Exclusive instruction which begins the sequence. */
2631 if (inst
.opcode
->iclass
!= ldstexcl
|| bit (insn
, 22) == 0)
2634 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2637 insn
= read_memory_unsigned_integer (loc
, insn_size
,
2638 byte_order_for_code
);
2640 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2642 /* Check if the instruction is a conditional branch. */
2643 if (inst
.opcode
->iclass
== condbranch
)
2645 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_ADDR_PCREL19
);
2647 if (bc_insn_count
>= 1)
2650 /* It is, so we'll try to set a breakpoint at the destination. */
2651 breaks
[1] = loc
+ inst
.operands
[0].imm
.value
;
2657 /* Look for the Store Exclusive which closes the atomic sequence. */
2658 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22) == 0)
2665 /* We didn't find a closing Store Exclusive instruction, fall back. */
2669 /* Insert breakpoint after the end of the atomic sequence. */
2670 breaks
[0] = loc
+ insn_size
;
2672 /* Check for duplicated breakpoints, and also check that the second
2673 breakpoint is not within the atomic sequence. */
2675 && (breaks
[1] == breaks
[0]
2676 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
2677 last_breakpoint
= 0;
2679 std::vector
<CORE_ADDR
> next_pcs
;
2681 /* Insert the breakpoint at the end of the sequence, and one at the
2682 destination of the conditional branch, if it exists. */
2683 for (index
= 0; index
<= last_breakpoint
; index
++)
2684 next_pcs
.push_back (breaks
[index
]);
2689 struct aarch64_displaced_step_closure
: public displaced_step_closure
2691 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2692 is being displaced stepping. */
2695 /* PC adjustment offset after displaced stepping. */
2696 int32_t pc_adjust
= 0;
2699 /* Data when visiting instructions for displaced stepping. */
2701 struct aarch64_displaced_step_data
2703 struct aarch64_insn_data base
;
2705 /* The address where the instruction will be executed at. */
2707 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2708 uint32_t insn_buf
[DISPLACED_MODIFIED_INSNS
];
2709 /* Number of instructions in INSN_BUF. */
2710 unsigned insn_count
;
2711 /* Registers when doing displaced stepping. */
2712 struct regcache
*regs
;
2714 aarch64_displaced_step_closure
*dsc
;
2717 /* Implementation of aarch64_insn_visitor method "b". */
2720 aarch64_displaced_step_b (const int is_bl
, const int32_t offset
,
2721 struct aarch64_insn_data
*data
)
2723 struct aarch64_displaced_step_data
*dsd
2724 = (struct aarch64_displaced_step_data
*) data
;
2725 int64_t new_offset
= data
->insn_addr
- dsd
->new_addr
+ offset
;
2727 if (can_encode_int32 (new_offset
, 28))
2729 /* Emit B rather than BL, because executing BL on a new address
2730 will get the wrong address into LR. In order to avoid this,
2731 we emit B, and update LR if the instruction is BL. */
2732 emit_b (dsd
->insn_buf
, 0, new_offset
);
2738 emit_nop (dsd
->insn_buf
);
2740 dsd
->dsc
->pc_adjust
= offset
;
2746 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
2747 data
->insn_addr
+ 4);
2751 /* Implementation of aarch64_insn_visitor method "b_cond". */
2754 aarch64_displaced_step_b_cond (const unsigned cond
, const int32_t offset
,
2755 struct aarch64_insn_data
*data
)
2757 struct aarch64_displaced_step_data
*dsd
2758 = (struct aarch64_displaced_step_data
*) data
;
2760 /* GDB has to fix up PC after displaced step this instruction
2761 differently according to the condition is true or false. Instead
2762 of checking COND against conditional flags, we can use
2763 the following instructions, and GDB can tell how to fix up PC
2764 according to the PC value.
2766 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2772 emit_bcond (dsd
->insn_buf
, cond
, 8);
2774 dsd
->dsc
->pc_adjust
= offset
;
2775 dsd
->insn_count
= 1;
2778 /* Dynamically allocate a new register. If we know the register
2779 statically, we should make it a global as above instead of using this
2782 static struct aarch64_register
2783 aarch64_register (unsigned num
, int is64
)
2785 return (struct aarch64_register
) { num
, is64
};
2788 /* Implementation of aarch64_insn_visitor method "cb". */
2791 aarch64_displaced_step_cb (const int32_t offset
, const int is_cbnz
,
2792 const unsigned rn
, int is64
,
2793 struct aarch64_insn_data
*data
)
2795 struct aarch64_displaced_step_data
*dsd
2796 = (struct aarch64_displaced_step_data
*) data
;
2798 /* The offset is out of range for a compare and branch
2799 instruction. We can use the following instructions instead:
2801 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2806 emit_cb (dsd
->insn_buf
, is_cbnz
, aarch64_register (rn
, is64
), 8);
2807 dsd
->insn_count
= 1;
2809 dsd
->dsc
->pc_adjust
= offset
;
2812 /* Implementation of aarch64_insn_visitor method "tb". */
2815 aarch64_displaced_step_tb (const int32_t offset
, int is_tbnz
,
2816 const unsigned rt
, unsigned bit
,
2817 struct aarch64_insn_data
*data
)
2819 struct aarch64_displaced_step_data
*dsd
2820 = (struct aarch64_displaced_step_data
*) data
;
2822 /* The offset is out of range for a test bit and branch
2823 instruction We can use the following instructions instead:
2825 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2831 emit_tb (dsd
->insn_buf
, is_tbnz
, bit
, aarch64_register (rt
, 1), 8);
2832 dsd
->insn_count
= 1;
2834 dsd
->dsc
->pc_adjust
= offset
;
2837 /* Implementation of aarch64_insn_visitor method "adr". */
2840 aarch64_displaced_step_adr (const int32_t offset
, const unsigned rd
,
2841 const int is_adrp
, struct aarch64_insn_data
*data
)
2843 struct aarch64_displaced_step_data
*dsd
2844 = (struct aarch64_displaced_step_data
*) data
;
2845 /* We know exactly the address the ADR{P,} instruction will compute.
2846 We can just write it to the destination register. */
2847 CORE_ADDR address
= data
->insn_addr
+ offset
;
2851 /* Clear the lower 12 bits of the offset to get the 4K page. */
2852 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2856 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2859 dsd
->dsc
->pc_adjust
= 4;
2860 emit_nop (dsd
->insn_buf
);
2861 dsd
->insn_count
= 1;
2864 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2867 aarch64_displaced_step_ldr_literal (const int32_t offset
, const int is_sw
,
2868 const unsigned rt
, const int is64
,
2869 struct aarch64_insn_data
*data
)
2871 struct aarch64_displaced_step_data
*dsd
2872 = (struct aarch64_displaced_step_data
*) data
;
2873 CORE_ADDR address
= data
->insn_addr
+ offset
;
2874 struct aarch64_memory_operand zero
= { MEMORY_OPERAND_OFFSET
, 0 };
2876 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rt
,
2880 dsd
->insn_count
= emit_ldrsw (dsd
->insn_buf
, aarch64_register (rt
, 1),
2881 aarch64_register (rt
, 1), zero
);
2883 dsd
->insn_count
= emit_ldr (dsd
->insn_buf
, aarch64_register (rt
, is64
),
2884 aarch64_register (rt
, 1), zero
);
2886 dsd
->dsc
->pc_adjust
= 4;
2889 /* Implementation of aarch64_insn_visitor method "others". */
2892 aarch64_displaced_step_others (const uint32_t insn
,
2893 struct aarch64_insn_data
*data
)
2895 struct aarch64_displaced_step_data
*dsd
2896 = (struct aarch64_displaced_step_data
*) data
;
2898 aarch64_emit_insn (dsd
->insn_buf
, insn
);
2899 dsd
->insn_count
= 1;
2901 if ((insn
& 0xfffffc1f) == 0xd65f0000)
2904 dsd
->dsc
->pc_adjust
= 0;
2907 dsd
->dsc
->pc_adjust
= 4;
2910 static const struct aarch64_insn_visitor visitor
=
2912 aarch64_displaced_step_b
,
2913 aarch64_displaced_step_b_cond
,
2914 aarch64_displaced_step_cb
,
2915 aarch64_displaced_step_tb
,
2916 aarch64_displaced_step_adr
,
2917 aarch64_displaced_step_ldr_literal
,
2918 aarch64_displaced_step_others
,
2921 /* Implement the "displaced_step_copy_insn" gdbarch method. */
2923 struct displaced_step_closure
*
2924 aarch64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
2925 CORE_ADDR from
, CORE_ADDR to
,
2926 struct regcache
*regs
)
2928 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2929 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
2930 struct aarch64_displaced_step_data dsd
;
2933 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2936 /* Look for a Load Exclusive instruction which begins the sequence. */
2937 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22))
2939 /* We can't displaced step atomic sequences. */
2943 std::unique_ptr
<aarch64_displaced_step_closure
> dsc
2944 (new aarch64_displaced_step_closure
);
2945 dsd
.base
.insn_addr
= from
;
2948 dsd
.dsc
= dsc
.get ();
2950 aarch64_relocate_instruction (insn
, &visitor
,
2951 (struct aarch64_insn_data
*) &dsd
);
2952 gdb_assert (dsd
.insn_count
<= DISPLACED_MODIFIED_INSNS
);
2954 if (dsd
.insn_count
!= 0)
2958 /* Instruction can be relocated to scratch pad. Copy
2959 relocated instruction(s) there. */
2960 for (i
= 0; i
< dsd
.insn_count
; i
++)
2962 if (debug_displaced
)
2964 debug_printf ("displaced: writing insn ");
2965 debug_printf ("%.8x", dsd
.insn_buf
[i
]);
2966 debug_printf (" at %s\n", paddress (gdbarch
, to
+ i
* 4));
2968 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
2969 (ULONGEST
) dsd
.insn_buf
[i
]);
2977 return dsc
.release ();
2980 /* Implement the "displaced_step_fixup" gdbarch method. */
2983 aarch64_displaced_step_fixup (struct gdbarch
*gdbarch
,
2984 struct displaced_step_closure
*dsc_
,
2985 CORE_ADDR from
, CORE_ADDR to
,
2986 struct regcache
*regs
)
2988 aarch64_displaced_step_closure
*dsc
= (aarch64_displaced_step_closure
*) dsc_
;
2994 regcache_cooked_read_unsigned (regs
, AARCH64_PC_REGNUM
, &pc
);
2997 /* Condition is true. */
2999 else if (pc
- to
== 4)
3001 /* Condition is false. */
3005 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
3008 if (dsc
->pc_adjust
!= 0)
3010 if (debug_displaced
)
3012 debug_printf ("displaced: fixup: set PC to %s:%d\n",
3013 paddress (gdbarch
, from
), dsc
->pc_adjust
);
3015 regcache_cooked_write_unsigned (regs
, AARCH64_PC_REGNUM
,
3016 from
+ dsc
->pc_adjust
);
3020 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3023 aarch64_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
3024 struct displaced_step_closure
*closure
)
3029 /* Get the correct target description for the given VQ value.
3030 If VQ is zero then it is assumed SVE is not supported.
3031 (It is not possible to set VQ to zero on an SVE system). */
3034 aarch64_read_description (uint64_t vq
)
3036 if (vq
> AARCH64_MAX_SVE_VQ
)
3037 error (_("VQ is %" PRIu64
", maximum supported value is %d"), vq
,
3038 AARCH64_MAX_SVE_VQ
);
3040 struct target_desc
*tdesc
= tdesc_aarch64_list
[vq
];
3044 tdesc
= aarch64_create_target_description (vq
);
3045 tdesc_aarch64_list
[vq
] = tdesc
;
3051 /* Return the VQ used when creating the target description TDESC. */
3054 aarch64_get_tdesc_vq (const struct target_desc
*tdesc
)
3056 const struct tdesc_feature
*feature_sve
;
3058 if (!tdesc_has_registers (tdesc
))
3061 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3063 if (feature_sve
== nullptr)
3066 uint64_t vl
= tdesc_register_bitsize (feature_sve
,
3067 aarch64_sve_register_names
[0]) / 8;
3068 return sve_vq_from_vl (vl
);
3072 /* Initialize the current architecture based on INFO. If possible,
3073 re-use an architecture from ARCHES, which is a list of
3074 architectures already created during this debugging session.
3076 Called e.g. at program startup, when reading a core file, and when
3077 reading a binary file. */
3079 static struct gdbarch
*
3080 aarch64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3082 struct gdbarch_tdep
*tdep
;
3083 struct gdbarch
*gdbarch
;
3084 struct gdbarch_list
*best_arch
;
3085 struct tdesc_arch_data
*tdesc_data
= NULL
;
3086 const struct target_desc
*tdesc
= info
.target_desc
;
3089 const struct tdesc_feature
*feature_core
;
3090 const struct tdesc_feature
*feature_fpu
;
3091 const struct tdesc_feature
*feature_sve
;
3093 int num_pseudo_regs
= 0;
3095 /* Ensure we always have a target description. */
3096 if (!tdesc_has_registers (tdesc
))
3097 tdesc
= aarch64_read_description (0);
3100 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.core");
3101 feature_fpu
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.fpu");
3102 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3104 if (feature_core
== NULL
)
3107 tdesc_data
= tdesc_data_alloc ();
3109 /* Validate the description provides the mandatory core R registers
3110 and allocate their numbers. */
3111 for (i
= 0; i
< ARRAY_SIZE (aarch64_r_register_names
); i
++)
3112 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
,
3113 AARCH64_X0_REGNUM
+ i
,
3114 aarch64_r_register_names
[i
]);
3116 num_regs
= AARCH64_X0_REGNUM
+ i
;
3118 /* Add the V registers. */
3119 if (feature_fpu
!= NULL
)
3121 if (feature_sve
!= NULL
)
3122 error (_("Program contains both fpu and SVE features."));
3124 /* Validate the description provides the mandatory V registers
3125 and allocate their numbers. */
3126 for (i
= 0; i
< ARRAY_SIZE (aarch64_v_register_names
); i
++)
3127 valid_p
&= tdesc_numbered_register (feature_fpu
, tdesc_data
,
3128 AARCH64_V0_REGNUM
+ i
,
3129 aarch64_v_register_names
[i
]);
3131 num_regs
= AARCH64_V0_REGNUM
+ i
;
3134 /* Add the SVE registers. */
3135 if (feature_sve
!= NULL
)
3137 /* Validate the description provides the mandatory SVE registers
3138 and allocate their numbers. */
3139 for (i
= 0; i
< ARRAY_SIZE (aarch64_sve_register_names
); i
++)
3140 valid_p
&= tdesc_numbered_register (feature_sve
, tdesc_data
,
3141 AARCH64_SVE_Z0_REGNUM
+ i
,
3142 aarch64_sve_register_names
[i
]);
3144 num_regs
= AARCH64_SVE_Z0_REGNUM
+ i
;
3145 num_pseudo_regs
+= 32; /* add the Vn register pseudos. */
3148 if (feature_fpu
!= NULL
|| feature_sve
!= NULL
)
3150 num_pseudo_regs
+= 32; /* add the Qn scalar register pseudos */
3151 num_pseudo_regs
+= 32; /* add the Dn scalar register pseudos */
3152 num_pseudo_regs
+= 32; /* add the Sn scalar register pseudos */
3153 num_pseudo_regs
+= 32; /* add the Hn scalar register pseudos */
3154 num_pseudo_regs
+= 32; /* add the Bn scalar register pseudos */
3159 tdesc_data_cleanup (tdesc_data
);
3163 /* AArch64 code is always little-endian. */
3164 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
3166 /* If there is already a candidate, use it. */
3167 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3169 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3171 /* Found a match. */
3175 if (best_arch
!= NULL
)
3177 if (tdesc_data
!= NULL
)
3178 tdesc_data_cleanup (tdesc_data
);
3179 return best_arch
->gdbarch
;
3182 tdep
= XCNEW (struct gdbarch_tdep
);
3183 gdbarch
= gdbarch_alloc (&info
, tdep
);
3185 /* This should be low enough for everything. */
3186 tdep
->lowest_pc
= 0x20;
3187 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3188 tdep
->jb_elt_size
= 8;
3189 tdep
->vq
= aarch64_get_tdesc_vq (tdesc
);
3191 set_gdbarch_push_dummy_call (gdbarch
, aarch64_push_dummy_call
);
3192 set_gdbarch_frame_align (gdbarch
, aarch64_frame_align
);
3194 /* Frame handling. */
3195 set_gdbarch_dummy_id (gdbarch
, aarch64_dummy_id
);
3196 set_gdbarch_unwind_pc (gdbarch
, aarch64_unwind_pc
);
3197 set_gdbarch_unwind_sp (gdbarch
, aarch64_unwind_sp
);
3199 /* Advance PC across function entry code. */
3200 set_gdbarch_skip_prologue (gdbarch
, aarch64_skip_prologue
);
3202 /* The stack grows downward. */
3203 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3205 /* Breakpoint manipulation. */
3206 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3207 aarch64_breakpoint::kind_from_pc
);
3208 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3209 aarch64_breakpoint::bp_from_kind
);
3210 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3211 set_gdbarch_software_single_step (gdbarch
, aarch64_software_single_step
);
3213 /* Information about registers, etc. */
3214 set_gdbarch_sp_regnum (gdbarch
, AARCH64_SP_REGNUM
);
3215 set_gdbarch_pc_regnum (gdbarch
, AARCH64_PC_REGNUM
);
3216 set_gdbarch_num_regs (gdbarch
, num_regs
);
3218 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3219 set_gdbarch_pseudo_register_read_value (gdbarch
, aarch64_pseudo_read_value
);
3220 set_gdbarch_pseudo_register_write (gdbarch
, aarch64_pseudo_write
);
3221 set_tdesc_pseudo_register_name (gdbarch
, aarch64_pseudo_register_name
);
3222 set_tdesc_pseudo_register_type (gdbarch
, aarch64_pseudo_register_type
);
3223 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3224 aarch64_pseudo_register_reggroup_p
);
3227 set_gdbarch_short_bit (gdbarch
, 16);
3228 set_gdbarch_int_bit (gdbarch
, 32);
3229 set_gdbarch_float_bit (gdbarch
, 32);
3230 set_gdbarch_double_bit (gdbarch
, 64);
3231 set_gdbarch_long_double_bit (gdbarch
, 128);
3232 set_gdbarch_long_bit (gdbarch
, 64);
3233 set_gdbarch_long_long_bit (gdbarch
, 64);
3234 set_gdbarch_ptr_bit (gdbarch
, 64);
3235 set_gdbarch_char_signed (gdbarch
, 0);
3236 set_gdbarch_wchar_signed (gdbarch
, 0);
3237 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3238 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3239 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3241 /* Internal <-> external register number maps. */
3242 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, aarch64_dwarf_reg_to_regnum
);
3244 /* Returning results. */
3245 set_gdbarch_return_value (gdbarch
, aarch64_return_value
);
3248 set_gdbarch_print_insn (gdbarch
, aarch64_gdb_print_insn
);
3250 /* Virtual tables. */
3251 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3253 /* Hook in the ABI-specific overrides, if they have been registered. */
3254 info
.target_desc
= tdesc
;
3255 info
.tdesc_data
= tdesc_data
;
3256 gdbarch_init_osabi (info
, gdbarch
);
3258 dwarf2_frame_set_init_reg (gdbarch
, aarch64_dwarf2_frame_init_reg
);
3260 /* Add some default predicates. */
3261 frame_unwind_append_unwinder (gdbarch
, &aarch64_stub_unwind
);
3262 dwarf2_append_unwinders (gdbarch
);
3263 frame_unwind_append_unwinder (gdbarch
, &aarch64_prologue_unwind
);
3265 frame_base_set_default (gdbarch
, &aarch64_normal_base
);
3267 /* Now we have tuned the configuration, set a few final things,
3268 based on what the OS ABI has told us. */
3270 if (tdep
->jb_pc
>= 0)
3271 set_gdbarch_get_longjmp_target (gdbarch
, aarch64_get_longjmp_target
);
3273 set_gdbarch_gen_return_address (gdbarch
, aarch64_gen_return_address
);
3275 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3277 /* Add standard register aliases. */
3278 for (i
= 0; i
< ARRAY_SIZE (aarch64_register_aliases
); i
++)
3279 user_reg_add (gdbarch
, aarch64_register_aliases
[i
].name
,
3280 value_of_aarch64_user_reg
,
3281 &aarch64_register_aliases
[i
].regnum
);
3287 aarch64_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3289 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3294 fprintf_unfiltered (file
, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3295 paddress (gdbarch
, tdep
->lowest_pc
));
3301 static void aarch64_process_record_test (void);
3306 _initialize_aarch64_tdep (void)
3308 gdbarch_register (bfd_arch_aarch64
, aarch64_gdbarch_init
,
3311 /* Debug this file's internals. */
3312 add_setshow_boolean_cmd ("aarch64", class_maintenance
, &aarch64_debug
, _("\
3313 Set AArch64 debugging."), _("\
3314 Show AArch64 debugging."), _("\
3315 When on, AArch64 specific debugging is enabled."),
3318 &setdebuglist
, &showdebuglist
);
3321 selftests::register_test ("aarch64-analyze-prologue",
3322 selftests::aarch64_analyze_prologue_test
);
3323 selftests::register_test ("aarch64-process-record",
3324 selftests::aarch64_process_record_test
);
3325 selftests::record_xml_tdesc ("aarch64.xml",
3326 aarch64_create_target_description (0));
3330 /* AArch64 process record-replay related structures, defines etc. */
3332 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3335 unsigned int reg_len = LENGTH; \
3338 REGS = XNEWVEC (uint32_t, reg_len); \
3339 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3344 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3347 unsigned int mem_len = LENGTH; \
3350 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3351 memcpy(&MEMS->len, &RECORD_BUF[0], \
3352 sizeof(struct aarch64_mem_r) * LENGTH); \
3357 /* AArch64 record/replay structures and enumerations. */
3359 struct aarch64_mem_r
3361 uint64_t len
; /* Record length. */
3362 uint64_t addr
; /* Memory address. */
3365 enum aarch64_record_result
3367 AARCH64_RECORD_SUCCESS
,
3368 AARCH64_RECORD_UNSUPPORTED
,
3369 AARCH64_RECORD_UNKNOWN
3372 typedef struct insn_decode_record_t
3374 struct gdbarch
*gdbarch
;
3375 struct regcache
*regcache
;
3376 CORE_ADDR this_addr
; /* Address of insn to be recorded. */
3377 uint32_t aarch64_insn
; /* Insn to be recorded. */
3378 uint32_t mem_rec_count
; /* Count of memory records. */
3379 uint32_t reg_rec_count
; /* Count of register records. */
3380 uint32_t *aarch64_regs
; /* Registers to be recorded. */
3381 struct aarch64_mem_r
*aarch64_mems
; /* Memory locations to be recorded. */
3382 } insn_decode_record
;
3384 /* Record handler for data processing - register instructions. */
3387 aarch64_record_data_proc_reg (insn_decode_record
*aarch64_insn_r
)
3389 uint8_t reg_rd
, insn_bits24_27
, insn_bits21_23
;
3390 uint32_t record_buf
[4];
3392 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3393 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3394 insn_bits21_23
= bits (aarch64_insn_r
->aarch64_insn
, 21, 23);
3396 if (!bit (aarch64_insn_r
->aarch64_insn
, 28))
3400 /* Logical (shifted register). */
3401 if (insn_bits24_27
== 0x0a)
3402 setflags
= (bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03);
3404 else if (insn_bits24_27
== 0x0b)
3405 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3407 return AARCH64_RECORD_UNKNOWN
;
3409 record_buf
[0] = reg_rd
;
3410 aarch64_insn_r
->reg_rec_count
= 1;
3412 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3416 if (insn_bits24_27
== 0x0b)
3418 /* Data-processing (3 source). */
3419 record_buf
[0] = reg_rd
;
3420 aarch64_insn_r
->reg_rec_count
= 1;
3422 else if (insn_bits24_27
== 0x0a)
3424 if (insn_bits21_23
== 0x00)
3426 /* Add/subtract (with carry). */
3427 record_buf
[0] = reg_rd
;
3428 aarch64_insn_r
->reg_rec_count
= 1;
3429 if (bit (aarch64_insn_r
->aarch64_insn
, 29))
3431 record_buf
[1] = AARCH64_CPSR_REGNUM
;
3432 aarch64_insn_r
->reg_rec_count
= 2;
3435 else if (insn_bits21_23
== 0x02)
3437 /* Conditional compare (register) and conditional compare
3438 (immediate) instructions. */
3439 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3440 aarch64_insn_r
->reg_rec_count
= 1;
3442 else if (insn_bits21_23
== 0x04 || insn_bits21_23
== 0x06)
3444 /* CConditional select. */
3445 /* Data-processing (2 source). */
3446 /* Data-processing (1 source). */
3447 record_buf
[0] = reg_rd
;
3448 aarch64_insn_r
->reg_rec_count
= 1;
3451 return AARCH64_RECORD_UNKNOWN
;
3455 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3457 return AARCH64_RECORD_SUCCESS
;
3460 /* Record handler for data processing - immediate instructions. */
3463 aarch64_record_data_proc_imm (insn_decode_record
*aarch64_insn_r
)
3465 uint8_t reg_rd
, insn_bit23
, insn_bits24_27
, setflags
;
3466 uint32_t record_buf
[4];
3468 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3469 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3470 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3472 if (insn_bits24_27
== 0x00 /* PC rel addressing. */
3473 || insn_bits24_27
== 0x03 /* Bitfield and Extract. */
3474 || (insn_bits24_27
== 0x02 && insn_bit23
)) /* Move wide (immediate). */
3476 record_buf
[0] = reg_rd
;
3477 aarch64_insn_r
->reg_rec_count
= 1;
3479 else if (insn_bits24_27
== 0x01)
3481 /* Add/Subtract (immediate). */
3482 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3483 record_buf
[0] = reg_rd
;
3484 aarch64_insn_r
->reg_rec_count
= 1;
3486 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3488 else if (insn_bits24_27
== 0x02 && !insn_bit23
)
3490 /* Logical (immediate). */
3491 setflags
= bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03;
3492 record_buf
[0] = reg_rd
;
3493 aarch64_insn_r
->reg_rec_count
= 1;
3495 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3498 return AARCH64_RECORD_UNKNOWN
;
3500 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3502 return AARCH64_RECORD_SUCCESS
;
3505 /* Record handler for branch, exception generation and system instructions. */
3508 aarch64_record_branch_except_sys (insn_decode_record
*aarch64_insn_r
)
3510 struct gdbarch_tdep
*tdep
= gdbarch_tdep (aarch64_insn_r
->gdbarch
);
3511 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits22_23
;
3512 uint32_t record_buf
[4];
3514 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3515 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
3516 insn_bits22_23
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3518 if (insn_bits28_31
== 0x0d)
3520 /* Exception generation instructions. */
3521 if (insn_bits24_27
== 0x04)
3523 if (!bits (aarch64_insn_r
->aarch64_insn
, 2, 4)
3524 && !bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
3525 && bits (aarch64_insn_r
->aarch64_insn
, 0, 1) == 0x01)
3527 ULONGEST svc_number
;
3529 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, 8,
3531 return tdep
->aarch64_syscall_record (aarch64_insn_r
->regcache
,
3535 return AARCH64_RECORD_UNSUPPORTED
;
3537 /* System instructions. */
3538 else if (insn_bits24_27
== 0x05 && insn_bits22_23
== 0x00)
3540 uint32_t reg_rt
, reg_crn
;
3542 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3543 reg_crn
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3545 /* Record rt in case of sysl and mrs instructions. */
3546 if (bit (aarch64_insn_r
->aarch64_insn
, 21))
3548 record_buf
[0] = reg_rt
;
3549 aarch64_insn_r
->reg_rec_count
= 1;
3551 /* Record cpsr for hint and msr(immediate) instructions. */
3552 else if (reg_crn
== 0x02 || reg_crn
== 0x04)
3554 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3555 aarch64_insn_r
->reg_rec_count
= 1;
3558 /* Unconditional branch (register). */
3559 else if((insn_bits24_27
& 0x0e) == 0x06)
3561 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3562 if (bits (aarch64_insn_r
->aarch64_insn
, 21, 22) == 0x01)
3563 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3566 return AARCH64_RECORD_UNKNOWN
;
3568 /* Unconditional branch (immediate). */
3569 else if ((insn_bits28_31
& 0x07) == 0x01 && (insn_bits24_27
& 0x0c) == 0x04)
3571 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3572 if (bit (aarch64_insn_r
->aarch64_insn
, 31))
3573 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3576 /* Compare & branch (immediate), Test & branch (immediate) and
3577 Conditional branch (immediate). */
3578 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3580 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3582 return AARCH64_RECORD_SUCCESS
;
3585 /* Record handler for advanced SIMD load and store instructions. */
3588 aarch64_record_asimd_load_store (insn_decode_record
*aarch64_insn_r
)
3591 uint64_t addr_offset
= 0;
3592 uint32_t record_buf
[24];
3593 uint64_t record_buf_mem
[24];
3594 uint32_t reg_rn
, reg_rt
;
3595 uint32_t reg_index
= 0, mem_index
= 0;
3596 uint8_t opcode_bits
, size_bits
;
3598 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3599 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3600 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3601 opcode_bits
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3602 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
, &address
);
3605 debug_printf ("Process record: Advanced SIMD load/store\n");
3607 /* Load/store single structure. */
3608 if (bit (aarch64_insn_r
->aarch64_insn
, 24))
3610 uint8_t sindex
, scale
, selem
, esize
, replicate
= 0;
3611 scale
= opcode_bits
>> 2;
3612 selem
= ((opcode_bits
& 0x02) |
3613 bit (aarch64_insn_r
->aarch64_insn
, 21)) + 1;
3617 if (size_bits
& 0x01)
3618 return AARCH64_RECORD_UNKNOWN
;
3621 if ((size_bits
>> 1) & 0x01)
3622 return AARCH64_RECORD_UNKNOWN
;
3623 if (size_bits
& 0x01)
3625 if (!((opcode_bits
>> 1) & 0x01))
3628 return AARCH64_RECORD_UNKNOWN
;
3632 if (bit (aarch64_insn_r
->aarch64_insn
, 22) && !(opcode_bits
& 0x01))
3639 return AARCH64_RECORD_UNKNOWN
;
3645 for (sindex
= 0; sindex
< selem
; sindex
++)
3647 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3648 reg_rt
= (reg_rt
+ 1) % 32;
3652 for (sindex
= 0; sindex
< selem
; sindex
++)
3654 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3655 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3658 record_buf_mem
[mem_index
++] = esize
/ 8;
3659 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3661 addr_offset
= addr_offset
+ (esize
/ 8);
3662 reg_rt
= (reg_rt
+ 1) % 32;
3666 /* Load/store multiple structure. */
3669 uint8_t selem
, esize
, rpt
, elements
;
3670 uint8_t eindex
, rindex
;
3672 esize
= 8 << size_bits
;
3673 if (bit (aarch64_insn_r
->aarch64_insn
, 30))
3674 elements
= 128 / esize
;
3676 elements
= 64 / esize
;
3678 switch (opcode_bits
)
3680 /*LD/ST4 (4 Registers). */
3685 /*LD/ST1 (4 Registers). */
3690 /*LD/ST3 (3 Registers). */
3695 /*LD/ST1 (3 Registers). */
3700 /*LD/ST1 (1 Register). */
3705 /*LD/ST2 (2 Registers). */
3710 /*LD/ST1 (2 Registers). */
3716 return AARCH64_RECORD_UNSUPPORTED
;
3719 for (rindex
= 0; rindex
< rpt
; rindex
++)
3720 for (eindex
= 0; eindex
< elements
; eindex
++)
3722 uint8_t reg_tt
, sindex
;
3723 reg_tt
= (reg_rt
+ rindex
) % 32;
3724 for (sindex
= 0; sindex
< selem
; sindex
++)
3726 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3727 record_buf
[reg_index
++] = reg_tt
+ AARCH64_V0_REGNUM
;
3730 record_buf_mem
[mem_index
++] = esize
/ 8;
3731 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3733 addr_offset
= addr_offset
+ (esize
/ 8);
3734 reg_tt
= (reg_tt
+ 1) % 32;
3739 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
3740 record_buf
[reg_index
++] = reg_rn
;
3742 aarch64_insn_r
->reg_rec_count
= reg_index
;
3743 aarch64_insn_r
->mem_rec_count
= mem_index
/ 2;
3744 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
3746 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3748 return AARCH64_RECORD_SUCCESS
;
3751 /* Record handler for load and store instructions. */
3754 aarch64_record_load_store (insn_decode_record
*aarch64_insn_r
)
3756 uint8_t insn_bits24_27
, insn_bits28_29
, insn_bits10_11
;
3757 uint8_t insn_bit23
, insn_bit21
;
3758 uint8_t opc
, size_bits
, ld_flag
, vector_flag
;
3759 uint32_t reg_rn
, reg_rt
, reg_rt2
;
3760 uint64_t datasize
, offset
;
3761 uint32_t record_buf
[8];
3762 uint64_t record_buf_mem
[8];
3765 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3766 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3767 insn_bits28_29
= bits (aarch64_insn_r
->aarch64_insn
, 28, 29);
3768 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
3769 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3770 ld_flag
= bit (aarch64_insn_r
->aarch64_insn
, 22);
3771 vector_flag
= bit (aarch64_insn_r
->aarch64_insn
, 26);
3772 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3773 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3774 reg_rt2
= bits (aarch64_insn_r
->aarch64_insn
, 10, 14);
3775 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 30, 31);
3777 /* Load/store exclusive. */
3778 if (insn_bits24_27
== 0x08 && insn_bits28_29
== 0x00)
3781 debug_printf ("Process record: load/store exclusive\n");
3785 record_buf
[0] = reg_rt
;
3786 aarch64_insn_r
->reg_rec_count
= 1;
3789 record_buf
[1] = reg_rt2
;
3790 aarch64_insn_r
->reg_rec_count
= 2;
3796 datasize
= (8 << size_bits
) * 2;
3798 datasize
= (8 << size_bits
);
3799 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3801 record_buf_mem
[0] = datasize
/ 8;
3802 record_buf_mem
[1] = address
;
3803 aarch64_insn_r
->mem_rec_count
= 1;
3806 /* Save register rs. */
3807 record_buf
[0] = bits (aarch64_insn_r
->aarch64_insn
, 16, 20);
3808 aarch64_insn_r
->reg_rec_count
= 1;
3812 /* Load register (literal) instructions decoding. */
3813 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x01)
3816 debug_printf ("Process record: load register (literal)\n");
3818 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3820 record_buf
[0] = reg_rt
;
3821 aarch64_insn_r
->reg_rec_count
= 1;
3823 /* All types of load/store pair instructions decoding. */
3824 else if ((insn_bits24_27
& 0x0a) == 0x08 && insn_bits28_29
== 0x02)
3827 debug_printf ("Process record: load/store pair\n");
3833 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3834 record_buf
[1] = reg_rt2
+ AARCH64_V0_REGNUM
;
3838 record_buf
[0] = reg_rt
;
3839 record_buf
[1] = reg_rt2
;
3841 aarch64_insn_r
->reg_rec_count
= 2;
3846 imm7_off
= bits (aarch64_insn_r
->aarch64_insn
, 15, 21);
3848 size_bits
= size_bits
>> 1;
3849 datasize
= 8 << (2 + size_bits
);
3850 offset
= (imm7_off
& 0x40) ? (~imm7_off
& 0x007f) + 1 : imm7_off
;
3851 offset
= offset
<< (2 + size_bits
);
3852 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3854 if (!((insn_bits24_27
& 0x0b) == 0x08 && insn_bit23
))
3856 if (imm7_off
& 0x40)
3857 address
= address
- offset
;
3859 address
= address
+ offset
;
3862 record_buf_mem
[0] = datasize
/ 8;
3863 record_buf_mem
[1] = address
;
3864 record_buf_mem
[2] = datasize
/ 8;
3865 record_buf_mem
[3] = address
+ (datasize
/ 8);
3866 aarch64_insn_r
->mem_rec_count
= 2;
3868 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
3869 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
3871 /* Load/store register (unsigned immediate) instructions. */
3872 else if ((insn_bits24_27
& 0x0b) == 0x09 && insn_bits28_29
== 0x03)
3874 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3884 if (size_bits
== 0x3 && vector_flag
== 0x0 && opc
== 0x2)
3886 /* PRFM (immediate) */
3887 return AARCH64_RECORD_SUCCESS
;
3889 else if (size_bits
== 0x2 && vector_flag
== 0x0 && opc
== 0x2)
3891 /* LDRSW (immediate) */
3905 debug_printf ("Process record: load/store (unsigned immediate):"
3906 " size %x V %d opc %x\n", size_bits
, vector_flag
,
3912 offset
= bits (aarch64_insn_r
->aarch64_insn
, 10, 21);
3913 datasize
= 8 << size_bits
;
3914 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3916 offset
= offset
<< size_bits
;
3917 address
= address
+ offset
;
3919 record_buf_mem
[0] = datasize
>> 3;
3920 record_buf_mem
[1] = address
;
3921 aarch64_insn_r
->mem_rec_count
= 1;
3926 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3928 record_buf
[0] = reg_rt
;
3929 aarch64_insn_r
->reg_rec_count
= 1;
3932 /* Load/store register (register offset) instructions. */
3933 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
3934 && insn_bits10_11
== 0x02 && insn_bit21
)
3937 debug_printf ("Process record: load/store (register offset)\n");
3938 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3945 if (size_bits
!= 0x03)
3948 return AARCH64_RECORD_UNKNOWN
;
3952 ULONGEST reg_rm_val
;
3954 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
,
3955 bits (aarch64_insn_r
->aarch64_insn
, 16, 20), ®_rm_val
);
3956 if (bit (aarch64_insn_r
->aarch64_insn
, 12))
3957 offset
= reg_rm_val
<< size_bits
;
3959 offset
= reg_rm_val
;
3960 datasize
= 8 << size_bits
;
3961 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3963 address
= address
+ offset
;
3964 record_buf_mem
[0] = datasize
>> 3;
3965 record_buf_mem
[1] = address
;
3966 aarch64_insn_r
->mem_rec_count
= 1;
3971 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3973 record_buf
[0] = reg_rt
;
3974 aarch64_insn_r
->reg_rec_count
= 1;
3977 /* Load/store register (immediate and unprivileged) instructions. */
3978 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
3983 debug_printf ("Process record: load/store "
3984 "(immediate and unprivileged)\n");
3986 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3993 if (size_bits
!= 0x03)
3996 return AARCH64_RECORD_UNKNOWN
;
4001 imm9_off
= bits (aarch64_insn_r
->aarch64_insn
, 12, 20);
4002 offset
= (imm9_off
& 0x0100) ? (((~imm9_off
) & 0x01ff) + 1) : imm9_off
;
4003 datasize
= 8 << size_bits
;
4004 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4006 if (insn_bits10_11
!= 0x01)
4008 if (imm9_off
& 0x0100)
4009 address
= address
- offset
;
4011 address
= address
+ offset
;
4013 record_buf_mem
[0] = datasize
>> 3;
4014 record_buf_mem
[1] = address
;
4015 aarch64_insn_r
->mem_rec_count
= 1;
4020 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4022 record_buf
[0] = reg_rt
;
4023 aarch64_insn_r
->reg_rec_count
= 1;
4025 if (insn_bits10_11
== 0x01 || insn_bits10_11
== 0x03)
4026 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4028 /* Advanced SIMD load/store instructions. */
4030 return aarch64_record_asimd_load_store (aarch64_insn_r
);
4032 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
4034 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4036 return AARCH64_RECORD_SUCCESS
;
4039 /* Record handler for data processing SIMD and floating point instructions. */
4042 aarch64_record_data_proc_simd_fp (insn_decode_record
*aarch64_insn_r
)
4044 uint8_t insn_bit21
, opcode
, rmode
, reg_rd
;
4045 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits10_11
, insn_bits12_15
;
4046 uint8_t insn_bits11_14
;
4047 uint32_t record_buf
[2];
4049 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
4050 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
4051 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
4052 insn_bits12_15
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
4053 insn_bits11_14
= bits (aarch64_insn_r
->aarch64_insn
, 11, 14);
4054 opcode
= bits (aarch64_insn_r
->aarch64_insn
, 16, 18);
4055 rmode
= bits (aarch64_insn_r
->aarch64_insn
, 19, 20);
4056 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
4057 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
4060 debug_printf ("Process record: data processing SIMD/FP: ");
4062 if ((insn_bits28_31
& 0x05) == 0x01 && insn_bits24_27
== 0x0e)
4064 /* Floating point - fixed point conversion instructions. */
4068 debug_printf ("FP - fixed point conversion");
4070 if ((opcode
>> 1) == 0x0 && rmode
== 0x03)
4071 record_buf
[0] = reg_rd
;
4073 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4075 /* Floating point - conditional compare instructions. */
4076 else if (insn_bits10_11
== 0x01)
4079 debug_printf ("FP - conditional compare");
4081 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4083 /* Floating point - data processing (2-source) and
4084 conditional select instructions. */
4085 else if (insn_bits10_11
== 0x02 || insn_bits10_11
== 0x03)
4088 debug_printf ("FP - DP (2-source)");
4090 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4092 else if (insn_bits10_11
== 0x00)
4094 /* Floating point - immediate instructions. */
4095 if ((insn_bits12_15
& 0x01) == 0x01
4096 || (insn_bits12_15
& 0x07) == 0x04)
4099 debug_printf ("FP - immediate");
4100 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4102 /* Floating point - compare instructions. */
4103 else if ((insn_bits12_15
& 0x03) == 0x02)
4106 debug_printf ("FP - immediate");
4107 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4109 /* Floating point - integer conversions instructions. */
4110 else if (insn_bits12_15
== 0x00)
4112 /* Convert float to integer instruction. */
4113 if (!(opcode
>> 1) || ((opcode
>> 1) == 0x02 && !rmode
))
4116 debug_printf ("float to int conversion");
4118 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4120 /* Convert integer to float instruction. */
4121 else if ((opcode
>> 1) == 0x01 && !rmode
)
4124 debug_printf ("int to float conversion");
4126 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4128 /* Move float to integer instruction. */
4129 else if ((opcode
>> 1) == 0x03)
4132 debug_printf ("move float to int");
4134 if (!(opcode
& 0x01))
4135 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4137 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4140 return AARCH64_RECORD_UNKNOWN
;
4143 return AARCH64_RECORD_UNKNOWN
;
4146 return AARCH64_RECORD_UNKNOWN
;
4148 else if ((insn_bits28_31
& 0x09) == 0x00 && insn_bits24_27
== 0x0e)
4151 debug_printf ("SIMD copy");
4153 /* Advanced SIMD copy instructions. */
4154 if (!bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
4155 && !bit (aarch64_insn_r
->aarch64_insn
, 15)
4156 && bit (aarch64_insn_r
->aarch64_insn
, 10))
4158 if (insn_bits11_14
== 0x05 || insn_bits11_14
== 0x07)
4159 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4161 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4164 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4166 /* All remaining floating point or advanced SIMD instructions. */
4170 debug_printf ("all remain");
4172 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4176 debug_printf ("\n");
4178 aarch64_insn_r
->reg_rec_count
++;
4179 gdb_assert (aarch64_insn_r
->reg_rec_count
== 1);
4180 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4182 return AARCH64_RECORD_SUCCESS
;
4185 /* Decodes insns type and invokes its record handler. */
4188 aarch64_record_decode_insn_handler (insn_decode_record
*aarch64_insn_r
)
4190 uint32_t ins_bit25
, ins_bit26
, ins_bit27
, ins_bit28
;
4192 ins_bit25
= bit (aarch64_insn_r
->aarch64_insn
, 25);
4193 ins_bit26
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4194 ins_bit27
= bit (aarch64_insn_r
->aarch64_insn
, 27);
4195 ins_bit28
= bit (aarch64_insn_r
->aarch64_insn
, 28);
4197 /* Data processing - immediate instructions. */
4198 if (!ins_bit26
&& !ins_bit27
&& ins_bit28
)
4199 return aarch64_record_data_proc_imm (aarch64_insn_r
);
4201 /* Branch, exception generation and system instructions. */
4202 if (ins_bit26
&& !ins_bit27
&& ins_bit28
)
4203 return aarch64_record_branch_except_sys (aarch64_insn_r
);
4205 /* Load and store instructions. */
4206 if (!ins_bit25
&& ins_bit27
)
4207 return aarch64_record_load_store (aarch64_insn_r
);
4209 /* Data processing - register instructions. */
4210 if (ins_bit25
&& !ins_bit26
&& ins_bit27
)
4211 return aarch64_record_data_proc_reg (aarch64_insn_r
);
4213 /* Data processing - SIMD and floating point instructions. */
4214 if (ins_bit25
&& ins_bit26
&& ins_bit27
)
4215 return aarch64_record_data_proc_simd_fp (aarch64_insn_r
);
4217 return AARCH64_RECORD_UNSUPPORTED
;
4220 /* Cleans up local record registers and memory allocations. */
4223 deallocate_reg_mem (insn_decode_record
*record
)
4225 xfree (record
->aarch64_regs
);
4226 xfree (record
->aarch64_mems
);
4230 namespace selftests
{
4233 aarch64_process_record_test (void)
4235 struct gdbarch_info info
;
4238 gdbarch_info_init (&info
);
4239 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
4241 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
4242 SELF_CHECK (gdbarch
!= NULL
);
4244 insn_decode_record aarch64_record
;
4246 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4247 aarch64_record
.regcache
= NULL
;
4248 aarch64_record
.this_addr
= 0;
4249 aarch64_record
.gdbarch
= gdbarch
;
4251 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4252 aarch64_record
.aarch64_insn
= 0xf9800020;
4253 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4254 SELF_CHECK (ret
== AARCH64_RECORD_SUCCESS
);
4255 SELF_CHECK (aarch64_record
.reg_rec_count
== 0);
4256 SELF_CHECK (aarch64_record
.mem_rec_count
== 0);
4258 deallocate_reg_mem (&aarch64_record
);
4261 } // namespace selftests
4262 #endif /* GDB_SELF_TEST */
4264 /* Parse the current instruction and record the values of the registers and
4265 memory that will be changed in current instruction to record_arch_list
4266 return -1 if something is wrong. */
4269 aarch64_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4270 CORE_ADDR insn_addr
)
4272 uint32_t rec_no
= 0;
4273 uint8_t insn_size
= 4;
4275 gdb_byte buf
[insn_size
];
4276 insn_decode_record aarch64_record
;
4278 memset (&buf
[0], 0, insn_size
);
4279 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4280 target_read_memory (insn_addr
, &buf
[0], insn_size
);
4281 aarch64_record
.aarch64_insn
4282 = (uint32_t) extract_unsigned_integer (&buf
[0],
4284 gdbarch_byte_order (gdbarch
));
4285 aarch64_record
.regcache
= regcache
;
4286 aarch64_record
.this_addr
= insn_addr
;
4287 aarch64_record
.gdbarch
= gdbarch
;
4289 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4290 if (ret
== AARCH64_RECORD_UNSUPPORTED
)
4292 printf_unfiltered (_("Process record does not support instruction "
4293 "0x%0x at address %s.\n"),
4294 aarch64_record
.aarch64_insn
,
4295 paddress (gdbarch
, insn_addr
));
4301 /* Record registers. */
4302 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4304 /* Always record register CPSR. */
4305 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4306 AARCH64_CPSR_REGNUM
);
4307 if (aarch64_record
.aarch64_regs
)
4308 for (rec_no
= 0; rec_no
< aarch64_record
.reg_rec_count
; rec_no
++)
4309 if (record_full_arch_list_add_reg (aarch64_record
.regcache
,
4310 aarch64_record
.aarch64_regs
[rec_no
]))
4313 /* Record memories. */
4314 if (aarch64_record
.aarch64_mems
)
4315 for (rec_no
= 0; rec_no
< aarch64_record
.mem_rec_count
; rec_no
++)
4316 if (record_full_arch_list_add_mem
4317 ((CORE_ADDR
)aarch64_record
.aarch64_mems
[rec_no
].addr
,
4318 aarch64_record
.aarch64_mems
[rec_no
].len
))
4321 if (record_full_arch_list_add_end ())
4325 deallocate_reg_mem (&aarch64_record
);