1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2021 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
28 #include "reggroups.h"
30 #include "arch-utils.h"
32 #include "frame-unwind.h"
33 #include "frame-base.h"
34 #include "trad-frame.h"
37 #include "dwarf2/frame.h"
39 #include "prologue-value.h"
40 #include "target-descriptions.h"
41 #include "user-regs.h"
43 #include "gdbsupport/selftest.h"
45 #include "aarch64-tdep.h"
46 #include "aarch64-ravenscar-thread.h"
49 #include "record-full.h"
50 #include "arch/aarch64-insn.h"
53 #include "opcode/aarch64.h"
56 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
58 #define HA_MAX_NUM_FLDS 4
60 /* All possible aarch64 target descriptors. */
61 static target_desc
*tdesc_aarch64_list
[AARCH64_MAX_SVE_VQ
+ 1][2/*pauth*/][2 /* mte */];
63 /* The standard register names, and all the valid aliases for them. */
66 const char *const name
;
68 } aarch64_register_aliases
[] =
70 /* 64-bit register names. */
71 {"fp", AARCH64_FP_REGNUM
},
72 {"lr", AARCH64_LR_REGNUM
},
73 {"sp", AARCH64_SP_REGNUM
},
75 /* 32-bit register names. */
76 {"w0", AARCH64_X0_REGNUM
+ 0},
77 {"w1", AARCH64_X0_REGNUM
+ 1},
78 {"w2", AARCH64_X0_REGNUM
+ 2},
79 {"w3", AARCH64_X0_REGNUM
+ 3},
80 {"w4", AARCH64_X0_REGNUM
+ 4},
81 {"w5", AARCH64_X0_REGNUM
+ 5},
82 {"w6", AARCH64_X0_REGNUM
+ 6},
83 {"w7", AARCH64_X0_REGNUM
+ 7},
84 {"w8", AARCH64_X0_REGNUM
+ 8},
85 {"w9", AARCH64_X0_REGNUM
+ 9},
86 {"w10", AARCH64_X0_REGNUM
+ 10},
87 {"w11", AARCH64_X0_REGNUM
+ 11},
88 {"w12", AARCH64_X0_REGNUM
+ 12},
89 {"w13", AARCH64_X0_REGNUM
+ 13},
90 {"w14", AARCH64_X0_REGNUM
+ 14},
91 {"w15", AARCH64_X0_REGNUM
+ 15},
92 {"w16", AARCH64_X0_REGNUM
+ 16},
93 {"w17", AARCH64_X0_REGNUM
+ 17},
94 {"w18", AARCH64_X0_REGNUM
+ 18},
95 {"w19", AARCH64_X0_REGNUM
+ 19},
96 {"w20", AARCH64_X0_REGNUM
+ 20},
97 {"w21", AARCH64_X0_REGNUM
+ 21},
98 {"w22", AARCH64_X0_REGNUM
+ 22},
99 {"w23", AARCH64_X0_REGNUM
+ 23},
100 {"w24", AARCH64_X0_REGNUM
+ 24},
101 {"w25", AARCH64_X0_REGNUM
+ 25},
102 {"w26", AARCH64_X0_REGNUM
+ 26},
103 {"w27", AARCH64_X0_REGNUM
+ 27},
104 {"w28", AARCH64_X0_REGNUM
+ 28},
105 {"w29", AARCH64_X0_REGNUM
+ 29},
106 {"w30", AARCH64_X0_REGNUM
+ 30},
109 {"ip0", AARCH64_X0_REGNUM
+ 16},
110 {"ip1", AARCH64_X0_REGNUM
+ 17}
113 /* The required core 'R' registers. */
114 static const char *const aarch64_r_register_names
[] =
116 /* These registers must appear in consecutive RAW register number
117 order and they must begin with AARCH64_X0_REGNUM! */
118 "x0", "x1", "x2", "x3",
119 "x4", "x5", "x6", "x7",
120 "x8", "x9", "x10", "x11",
121 "x12", "x13", "x14", "x15",
122 "x16", "x17", "x18", "x19",
123 "x20", "x21", "x22", "x23",
124 "x24", "x25", "x26", "x27",
125 "x28", "x29", "x30", "sp",
129 /* The FP/SIMD 'V' registers. */
130 static const char *const aarch64_v_register_names
[] =
132 /* These registers must appear in consecutive RAW register number
133 order and they must begin with AARCH64_V0_REGNUM! */
134 "v0", "v1", "v2", "v3",
135 "v4", "v5", "v6", "v7",
136 "v8", "v9", "v10", "v11",
137 "v12", "v13", "v14", "v15",
138 "v16", "v17", "v18", "v19",
139 "v20", "v21", "v22", "v23",
140 "v24", "v25", "v26", "v27",
141 "v28", "v29", "v30", "v31",
146 /* The SVE 'Z' and 'P' registers. */
147 static const char *const aarch64_sve_register_names
[] =
149 /* These registers must appear in consecutive RAW register number
150 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
151 "z0", "z1", "z2", "z3",
152 "z4", "z5", "z6", "z7",
153 "z8", "z9", "z10", "z11",
154 "z12", "z13", "z14", "z15",
155 "z16", "z17", "z18", "z19",
156 "z20", "z21", "z22", "z23",
157 "z24", "z25", "z26", "z27",
158 "z28", "z29", "z30", "z31",
160 "p0", "p1", "p2", "p3",
161 "p4", "p5", "p6", "p7",
162 "p8", "p9", "p10", "p11",
163 "p12", "p13", "p14", "p15",
167 static const char *const aarch64_pauth_register_names
[] =
169 /* Authentication mask for data pointer. */
171 /* Authentication mask for code pointer. */
175 static const char *const aarch64_mte_register_names
[] =
177 /* Tag Control Register. */
181 /* AArch64 prologue cache structure. */
182 struct aarch64_prologue_cache
184 /* The program counter at the start of the function. It is used to
185 identify this frame as a prologue frame. */
188 /* The program counter at the time this frame was created; i.e. where
189 this function was called from. It is used to identify this frame as a
193 /* The stack pointer at the time this frame was created; i.e. the
194 caller's stack pointer when this function was called. It is used
195 to identify this frame. */
198 /* Is the target available to read from? */
201 /* The frame base for this frame is just prev_sp - frame size.
202 FRAMESIZE is the distance from the frame pointer to the
203 initial stack pointer. */
206 /* The register used to hold the frame pointer for this frame. */
209 /* Saved register offsets. */
210 trad_frame_saved_reg
*saved_regs
;
214 show_aarch64_debug (struct ui_file
*file
, int from_tty
,
215 struct cmd_list_element
*c
, const char *value
)
217 fprintf_filtered (file
, _("AArch64 debugging is %s.\n"), value
);
222 /* Abstract instruction reader. */
224 class abstract_instruction_reader
227 /* Read in one instruction. */
228 virtual ULONGEST
read (CORE_ADDR memaddr
, int len
,
229 enum bfd_endian byte_order
) = 0;
232 /* Instruction reader from real target. */
234 class instruction_reader
: public abstract_instruction_reader
237 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
240 return read_code_unsigned_integer (memaddr
, len
, byte_order
);
246 /* If address signing is enabled, mask off the signature bits from the link
247 register, which is passed by value in ADDR, using the register values in
251 aarch64_frame_unmask_lr (struct gdbarch_tdep
*tdep
,
252 struct frame_info
*this_frame
, CORE_ADDR addr
)
254 if (tdep
->has_pauth ()
255 && frame_unwind_register_unsigned (this_frame
,
256 tdep
->pauth_ra_state_regnum
))
258 int cmask_num
= AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
);
259 CORE_ADDR cmask
= frame_unwind_register_unsigned (this_frame
, cmask_num
);
260 addr
= addr
& ~cmask
;
262 /* Record in the frame that the link register required unmasking. */
263 set_frame_previous_pc_masked (this_frame
);
269 /* Implement the "get_pc_address_flags" gdbarch method. */
272 aarch64_get_pc_address_flags (frame_info
*frame
, CORE_ADDR pc
)
274 if (pc
!= 0 && get_frame_pc_masked (frame
))
280 /* Analyze a prologue, looking for a recognizable stack frame
281 and frame pointer. Scan until we encounter a store that could
282 clobber the stack frame unexpectedly, or an unknown instruction. */
285 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
286 CORE_ADDR start
, CORE_ADDR limit
,
287 struct aarch64_prologue_cache
*cache
,
288 abstract_instruction_reader
& reader
)
290 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
293 /* Whether the stack has been set. This should be true when we notice a SP
294 to FP move or if we are using the SP as the base register for storing
295 data, in case the FP is ommitted. */
296 bool seen_stack_set
= false;
298 /* Track X registers and D registers in prologue. */
299 pv_t regs
[AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
];
301 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
; i
++)
302 regs
[i
] = pv_register (i
, 0);
303 pv_area
stack (AARCH64_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
305 for (; start
< limit
; start
+= 4)
310 insn
= reader
.read (start
, 4, byte_order_for_code
);
312 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
315 if (inst
.opcode
->iclass
== addsub_imm
316 && (inst
.opcode
->op
== OP_ADD
317 || strcmp ("sub", inst
.opcode
->name
) == 0))
319 unsigned rd
= inst
.operands
[0].reg
.regno
;
320 unsigned rn
= inst
.operands
[1].reg
.regno
;
322 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 3);
323 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd_SP
);
324 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn_SP
);
325 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_AIMM
);
327 if (inst
.opcode
->op
== OP_ADD
)
329 regs
[rd
] = pv_add_constant (regs
[rn
],
330 inst
.operands
[2].imm
.value
);
334 regs
[rd
] = pv_add_constant (regs
[rn
],
335 -inst
.operands
[2].imm
.value
);
338 /* Did we move SP to FP? */
339 if (rn
== AARCH64_SP_REGNUM
&& rd
== AARCH64_FP_REGNUM
)
340 seen_stack_set
= true;
342 else if (inst
.opcode
->iclass
== pcreladdr
343 && inst
.operands
[1].type
== AARCH64_OPND_ADDR_ADRP
)
345 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
346 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
348 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
350 else if (inst
.opcode
->iclass
== branch_imm
)
352 /* Stop analysis on branch. */
355 else if (inst
.opcode
->iclass
== condbranch
)
357 /* Stop analysis on branch. */
360 else if (inst
.opcode
->iclass
== branch_reg
)
362 /* Stop analysis on branch. */
365 else if (inst
.opcode
->iclass
== compbranch
)
367 /* Stop analysis on branch. */
370 else if (inst
.opcode
->op
== OP_MOVZ
)
372 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
374 /* If this shows up before we set the stack, keep going. Otherwise
375 stop the analysis. */
379 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
381 else if (inst
.opcode
->iclass
== log_shift
382 && strcmp (inst
.opcode
->name
, "orr") == 0)
384 unsigned rd
= inst
.operands
[0].reg
.regno
;
385 unsigned rn
= inst
.operands
[1].reg
.regno
;
386 unsigned rm
= inst
.operands
[2].reg
.regno
;
388 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
389 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn
);
390 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_Rm_SFT
);
392 if (inst
.operands
[2].shifter
.amount
== 0
393 && rn
== AARCH64_SP_REGNUM
)
397 aarch64_debug_printf ("prologue analysis gave up "
398 "addr=%s opcode=0x%x (orr x register)",
399 core_addr_to_string_nz (start
), insn
);
404 else if (inst
.opcode
->op
== OP_STUR
)
406 unsigned rt
= inst
.operands
[0].reg
.regno
;
407 unsigned rn
= inst
.operands
[1].addr
.base_regno
;
408 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
410 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
411 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
);
412 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_ADDR_SIMM9
);
413 gdb_assert (!inst
.operands
[1].addr
.offset
.is_reg
);
416 (pv_add_constant (regs
[rn
], inst
.operands
[1].addr
.offset
.imm
),
419 /* Are we storing with SP as a base? */
420 if (rn
== AARCH64_SP_REGNUM
)
421 seen_stack_set
= true;
423 else if ((inst
.opcode
->iclass
== ldstpair_off
424 || (inst
.opcode
->iclass
== ldstpair_indexed
425 && inst
.operands
[2].addr
.preind
))
426 && strcmp ("stp", inst
.opcode
->name
) == 0)
428 /* STP with addressing mode Pre-indexed and Base register. */
431 unsigned rn
= inst
.operands
[2].addr
.base_regno
;
432 int32_t imm
= inst
.operands
[2].addr
.offset
.imm
;
433 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
435 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
436 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
437 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rt2
438 || inst
.operands
[1].type
== AARCH64_OPND_Ft2
);
439 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_ADDR_SIMM7
);
440 gdb_assert (!inst
.operands
[2].addr
.offset
.is_reg
);
442 /* If recording this store would invalidate the store area
443 (perhaps because rn is not known) then we should abandon
444 further prologue analysis. */
445 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
)))
448 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
+ 8)))
451 rt1
= inst
.operands
[0].reg
.regno
;
452 rt2
= inst
.operands
[1].reg
.regno
;
453 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
455 rt1
+= AARCH64_X_REGISTER_COUNT
;
456 rt2
+= AARCH64_X_REGISTER_COUNT
;
459 stack
.store (pv_add_constant (regs
[rn
], imm
), size
, regs
[rt1
]);
460 stack
.store (pv_add_constant (regs
[rn
], imm
+ size
), size
, regs
[rt2
]);
462 if (inst
.operands
[2].addr
.writeback
)
463 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
465 /* Ignore the instruction that allocates stack space and sets
467 if (rn
== AARCH64_SP_REGNUM
&& !inst
.operands
[2].addr
.writeback
)
468 seen_stack_set
= true;
470 else if ((inst
.opcode
->iclass
== ldst_imm9
/* Signed immediate. */
471 || (inst
.opcode
->iclass
== ldst_pos
/* Unsigned immediate. */
472 && (inst
.opcode
->op
== OP_STR_POS
473 || inst
.opcode
->op
== OP_STRF_POS
)))
474 && inst
.operands
[1].addr
.base_regno
== AARCH64_SP_REGNUM
475 && strcmp ("str", inst
.opcode
->name
) == 0)
477 /* STR (immediate) */
478 unsigned int rt
= inst
.operands
[0].reg
.regno
;
479 int32_t imm
= inst
.operands
[1].addr
.offset
.imm
;
480 unsigned int rn
= inst
.operands
[1].addr
.base_regno
;
481 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
482 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
483 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
485 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
486 rt
+= AARCH64_X_REGISTER_COUNT
;
488 stack
.store (pv_add_constant (regs
[rn
], imm
), size
, regs
[rt
]);
489 if (inst
.operands
[1].addr
.writeback
)
490 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
492 /* Are we storing with SP as a base? */
493 if (rn
== AARCH64_SP_REGNUM
)
494 seen_stack_set
= true;
496 else if (inst
.opcode
->iclass
== testbranch
)
498 /* Stop analysis on branch. */
501 else if (inst
.opcode
->iclass
== ic_system
)
503 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
504 int ra_state_val
= 0;
506 if (insn
== 0xd503233f /* paciasp. */
507 || insn
== 0xd503237f /* pacibsp. */)
509 /* Return addresses are mangled. */
512 else if (insn
== 0xd50323bf /* autiasp. */
513 || insn
== 0xd50323ff /* autibsp. */)
515 /* Return addresses are not mangled. */
520 aarch64_debug_printf ("prologue analysis gave up addr=%s"
521 " opcode=0x%x (iclass)",
522 core_addr_to_string_nz (start
), insn
);
526 if (tdep
->has_pauth () && cache
!= nullptr)
528 int regnum
= tdep
->pauth_ra_state_regnum
;
529 cache
->saved_regs
[regnum
].set_value (ra_state_val
);
534 aarch64_debug_printf ("prologue analysis gave up addr=%s"
536 core_addr_to_string_nz (start
), insn
);
545 if (pv_is_register (regs
[AARCH64_FP_REGNUM
], AARCH64_SP_REGNUM
))
547 /* Frame pointer is fp. Frame size is constant. */
548 cache
->framereg
= AARCH64_FP_REGNUM
;
549 cache
->framesize
= -regs
[AARCH64_FP_REGNUM
].k
;
551 else if (pv_is_register (regs
[AARCH64_SP_REGNUM
], AARCH64_SP_REGNUM
))
553 /* Try the stack pointer. */
554 cache
->framesize
= -regs
[AARCH64_SP_REGNUM
].k
;
555 cache
->framereg
= AARCH64_SP_REGNUM
;
559 /* We're just out of luck. We don't know where the frame is. */
560 cache
->framereg
= -1;
561 cache
->framesize
= 0;
564 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
568 if (stack
.find_reg (gdbarch
, i
, &offset
))
569 cache
->saved_regs
[i
].set_addr (offset
);
572 for (i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
574 int regnum
= gdbarch_num_regs (gdbarch
);
577 if (stack
.find_reg (gdbarch
, i
+ AARCH64_X_REGISTER_COUNT
,
579 cache
->saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].set_addr (offset
);
586 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
587 CORE_ADDR start
, CORE_ADDR limit
,
588 struct aarch64_prologue_cache
*cache
)
590 instruction_reader reader
;
592 return aarch64_analyze_prologue (gdbarch
, start
, limit
, cache
,
598 namespace selftests
{
600 /* Instruction reader from manually cooked instruction sequences. */
602 class instruction_reader_test
: public abstract_instruction_reader
605 template<size_t SIZE
>
606 explicit instruction_reader_test (const uint32_t (&insns
)[SIZE
])
607 : m_insns (insns
), m_insns_size (SIZE
)
610 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
613 SELF_CHECK (len
== 4);
614 SELF_CHECK (memaddr
% 4 == 0);
615 SELF_CHECK (memaddr
/ 4 < m_insns_size
);
617 return m_insns
[memaddr
/ 4];
621 const uint32_t *m_insns
;
626 aarch64_analyze_prologue_test (void)
628 struct gdbarch_info info
;
630 gdbarch_info_init (&info
);
631 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
633 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
634 SELF_CHECK (gdbarch
!= NULL
);
636 struct aarch64_prologue_cache cache
;
637 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
639 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
641 /* Test the simple prologue in which frame pointer is used. */
643 static const uint32_t insns
[] = {
644 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
645 0x910003fd, /* mov x29, sp */
646 0x97ffffe6, /* bl 0x400580 */
648 instruction_reader_test
reader (insns
);
650 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
651 SELF_CHECK (end
== 4 * 2);
653 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
654 SELF_CHECK (cache
.framesize
== 272);
656 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
658 if (i
== AARCH64_FP_REGNUM
)
659 SELF_CHECK (cache
.saved_regs
[i
].addr () == -272);
660 else if (i
== AARCH64_LR_REGNUM
)
661 SELF_CHECK (cache
.saved_regs
[i
].addr () == -264);
663 SELF_CHECK (cache
.saved_regs
[i
].is_realreg ()
664 && cache
.saved_regs
[i
].realreg () == i
);
667 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
669 int num_regs
= gdbarch_num_regs (gdbarch
);
670 int regnum
= i
+ num_regs
+ AARCH64_D0_REGNUM
;
672 SELF_CHECK (cache
.saved_regs
[regnum
].is_realreg ()
673 && cache
.saved_regs
[regnum
].realreg () == regnum
);
677 /* Test a prologue in which STR is used and frame pointer is not
680 static const uint32_t insns
[] = {
681 0xf81d0ff3, /* str x19, [sp, #-48]! */
682 0xb9002fe0, /* str w0, [sp, #44] */
683 0xf90013e1, /* str x1, [sp, #32]*/
684 0xfd000fe0, /* str d0, [sp, #24] */
685 0xaa0203f3, /* mov x19, x2 */
686 0xf94013e0, /* ldr x0, [sp, #32] */
688 instruction_reader_test
reader (insns
);
690 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
691 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
693 SELF_CHECK (end
== 4 * 5);
695 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
696 SELF_CHECK (cache
.framesize
== 48);
698 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
701 SELF_CHECK (cache
.saved_regs
[i
].addr () == -16);
703 SELF_CHECK (cache
.saved_regs
[i
].addr () == -48);
705 SELF_CHECK (cache
.saved_regs
[i
].is_realreg ()
706 && cache
.saved_regs
[i
].realreg () == i
);
709 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
711 int num_regs
= gdbarch_num_regs (gdbarch
);
712 int regnum
= i
+ num_regs
+ AARCH64_D0_REGNUM
;
716 SELF_CHECK (cache
.saved_regs
[regnum
].addr () == -24);
718 SELF_CHECK (cache
.saved_regs
[regnum
].is_realreg ()
719 && cache
.saved_regs
[regnum
].realreg () == regnum
);
723 /* Test handling of movz before setting the frame pointer. */
725 static const uint32_t insns
[] = {
726 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
727 0x52800020, /* mov w0, #0x1 */
728 0x910003fd, /* mov x29, sp */
729 0x528000a2, /* mov w2, #0x5 */
730 0x97fffff8, /* bl 6e4 */
733 instruction_reader_test
reader (insns
);
735 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
736 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
738 /* We should stop at the 4th instruction. */
739 SELF_CHECK (end
== (4 - 1) * 4);
740 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
741 SELF_CHECK (cache
.framesize
== 16);
744 /* Test handling of movz/stp when using the stack pointer as frame
747 static const uint32_t insns
[] = {
748 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
749 0x52800020, /* mov w0, #0x1 */
750 0x290207e0, /* stp w0, w1, [sp, #16] */
751 0xa9018fe2, /* stp x2, x3, [sp, #24] */
752 0x528000a2, /* mov w2, #0x5 */
753 0x97fffff8, /* bl 6e4 */
756 instruction_reader_test
reader (insns
);
758 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
759 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
761 /* We should stop at the 5th instruction. */
762 SELF_CHECK (end
== (5 - 1) * 4);
763 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
764 SELF_CHECK (cache
.framesize
== 64);
767 /* Test handling of movz/str when using the stack pointer as frame
770 static const uint32_t insns
[] = {
771 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
772 0x52800020, /* mov w0, #0x1 */
773 0xb9002be4, /* str w4, [sp, #40] */
774 0xf9001be5, /* str x5, [sp, #48] */
775 0x528000a2, /* mov w2, #0x5 */
776 0x97fffff8, /* bl 6e4 */
779 instruction_reader_test
reader (insns
);
781 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
782 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
784 /* We should stop at the 5th instruction. */
785 SELF_CHECK (end
== (5 - 1) * 4);
786 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
787 SELF_CHECK (cache
.framesize
== 64);
790 /* Test handling of movz/stur when using the stack pointer as frame
793 static const uint32_t insns
[] = {
794 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
795 0x52800020, /* mov w0, #0x1 */
796 0xb80343e6, /* stur w6, [sp, #52] */
797 0xf80383e7, /* stur x7, [sp, #56] */
798 0x528000a2, /* mov w2, #0x5 */
799 0x97fffff8, /* bl 6e4 */
802 instruction_reader_test
reader (insns
);
804 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
805 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
807 /* We should stop at the 5th instruction. */
808 SELF_CHECK (end
== (5 - 1) * 4);
809 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
810 SELF_CHECK (cache
.framesize
== 64);
813 /* Test handling of movz when there is no frame pointer set or no stack
816 static const uint32_t insns
[] = {
817 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
818 0x52800020, /* mov w0, #0x1 */
819 0x528000a2, /* mov w2, #0x5 */
820 0x97fffff8, /* bl 6e4 */
823 instruction_reader_test
reader (insns
);
825 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
826 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
828 /* We should stop at the 4th instruction. */
829 SELF_CHECK (end
== (4 - 1) * 4);
830 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
831 SELF_CHECK (cache
.framesize
== 16);
834 /* Test a prologue in which there is a return address signing instruction. */
835 if (tdep
->has_pauth ())
837 static const uint32_t insns
[] = {
838 0xd503233f, /* paciasp */
839 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
840 0x910003fd, /* mov x29, sp */
841 0xf801c3f3, /* str x19, [sp, #28] */
842 0xb9401fa0, /* ldr x19, [x29, #28] */
844 instruction_reader_test
reader (insns
);
846 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
847 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
,
850 SELF_CHECK (end
== 4 * 4);
851 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
852 SELF_CHECK (cache
.framesize
== 48);
854 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
857 SELF_CHECK (cache
.saved_regs
[i
].addr () == -20);
858 else if (i
== AARCH64_FP_REGNUM
)
859 SELF_CHECK (cache
.saved_regs
[i
].addr () == -48);
860 else if (i
== AARCH64_LR_REGNUM
)
861 SELF_CHECK (cache
.saved_regs
[i
].addr () == -40);
863 SELF_CHECK (cache
.saved_regs
[i
].is_realreg ()
864 && cache
.saved_regs
[i
].realreg () == i
);
867 if (tdep
->has_pauth ())
869 int regnum
= tdep
->pauth_ra_state_regnum
;
870 SELF_CHECK (cache
.saved_regs
[regnum
].is_value ());
874 } // namespace selftests
875 #endif /* GDB_SELF_TEST */
877 /* Implement the "skip_prologue" gdbarch method. */
880 aarch64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
882 CORE_ADDR func_addr
, limit_pc
;
884 /* See if we can determine the end of the prologue via the symbol
885 table. If so, then return either PC, or the PC after the
886 prologue, whichever is greater. */
887 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
889 CORE_ADDR post_prologue_pc
890 = skip_prologue_using_sal (gdbarch
, func_addr
);
892 if (post_prologue_pc
!= 0)
893 return std::max (pc
, post_prologue_pc
);
896 /* Can't determine prologue from the symbol table, need to examine
899 /* Find an upper limit on the function prologue using the debug
900 information. If the debug information could not be used to
901 provide that bound, then use an arbitrary large number as the
903 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
905 limit_pc
= pc
+ 128; /* Magic. */
907 /* Try disassembling prologue. */
908 return aarch64_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
911 /* Scan the function prologue for THIS_FRAME and populate the prologue
915 aarch64_scan_prologue (struct frame_info
*this_frame
,
916 struct aarch64_prologue_cache
*cache
)
918 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
919 CORE_ADDR prologue_start
;
920 CORE_ADDR prologue_end
;
921 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
922 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
924 cache
->prev_pc
= prev_pc
;
926 /* Assume we do not find a frame. */
927 cache
->framereg
= -1;
928 cache
->framesize
= 0;
930 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
933 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
937 /* No line info so use the current PC. */
938 prologue_end
= prev_pc
;
940 else if (sal
.end
< prologue_end
)
942 /* The next line begins after the function end. */
943 prologue_end
= sal
.end
;
946 prologue_end
= std::min (prologue_end
, prev_pc
);
947 aarch64_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
953 frame_loc
= get_frame_register_unsigned (this_frame
, AARCH64_FP_REGNUM
);
957 cache
->framereg
= AARCH64_FP_REGNUM
;
958 cache
->framesize
= 16;
959 cache
->saved_regs
[29].set_addr (0);
960 cache
->saved_regs
[30].set_addr (8);
964 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
965 function may throw an exception if the inferior's registers or memory is
969 aarch64_make_prologue_cache_1 (struct frame_info
*this_frame
,
970 struct aarch64_prologue_cache
*cache
)
972 CORE_ADDR unwound_fp
;
975 aarch64_scan_prologue (this_frame
, cache
);
977 if (cache
->framereg
== -1)
980 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
984 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
986 /* Calculate actual addresses of saved registers using offsets
987 determined by aarch64_analyze_prologue. */
988 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
989 if (cache
->saved_regs
[reg
].is_addr ())
990 cache
->saved_regs
[reg
].set_addr (cache
->saved_regs
[reg
].addr ()
993 cache
->func
= get_frame_func (this_frame
);
995 cache
->available_p
= 1;
998 /* Allocate and fill in *THIS_CACHE with information about the prologue of
999 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
1000 Return a pointer to the current aarch64_prologue_cache in
1003 static struct aarch64_prologue_cache
*
1004 aarch64_make_prologue_cache (struct frame_info
*this_frame
, void **this_cache
)
1006 struct aarch64_prologue_cache
*cache
;
1008 if (*this_cache
!= NULL
)
1009 return (struct aarch64_prologue_cache
*) *this_cache
;
1011 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
1012 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1013 *this_cache
= cache
;
1017 aarch64_make_prologue_cache_1 (this_frame
, cache
);
1019 catch (const gdb_exception_error
&ex
)
1021 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
1028 /* Implement the "stop_reason" frame_unwind method. */
1030 static enum unwind_stop_reason
1031 aarch64_prologue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1034 struct aarch64_prologue_cache
*cache
1035 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1037 if (!cache
->available_p
)
1038 return UNWIND_UNAVAILABLE
;
1040 /* Halt the backtrace at "_start". */
1041 if (cache
->prev_pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1042 return UNWIND_OUTERMOST
;
1044 /* We've hit a wall, stop. */
1045 if (cache
->prev_sp
== 0)
1046 return UNWIND_OUTERMOST
;
1048 return UNWIND_NO_REASON
;
1051 /* Our frame ID for a normal frame is the current function's starting
1052 PC and the caller's SP when we were called. */
1055 aarch64_prologue_this_id (struct frame_info
*this_frame
,
1056 void **this_cache
, struct frame_id
*this_id
)
1058 struct aarch64_prologue_cache
*cache
1059 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1061 if (!cache
->available_p
)
1062 *this_id
= frame_id_build_unavailable_stack (cache
->func
);
1064 *this_id
= frame_id_build (cache
->prev_sp
, cache
->func
);
1067 /* Implement the "prev_register" frame_unwind method. */
1069 static struct value
*
1070 aarch64_prologue_prev_register (struct frame_info
*this_frame
,
1071 void **this_cache
, int prev_regnum
)
1073 struct aarch64_prologue_cache
*cache
1074 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1076 /* If we are asked to unwind the PC, then we need to return the LR
1077 instead. The prologue may save PC, but it will point into this
1078 frame's prologue, not the next frame's resume location. */
1079 if (prev_regnum
== AARCH64_PC_REGNUM
)
1082 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1083 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1085 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1087 if (tdep
->has_pauth ()
1088 && cache
->saved_regs
[tdep
->pauth_ra_state_regnum
].is_value ())
1089 lr
= aarch64_frame_unmask_lr (tdep
, this_frame
, lr
);
1091 return frame_unwind_got_constant (this_frame
, prev_regnum
, lr
);
1094 /* SP is generally not saved to the stack, but this frame is
1095 identified by the next frame's stack pointer at the time of the
1096 call. The value was already reconstructed into PREV_SP. */
1102 | | | <- Previous SP
1105 +--| saved fp |<- FP
1109 if (prev_regnum
== AARCH64_SP_REGNUM
)
1110 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1113 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1117 /* AArch64 prologue unwinder. */
1118 static frame_unwind aarch64_prologue_unwind
=
1121 aarch64_prologue_frame_unwind_stop_reason
,
1122 aarch64_prologue_this_id
,
1123 aarch64_prologue_prev_register
,
1125 default_frame_sniffer
1128 /* Allocate and fill in *THIS_CACHE with information about the prologue of
1129 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
1130 Return a pointer to the current aarch64_prologue_cache in
1133 static struct aarch64_prologue_cache
*
1134 aarch64_make_stub_cache (struct frame_info
*this_frame
, void **this_cache
)
1136 struct aarch64_prologue_cache
*cache
;
1138 if (*this_cache
!= NULL
)
1139 return (struct aarch64_prologue_cache
*) *this_cache
;
1141 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
1142 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1143 *this_cache
= cache
;
1147 cache
->prev_sp
= get_frame_register_unsigned (this_frame
,
1149 cache
->prev_pc
= get_frame_pc (this_frame
);
1150 cache
->available_p
= 1;
1152 catch (const gdb_exception_error
&ex
)
1154 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
1161 /* Implement the "stop_reason" frame_unwind method. */
1163 static enum unwind_stop_reason
1164 aarch64_stub_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1167 struct aarch64_prologue_cache
*cache
1168 = aarch64_make_stub_cache (this_frame
, this_cache
);
1170 if (!cache
->available_p
)
1171 return UNWIND_UNAVAILABLE
;
1173 return UNWIND_NO_REASON
;
1176 /* Our frame ID for a stub frame is the current SP and LR. */
1179 aarch64_stub_this_id (struct frame_info
*this_frame
,
1180 void **this_cache
, struct frame_id
*this_id
)
1182 struct aarch64_prologue_cache
*cache
1183 = aarch64_make_stub_cache (this_frame
, this_cache
);
1185 if (cache
->available_p
)
1186 *this_id
= frame_id_build (cache
->prev_sp
, cache
->prev_pc
);
1188 *this_id
= frame_id_build_unavailable_stack (cache
->prev_pc
);
1191 /* Implement the "sniffer" frame_unwind method. */
1194 aarch64_stub_unwind_sniffer (const struct frame_unwind
*self
,
1195 struct frame_info
*this_frame
,
1196 void **this_prologue_cache
)
1198 CORE_ADDR addr_in_block
;
1201 addr_in_block
= get_frame_address_in_block (this_frame
);
1202 if (in_plt_section (addr_in_block
)
1203 /* We also use the stub winder if the target memory is unreadable
1204 to avoid having the prologue unwinder trying to read it. */
1205 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1211 /* AArch64 stub unwinder. */
1212 static frame_unwind aarch64_stub_unwind
=
1215 aarch64_stub_frame_unwind_stop_reason
,
1216 aarch64_stub_this_id
,
1217 aarch64_prologue_prev_register
,
1219 aarch64_stub_unwind_sniffer
1222 /* Return the frame base address of *THIS_FRAME. */
1225 aarch64_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1227 struct aarch64_prologue_cache
*cache
1228 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1230 return cache
->prev_sp
- cache
->framesize
;
1233 /* AArch64 default frame base information. */
1234 static frame_base aarch64_normal_base
=
1236 &aarch64_prologue_unwind
,
1237 aarch64_normal_frame_base
,
1238 aarch64_normal_frame_base
,
1239 aarch64_normal_frame_base
1242 /* Return the value of the REGNUM register in the previous frame of
1245 static struct value
*
1246 aarch64_dwarf2_prev_register (struct frame_info
*this_frame
,
1247 void **this_cache
, int regnum
)
1249 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1254 case AARCH64_PC_REGNUM
:
1255 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1256 lr
= aarch64_frame_unmask_lr (tdep
, this_frame
, lr
);
1257 return frame_unwind_got_constant (this_frame
, regnum
, lr
);
1260 internal_error (__FILE__
, __LINE__
,
1261 _("Unexpected register %d"), regnum
);
1265 static const unsigned char op_lit0
= DW_OP_lit0
;
1266 static const unsigned char op_lit1
= DW_OP_lit1
;
1268 /* Implement the "init_reg" dwarf2_frame_ops method. */
1271 aarch64_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1272 struct dwarf2_frame_state_reg
*reg
,
1273 struct frame_info
*this_frame
)
1275 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1279 case AARCH64_PC_REGNUM
:
1280 reg
->how
= DWARF2_FRAME_REG_FN
;
1281 reg
->loc
.fn
= aarch64_dwarf2_prev_register
;
1284 case AARCH64_SP_REGNUM
:
1285 reg
->how
= DWARF2_FRAME_REG_CFA
;
1289 /* Init pauth registers. */
1290 if (tdep
->has_pauth ())
1292 if (regnum
== tdep
->pauth_ra_state_regnum
)
1294 /* Initialize RA_STATE to zero. */
1295 reg
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1296 reg
->loc
.exp
.start
= &op_lit0
;
1297 reg
->loc
.exp
.len
= 1;
1300 else if (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
1301 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
))
1303 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1309 /* Implement the execute_dwarf_cfa_vendor_op method. */
1312 aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch
*gdbarch
, gdb_byte op
,
1313 struct dwarf2_frame_state
*fs
)
1315 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1316 struct dwarf2_frame_state_reg
*ra_state
;
1318 if (op
== DW_CFA_AARCH64_negate_ra_state
)
1320 /* On systems without pauth, treat as a nop. */
1321 if (!tdep
->has_pauth ())
1324 /* Allocate RA_STATE column if it's not allocated yet. */
1325 fs
->regs
.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE
+ 1);
1327 /* Toggle the status of RA_STATE between 0 and 1. */
1328 ra_state
= &(fs
->regs
.reg
[AARCH64_DWARF_PAUTH_RA_STATE
]);
1329 ra_state
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1331 if (ra_state
->loc
.exp
.start
== nullptr
1332 || ra_state
->loc
.exp
.start
== &op_lit0
)
1333 ra_state
->loc
.exp
.start
= &op_lit1
;
1335 ra_state
->loc
.exp
.start
= &op_lit0
;
1337 ra_state
->loc
.exp
.len
= 1;
1345 /* Used for matching BRK instructions for AArch64. */
1346 static constexpr uint32_t BRK_INSN_MASK
= 0xffe0001f;
1347 static constexpr uint32_t BRK_INSN_BASE
= 0xd4200000;
1349 /* Implementation of gdbarch_program_breakpoint_here_p for aarch64. */
1352 aarch64_program_breakpoint_here_p (gdbarch
*gdbarch
, CORE_ADDR address
)
1354 const uint32_t insn_len
= 4;
1355 gdb_byte target_mem
[4];
1357 /* Enable the automatic memory restoration from breakpoints while
1358 we read the memory. Otherwise we may find temporary breakpoints, ones
1359 inserted by GDB, and flag them as permanent breakpoints. */
1360 scoped_restore restore_memory
1361 = make_scoped_restore_show_memory_breakpoints (0);
1363 if (target_read_memory (address
, target_mem
, insn_len
) == 0)
1366 (uint32_t) extract_unsigned_integer (target_mem
, insn_len
,
1367 gdbarch_byte_order_for_code (gdbarch
));
1369 /* Check if INSN is a BRK instruction pattern. There are multiple choices
1370 of such instructions with different immediate values. Different OS'
1371 may use a different variation, but they have the same outcome. */
1372 return ((insn
& BRK_INSN_MASK
) == BRK_INSN_BASE
);
1378 /* When arguments must be pushed onto the stack, they go on in reverse
1379 order. The code below implements a FILO (stack) to do this. */
1383 /* Value to pass on stack. It can be NULL if this item is for stack
1385 const gdb_byte
*data
;
1387 /* Size in bytes of value to pass on stack. */
1391 /* Implement the gdbarch type alignment method, overrides the generic
1392 alignment algorithm for anything that is aarch64 specific. */
1395 aarch64_type_align (gdbarch
*gdbarch
, struct type
*t
)
1397 t
= check_typedef (t
);
1398 if (t
->code () == TYPE_CODE_ARRAY
&& t
->is_vector ())
1400 /* Use the natural alignment for vector types (the same for
1401 scalar type), but the maximum alignment is 128-bit. */
1402 if (TYPE_LENGTH (t
) > 16)
1405 return TYPE_LENGTH (t
);
1408 /* Allow the common code to calculate the alignment. */
1412 /* Worker function for aapcs_is_vfp_call_or_return_candidate.
1414 Return the number of register required, or -1 on failure.
1416 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1417 to the element, else fail if the type of this element does not match the
1421 aapcs_is_vfp_call_or_return_candidate_1 (struct type
*type
,
1422 struct type
**fundamental_type
)
1424 if (type
== nullptr)
1427 switch (type
->code ())
1430 if (TYPE_LENGTH (type
) > 16)
1433 if (*fundamental_type
== nullptr)
1434 *fundamental_type
= type
;
1435 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1436 || type
->code () != (*fundamental_type
)->code ())
1441 case TYPE_CODE_COMPLEX
:
1443 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
1444 if (TYPE_LENGTH (target_type
) > 16)
1447 if (*fundamental_type
== nullptr)
1448 *fundamental_type
= target_type
;
1449 else if (TYPE_LENGTH (target_type
) != TYPE_LENGTH (*fundamental_type
)
1450 || target_type
->code () != (*fundamental_type
)->code ())
1456 case TYPE_CODE_ARRAY
:
1458 if (type
->is_vector ())
1460 if (TYPE_LENGTH (type
) != 8 && TYPE_LENGTH (type
) != 16)
1463 if (*fundamental_type
== nullptr)
1464 *fundamental_type
= type
;
1465 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1466 || type
->code () != (*fundamental_type
)->code ())
1473 struct type
*target_type
= TYPE_TARGET_TYPE (type
);
1474 int count
= aapcs_is_vfp_call_or_return_candidate_1
1475 (target_type
, fundamental_type
);
1480 count
*= (TYPE_LENGTH (type
) / TYPE_LENGTH (target_type
));
1485 case TYPE_CODE_STRUCT
:
1486 case TYPE_CODE_UNION
:
1490 for (int i
= 0; i
< type
->num_fields (); i
++)
1492 /* Ignore any static fields. */
1493 if (field_is_static (&type
->field (i
)))
1496 struct type
*member
= check_typedef (type
->field (i
).type ());
1498 int sub_count
= aapcs_is_vfp_call_or_return_candidate_1
1499 (member
, fundamental_type
);
1500 if (sub_count
== -1)
1505 /* Ensure there is no padding between the fields (allowing for empty
1506 zero length structs) */
1507 int ftype_length
= (*fundamental_type
== nullptr)
1508 ? 0 : TYPE_LENGTH (*fundamental_type
);
1509 if (count
* ftype_length
!= TYPE_LENGTH (type
))
1522 /* Return true if an argument, whose type is described by TYPE, can be passed or
1523 returned in simd/fp registers, providing enough parameter passing registers
1524 are available. This is as described in the AAPCS64.
1526 Upon successful return, *COUNT returns the number of needed registers,
1527 *FUNDAMENTAL_TYPE contains the type of those registers.
1529 Candidate as per the AAPCS64 5.4.2.C is either a:
1532 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1533 all the members are floats and has at most 4 members.
1534 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1535 all the members are short vectors and has at most 4 members.
1538 Note that HFAs and HVAs can include nested structures and arrays. */
1541 aapcs_is_vfp_call_or_return_candidate (struct type
*type
, int *count
,
1542 struct type
**fundamental_type
)
1544 if (type
== nullptr)
1547 *fundamental_type
= nullptr;
1549 int ag_count
= aapcs_is_vfp_call_or_return_candidate_1 (type
,
1552 if (ag_count
> 0 && ag_count
<= HA_MAX_NUM_FLDS
)
1561 /* AArch64 function call information structure. */
1562 struct aarch64_call_info
1564 /* the current argument number. */
1565 unsigned argnum
= 0;
1567 /* The next general purpose register number, equivalent to NGRN as
1568 described in the AArch64 Procedure Call Standard. */
1571 /* The next SIMD and floating point register number, equivalent to
1572 NSRN as described in the AArch64 Procedure Call Standard. */
1575 /* The next stacked argument address, equivalent to NSAA as
1576 described in the AArch64 Procedure Call Standard. */
1579 /* Stack item vector. */
1580 std::vector
<stack_item_t
> si
;
1583 /* Pass a value in a sequence of consecutive X registers. The caller
1584 is responsible for ensuring sufficient registers are available. */
1587 pass_in_x (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1588 struct aarch64_call_info
*info
, struct type
*type
,
1591 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1592 int len
= TYPE_LENGTH (type
);
1593 enum type_code typecode
= type
->code ();
1594 int regnum
= AARCH64_X0_REGNUM
+ info
->ngrn
;
1595 const bfd_byte
*buf
= value_contents (arg
);
1601 int partial_len
= len
< X_REGISTER_SIZE
? len
: X_REGISTER_SIZE
;
1602 CORE_ADDR regval
= extract_unsigned_integer (buf
, partial_len
,
1606 /* Adjust sub-word struct/union args when big-endian. */
1607 if (byte_order
== BFD_ENDIAN_BIG
1608 && partial_len
< X_REGISTER_SIZE
1609 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1610 regval
<<= ((X_REGISTER_SIZE
- partial_len
) * TARGET_CHAR_BIT
);
1612 aarch64_debug_printf ("arg %d in %s = 0x%s", info
->argnum
,
1613 gdbarch_register_name (gdbarch
, regnum
),
1614 phex (regval
, X_REGISTER_SIZE
));
1616 regcache_cooked_write_unsigned (regcache
, regnum
, regval
);
1623 /* Attempt to marshall a value in a V register. Return 1 if
1624 successful, or 0 if insufficient registers are available. This
1625 function, unlike the equivalent pass_in_x() function does not
1626 handle arguments spread across multiple registers. */
1629 pass_in_v (struct gdbarch
*gdbarch
,
1630 struct regcache
*regcache
,
1631 struct aarch64_call_info
*info
,
1632 int len
, const bfd_byte
*buf
)
1636 int regnum
= AARCH64_V0_REGNUM
+ info
->nsrn
;
1637 /* Enough space for a full vector register. */
1638 gdb_byte reg
[register_size (gdbarch
, regnum
)];
1639 gdb_assert (len
<= sizeof (reg
));
1644 memset (reg
, 0, sizeof (reg
));
1645 /* PCS C.1, the argument is allocated to the least significant
1646 bits of V register. */
1647 memcpy (reg
, buf
, len
);
1648 regcache
->cooked_write (regnum
, reg
);
1650 aarch64_debug_printf ("arg %d in %s", info
->argnum
,
1651 gdbarch_register_name (gdbarch
, regnum
));
1659 /* Marshall an argument onto the stack. */
1662 pass_on_stack (struct aarch64_call_info
*info
, struct type
*type
,
1665 const bfd_byte
*buf
= value_contents (arg
);
1666 int len
= TYPE_LENGTH (type
);
1672 align
= type_align (type
);
1674 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1675 Natural alignment of the argument's type. */
1676 align
= align_up (align
, 8);
1678 /* The AArch64 PCS requires at most doubleword alignment. */
1682 aarch64_debug_printf ("arg %d len=%d @ sp + %d\n", info
->argnum
, len
,
1687 info
->si
.push_back (item
);
1690 if (info
->nsaa
& (align
- 1))
1692 /* Push stack alignment padding. */
1693 int pad
= align
- (info
->nsaa
& (align
- 1));
1698 info
->si
.push_back (item
);
1703 /* Marshall an argument into a sequence of one or more consecutive X
1704 registers or, if insufficient X registers are available then onto
1708 pass_in_x_or_stack (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1709 struct aarch64_call_info
*info
, struct type
*type
,
1712 int len
= TYPE_LENGTH (type
);
1713 int nregs
= (len
+ X_REGISTER_SIZE
- 1) / X_REGISTER_SIZE
;
1715 /* PCS C.13 - Pass in registers if we have enough spare */
1716 if (info
->ngrn
+ nregs
<= 8)
1718 pass_in_x (gdbarch
, regcache
, info
, type
, arg
);
1719 info
->ngrn
+= nregs
;
1724 pass_on_stack (info
, type
, arg
);
1728 /* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1729 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1730 registers. A return value of false is an error state as the value will have
1731 been partially passed to the stack. */
1733 pass_in_v_vfp_candidate (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1734 struct aarch64_call_info
*info
, struct type
*arg_type
,
1737 switch (arg_type
->code ())
1740 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1741 value_contents (arg
));
1744 case TYPE_CODE_COMPLEX
:
1746 const bfd_byte
*buf
= value_contents (arg
);
1747 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (arg_type
));
1749 if (!pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1753 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1754 buf
+ TYPE_LENGTH (target_type
));
1757 case TYPE_CODE_ARRAY
:
1758 if (arg_type
->is_vector ())
1759 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1760 value_contents (arg
));
1763 case TYPE_CODE_STRUCT
:
1764 case TYPE_CODE_UNION
:
1765 for (int i
= 0; i
< arg_type
->num_fields (); i
++)
1767 /* Don't include static fields. */
1768 if (field_is_static (&arg_type
->field (i
)))
1771 struct value
*field
= value_primitive_field (arg
, 0, i
, arg_type
);
1772 struct type
*field_type
= check_typedef (value_type (field
));
1774 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, info
, field_type
,
1785 /* Implement the "push_dummy_call" gdbarch method. */
1788 aarch64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1789 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1791 struct value
**args
, CORE_ADDR sp
,
1792 function_call_return_method return_method
,
1793 CORE_ADDR struct_addr
)
1796 struct aarch64_call_info info
;
1798 /* We need to know what the type of the called function is in order
1799 to determine the number of named/anonymous arguments for the
1800 actual argument placement, and the return type in order to handle
1801 return value correctly.
1803 The generic code above us views the decision of return in memory
1804 or return in registers as a two stage processes. The language
1805 handler is consulted first and may decide to return in memory (eg
1806 class with copy constructor returned by value), this will cause
1807 the generic code to allocate space AND insert an initial leading
1810 If the language code does not decide to pass in memory then the
1811 target code is consulted.
1813 If the language code decides to pass in memory we want to move
1814 the pointer inserted as the initial argument from the argument
1815 list and into X8, the conventional AArch64 struct return pointer
1818 /* Set the return address. For the AArch64, the return breakpoint
1819 is always at BP_ADDR. */
1820 regcache_cooked_write_unsigned (regcache
, AARCH64_LR_REGNUM
, bp_addr
);
1822 /* If we were given an initial argument for the return slot, lose it. */
1823 if (return_method
== return_method_hidden_param
)
1829 /* The struct_return pointer occupies X8. */
1830 if (return_method
!= return_method_normal
)
1832 aarch64_debug_printf ("struct return in %s = 0x%s",
1833 gdbarch_register_name
1834 (gdbarch
, AARCH64_STRUCT_RETURN_REGNUM
),
1835 paddress (gdbarch
, struct_addr
));
1837 regcache_cooked_write_unsigned (regcache
, AARCH64_STRUCT_RETURN_REGNUM
,
1841 for (argnum
= 0; argnum
< nargs
; argnum
++)
1843 struct value
*arg
= args
[argnum
];
1844 struct type
*arg_type
, *fundamental_type
;
1847 arg_type
= check_typedef (value_type (arg
));
1848 len
= TYPE_LENGTH (arg_type
);
1850 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1851 if there are enough spare registers. */
1852 if (aapcs_is_vfp_call_or_return_candidate (arg_type
, &elements
,
1855 if (info
.nsrn
+ elements
<= 8)
1857 /* We know that we have sufficient registers available therefore
1858 this will never need to fallback to the stack. */
1859 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, &info
, arg_type
,
1861 gdb_assert_not_reached ("Failed to push args");
1866 pass_on_stack (&info
, arg_type
, arg
);
1871 switch (arg_type
->code ())
1874 case TYPE_CODE_BOOL
:
1875 case TYPE_CODE_CHAR
:
1876 case TYPE_CODE_RANGE
:
1877 case TYPE_CODE_ENUM
:
1880 /* Promote to 32 bit integer. */
1881 if (arg_type
->is_unsigned ())
1882 arg_type
= builtin_type (gdbarch
)->builtin_uint32
;
1884 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
1885 arg
= value_cast (arg_type
, arg
);
1887 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1890 case TYPE_CODE_STRUCT
:
1891 case TYPE_CODE_ARRAY
:
1892 case TYPE_CODE_UNION
:
1895 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1896 invisible reference. */
1898 /* Allocate aligned storage. */
1899 sp
= align_down (sp
- len
, 16);
1901 /* Write the real data into the stack. */
1902 write_memory (sp
, value_contents (arg
), len
);
1904 /* Construct the indirection. */
1905 arg_type
= lookup_pointer_type (arg_type
);
1906 arg
= value_from_pointer (arg_type
, sp
);
1907 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1910 /* PCS C.15 / C.18 multiple values pass. */
1911 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1915 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1920 /* Make sure stack retains 16 byte alignment. */
1922 sp
-= 16 - (info
.nsaa
& 15);
1924 while (!info
.si
.empty ())
1926 const stack_item_t
&si
= info
.si
.back ();
1929 if (si
.data
!= NULL
)
1930 write_memory (sp
, si
.data
, si
.len
);
1931 info
.si
.pop_back ();
1934 /* Finally, update the SP register. */
1935 regcache_cooked_write_unsigned (regcache
, AARCH64_SP_REGNUM
, sp
);
1940 /* Implement the "frame_align" gdbarch method. */
1943 aarch64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1945 /* Align the stack to sixteen bytes. */
1946 return sp
& ~(CORE_ADDR
) 15;
1949 /* Return the type for an AdvSISD Q register. */
1951 static struct type
*
1952 aarch64_vnq_type (struct gdbarch
*gdbarch
)
1954 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1956 if (tdep
->vnq_type
== NULL
)
1961 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1964 elem
= builtin_type (gdbarch
)->builtin_uint128
;
1965 append_composite_type_field (t
, "u", elem
);
1967 elem
= builtin_type (gdbarch
)->builtin_int128
;
1968 append_composite_type_field (t
, "s", elem
);
1973 return tdep
->vnq_type
;
1976 /* Return the type for an AdvSISD D register. */
1978 static struct type
*
1979 aarch64_vnd_type (struct gdbarch
*gdbarch
)
1981 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1983 if (tdep
->vnd_type
== NULL
)
1988 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1991 elem
= builtin_type (gdbarch
)->builtin_double
;
1992 append_composite_type_field (t
, "f", elem
);
1994 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1995 append_composite_type_field (t
, "u", elem
);
1997 elem
= builtin_type (gdbarch
)->builtin_int64
;
1998 append_composite_type_field (t
, "s", elem
);
2003 return tdep
->vnd_type
;
2006 /* Return the type for an AdvSISD S register. */
2008 static struct type
*
2009 aarch64_vns_type (struct gdbarch
*gdbarch
)
2011 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2013 if (tdep
->vns_type
== NULL
)
2018 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
2021 elem
= builtin_type (gdbarch
)->builtin_float
;
2022 append_composite_type_field (t
, "f", elem
);
2024 elem
= builtin_type (gdbarch
)->builtin_uint32
;
2025 append_composite_type_field (t
, "u", elem
);
2027 elem
= builtin_type (gdbarch
)->builtin_int32
;
2028 append_composite_type_field (t
, "s", elem
);
2033 return tdep
->vns_type
;
2036 /* Return the type for an AdvSISD H register. */
2038 static struct type
*
2039 aarch64_vnh_type (struct gdbarch
*gdbarch
)
2041 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2043 if (tdep
->vnh_type
== NULL
)
2048 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
2051 elem
= builtin_type (gdbarch
)->builtin_bfloat16
;
2052 append_composite_type_field (t
, "bf", elem
);
2054 elem
= builtin_type (gdbarch
)->builtin_half
;
2055 append_composite_type_field (t
, "f", elem
);
2057 elem
= builtin_type (gdbarch
)->builtin_uint16
;
2058 append_composite_type_field (t
, "u", elem
);
2060 elem
= builtin_type (gdbarch
)->builtin_int16
;
2061 append_composite_type_field (t
, "s", elem
);
2066 return tdep
->vnh_type
;
2069 /* Return the type for an AdvSISD B register. */
2071 static struct type
*
2072 aarch64_vnb_type (struct gdbarch
*gdbarch
)
2074 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2076 if (tdep
->vnb_type
== NULL
)
2081 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
2084 elem
= builtin_type (gdbarch
)->builtin_uint8
;
2085 append_composite_type_field (t
, "u", elem
);
2087 elem
= builtin_type (gdbarch
)->builtin_int8
;
2088 append_composite_type_field (t
, "s", elem
);
2093 return tdep
->vnb_type
;
2096 /* Return the type for an AdvSISD V register. */
2098 static struct type
*
2099 aarch64_vnv_type (struct gdbarch
*gdbarch
)
2101 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2103 if (tdep
->vnv_type
== NULL
)
2105 /* The other AArch64 pseudo registers (Q,D,H,S,B) refer to a single value
2106 slice from the non-pseudo vector registers. However NEON V registers
2107 are always vector registers, and need constructing as such. */
2108 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2110 struct type
*t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnv",
2113 struct type
*sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
2115 append_composite_type_field (sub
, "f",
2116 init_vector_type (bt
->builtin_double
, 2));
2117 append_composite_type_field (sub
, "u",
2118 init_vector_type (bt
->builtin_uint64
, 2));
2119 append_composite_type_field (sub
, "s",
2120 init_vector_type (bt
->builtin_int64
, 2));
2121 append_composite_type_field (t
, "d", sub
);
2123 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
2125 append_composite_type_field (sub
, "f",
2126 init_vector_type (bt
->builtin_float
, 4));
2127 append_composite_type_field (sub
, "u",
2128 init_vector_type (bt
->builtin_uint32
, 4));
2129 append_composite_type_field (sub
, "s",
2130 init_vector_type (bt
->builtin_int32
, 4));
2131 append_composite_type_field (t
, "s", sub
);
2133 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
2135 append_composite_type_field (sub
, "bf",
2136 init_vector_type (bt
->builtin_bfloat16
, 8));
2137 append_composite_type_field (sub
, "f",
2138 init_vector_type (bt
->builtin_half
, 8));
2139 append_composite_type_field (sub
, "u",
2140 init_vector_type (bt
->builtin_uint16
, 8));
2141 append_composite_type_field (sub
, "s",
2142 init_vector_type (bt
->builtin_int16
, 8));
2143 append_composite_type_field (t
, "h", sub
);
2145 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
2147 append_composite_type_field (sub
, "u",
2148 init_vector_type (bt
->builtin_uint8
, 16));
2149 append_composite_type_field (sub
, "s",
2150 init_vector_type (bt
->builtin_int8
, 16));
2151 append_composite_type_field (t
, "b", sub
);
2153 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
2155 append_composite_type_field (sub
, "u",
2156 init_vector_type (bt
->builtin_uint128
, 1));
2157 append_composite_type_field (sub
, "s",
2158 init_vector_type (bt
->builtin_int128
, 1));
2159 append_composite_type_field (t
, "q", sub
);
2164 return tdep
->vnv_type
;
2167 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
2170 aarch64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
2172 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2174 if (reg
>= AARCH64_DWARF_X0
&& reg
<= AARCH64_DWARF_X0
+ 30)
2175 return AARCH64_X0_REGNUM
+ reg
- AARCH64_DWARF_X0
;
2177 if (reg
== AARCH64_DWARF_SP
)
2178 return AARCH64_SP_REGNUM
;
2180 if (reg
>= AARCH64_DWARF_V0
&& reg
<= AARCH64_DWARF_V0
+ 31)
2181 return AARCH64_V0_REGNUM
+ reg
- AARCH64_DWARF_V0
;
2183 if (reg
== AARCH64_DWARF_SVE_VG
)
2184 return AARCH64_SVE_VG_REGNUM
;
2186 if (reg
== AARCH64_DWARF_SVE_FFR
)
2187 return AARCH64_SVE_FFR_REGNUM
;
2189 if (reg
>= AARCH64_DWARF_SVE_P0
&& reg
<= AARCH64_DWARF_SVE_P0
+ 15)
2190 return AARCH64_SVE_P0_REGNUM
+ reg
- AARCH64_DWARF_SVE_P0
;
2192 if (reg
>= AARCH64_DWARF_SVE_Z0
&& reg
<= AARCH64_DWARF_SVE_Z0
+ 15)
2193 return AARCH64_SVE_Z0_REGNUM
+ reg
- AARCH64_DWARF_SVE_Z0
;
2195 if (tdep
->has_pauth ())
2197 if (reg
>= AARCH64_DWARF_PAUTH_DMASK
&& reg
<= AARCH64_DWARF_PAUTH_CMASK
)
2198 return tdep
->pauth_reg_base
+ reg
- AARCH64_DWARF_PAUTH_DMASK
;
2200 if (reg
== AARCH64_DWARF_PAUTH_RA_STATE
)
2201 return tdep
->pauth_ra_state_regnum
;
2207 /* Implement the "print_insn" gdbarch method. */
2210 aarch64_gdb_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
2212 info
->symbols
= NULL
;
2213 return default_print_insn (memaddr
, info
);
2216 /* AArch64 BRK software debug mode instruction.
2217 Note that AArch64 code is always little-endian.
2218 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
2219 constexpr gdb_byte aarch64_default_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
2221 typedef BP_MANIPULATION (aarch64_default_breakpoint
) aarch64_breakpoint
;
2223 /* Extract from an array REGS containing the (raw) register state a
2224 function return value of type TYPE, and copy that, in virtual
2225 format, into VALBUF. */
2228 aarch64_extract_return_value (struct type
*type
, struct regcache
*regs
,
2231 struct gdbarch
*gdbarch
= regs
->arch ();
2232 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2234 struct type
*fundamental_type
;
2236 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2239 int len
= TYPE_LENGTH (fundamental_type
);
2241 for (int i
= 0; i
< elements
; i
++)
2243 int regno
= AARCH64_V0_REGNUM
+ i
;
2244 /* Enough space for a full vector register. */
2245 gdb_byte buf
[register_size (gdbarch
, regno
)];
2246 gdb_assert (len
<= sizeof (buf
));
2248 aarch64_debug_printf
2249 ("read HFA or HVA return value element %d from %s",
2250 i
+ 1, gdbarch_register_name (gdbarch
, regno
));
2252 regs
->cooked_read (regno
, buf
);
2254 memcpy (valbuf
, buf
, len
);
2258 else if (type
->code () == TYPE_CODE_INT
2259 || type
->code () == TYPE_CODE_CHAR
2260 || type
->code () == TYPE_CODE_BOOL
2261 || type
->code () == TYPE_CODE_PTR
2262 || TYPE_IS_REFERENCE (type
)
2263 || type
->code () == TYPE_CODE_ENUM
)
2265 /* If the type is a plain integer, then the access is
2266 straight-forward. Otherwise we have to play around a bit
2268 int len
= TYPE_LENGTH (type
);
2269 int regno
= AARCH64_X0_REGNUM
;
2274 /* By using store_unsigned_integer we avoid having to do
2275 anything special for small big-endian values. */
2276 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2277 store_unsigned_integer (valbuf
,
2278 (len
> X_REGISTER_SIZE
2279 ? X_REGISTER_SIZE
: len
), byte_order
, tmp
);
2280 len
-= X_REGISTER_SIZE
;
2281 valbuf
+= X_REGISTER_SIZE
;
2286 /* For a structure or union the behaviour is as if the value had
2287 been stored to word-aligned memory and then loaded into
2288 registers with 64-bit load instruction(s). */
2289 int len
= TYPE_LENGTH (type
);
2290 int regno
= AARCH64_X0_REGNUM
;
2291 bfd_byte buf
[X_REGISTER_SIZE
];
2295 regs
->cooked_read (regno
++, buf
);
2296 memcpy (valbuf
, buf
, len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2297 len
-= X_REGISTER_SIZE
;
2298 valbuf
+= X_REGISTER_SIZE
;
2304 /* Will a function return an aggregate type in memory or in a
2305 register? Return 0 if an aggregate type can be returned in a
2306 register, 1 if it must be returned in memory. */
2309 aarch64_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2311 type
= check_typedef (type
);
2313 struct type
*fundamental_type
;
2315 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2318 /* v0-v7 are used to return values and one register is allocated
2319 for one member. However, HFA or HVA has at most four members. */
2323 if (TYPE_LENGTH (type
) > 16)
2325 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2326 invisible reference. */
2334 /* Write into appropriate registers a function return value of type
2335 TYPE, given in virtual format. */
2338 aarch64_store_return_value (struct type
*type
, struct regcache
*regs
,
2339 const gdb_byte
*valbuf
)
2341 struct gdbarch
*gdbarch
= regs
->arch ();
2342 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2344 struct type
*fundamental_type
;
2346 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2349 int len
= TYPE_LENGTH (fundamental_type
);
2351 for (int i
= 0; i
< elements
; i
++)
2353 int regno
= AARCH64_V0_REGNUM
+ i
;
2354 /* Enough space for a full vector register. */
2355 gdb_byte tmpbuf
[register_size (gdbarch
, regno
)];
2356 gdb_assert (len
<= sizeof (tmpbuf
));
2358 aarch64_debug_printf
2359 ("write HFA or HVA return value element %d to %s",
2360 i
+ 1, gdbarch_register_name (gdbarch
, regno
));
2362 memcpy (tmpbuf
, valbuf
,
2363 len
> V_REGISTER_SIZE
? V_REGISTER_SIZE
: len
);
2364 regs
->cooked_write (regno
, tmpbuf
);
2368 else if (type
->code () == TYPE_CODE_INT
2369 || type
->code () == TYPE_CODE_CHAR
2370 || type
->code () == TYPE_CODE_BOOL
2371 || type
->code () == TYPE_CODE_PTR
2372 || TYPE_IS_REFERENCE (type
)
2373 || type
->code () == TYPE_CODE_ENUM
)
2375 if (TYPE_LENGTH (type
) <= X_REGISTER_SIZE
)
2377 /* Values of one word or less are zero/sign-extended and
2379 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2380 LONGEST val
= unpack_long (type
, valbuf
);
2382 store_signed_integer (tmpbuf
, X_REGISTER_SIZE
, byte_order
, val
);
2383 regs
->cooked_write (AARCH64_X0_REGNUM
, tmpbuf
);
2387 /* Integral values greater than one word are stored in
2388 consecutive registers starting with r0. This will always
2389 be a multiple of the regiser size. */
2390 int len
= TYPE_LENGTH (type
);
2391 int regno
= AARCH64_X0_REGNUM
;
2395 regs
->cooked_write (regno
++, valbuf
);
2396 len
-= X_REGISTER_SIZE
;
2397 valbuf
+= X_REGISTER_SIZE
;
2403 /* For a structure or union the behaviour is as if the value had
2404 been stored to word-aligned memory and then loaded into
2405 registers with 64-bit load instruction(s). */
2406 int len
= TYPE_LENGTH (type
);
2407 int regno
= AARCH64_X0_REGNUM
;
2408 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2412 memcpy (tmpbuf
, valbuf
,
2413 len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2414 regs
->cooked_write (regno
++, tmpbuf
);
2415 len
-= X_REGISTER_SIZE
;
2416 valbuf
+= X_REGISTER_SIZE
;
2421 /* Implement the "return_value" gdbarch method. */
2423 static enum return_value_convention
2424 aarch64_return_value (struct gdbarch
*gdbarch
, struct value
*func_value
,
2425 struct type
*valtype
, struct regcache
*regcache
,
2426 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2429 if (valtype
->code () == TYPE_CODE_STRUCT
2430 || valtype
->code () == TYPE_CODE_UNION
2431 || valtype
->code () == TYPE_CODE_ARRAY
)
2433 if (aarch64_return_in_memory (gdbarch
, valtype
))
2435 aarch64_debug_printf ("return value in memory");
2436 return RETURN_VALUE_STRUCT_CONVENTION
;
2441 aarch64_store_return_value (valtype
, regcache
, writebuf
);
2444 aarch64_extract_return_value (valtype
, regcache
, readbuf
);
2446 aarch64_debug_printf ("return value in registers");
2448 return RETURN_VALUE_REGISTER_CONVENTION
;
2451 /* Implement the "get_longjmp_target" gdbarch method. */
2454 aarch64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2457 gdb_byte buf
[X_REGISTER_SIZE
];
2458 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2459 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2460 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2462 jb_addr
= get_frame_register_unsigned (frame
, AARCH64_X0_REGNUM
);
2464 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2468 *pc
= extract_unsigned_integer (buf
, X_REGISTER_SIZE
, byte_order
);
2472 /* Implement the "gen_return_address" gdbarch method. */
2475 aarch64_gen_return_address (struct gdbarch
*gdbarch
,
2476 struct agent_expr
*ax
, struct axs_value
*value
,
2479 value
->type
= register_type (gdbarch
, AARCH64_LR_REGNUM
);
2480 value
->kind
= axs_lvalue_register
;
2481 value
->u
.reg
= AARCH64_LR_REGNUM
;
2485 /* Return the pseudo register name corresponding to register regnum. */
2488 aarch64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
2490 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2492 static const char *const q_name
[] =
2494 "q0", "q1", "q2", "q3",
2495 "q4", "q5", "q6", "q7",
2496 "q8", "q9", "q10", "q11",
2497 "q12", "q13", "q14", "q15",
2498 "q16", "q17", "q18", "q19",
2499 "q20", "q21", "q22", "q23",
2500 "q24", "q25", "q26", "q27",
2501 "q28", "q29", "q30", "q31",
2504 static const char *const d_name
[] =
2506 "d0", "d1", "d2", "d3",
2507 "d4", "d5", "d6", "d7",
2508 "d8", "d9", "d10", "d11",
2509 "d12", "d13", "d14", "d15",
2510 "d16", "d17", "d18", "d19",
2511 "d20", "d21", "d22", "d23",
2512 "d24", "d25", "d26", "d27",
2513 "d28", "d29", "d30", "d31",
2516 static const char *const s_name
[] =
2518 "s0", "s1", "s2", "s3",
2519 "s4", "s5", "s6", "s7",
2520 "s8", "s9", "s10", "s11",
2521 "s12", "s13", "s14", "s15",
2522 "s16", "s17", "s18", "s19",
2523 "s20", "s21", "s22", "s23",
2524 "s24", "s25", "s26", "s27",
2525 "s28", "s29", "s30", "s31",
2528 static const char *const h_name
[] =
2530 "h0", "h1", "h2", "h3",
2531 "h4", "h5", "h6", "h7",
2532 "h8", "h9", "h10", "h11",
2533 "h12", "h13", "h14", "h15",
2534 "h16", "h17", "h18", "h19",
2535 "h20", "h21", "h22", "h23",
2536 "h24", "h25", "h26", "h27",
2537 "h28", "h29", "h30", "h31",
2540 static const char *const b_name
[] =
2542 "b0", "b1", "b2", "b3",
2543 "b4", "b5", "b6", "b7",
2544 "b8", "b9", "b10", "b11",
2545 "b12", "b13", "b14", "b15",
2546 "b16", "b17", "b18", "b19",
2547 "b20", "b21", "b22", "b23",
2548 "b24", "b25", "b26", "b27",
2549 "b28", "b29", "b30", "b31",
2552 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2554 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2555 return q_name
[p_regnum
- AARCH64_Q0_REGNUM
];
2557 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2558 return d_name
[p_regnum
- AARCH64_D0_REGNUM
];
2560 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2561 return s_name
[p_regnum
- AARCH64_S0_REGNUM
];
2563 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2564 return h_name
[p_regnum
- AARCH64_H0_REGNUM
];
2566 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2567 return b_name
[p_regnum
- AARCH64_B0_REGNUM
];
2569 if (tdep
->has_sve ())
2571 static const char *const sve_v_name
[] =
2573 "v0", "v1", "v2", "v3",
2574 "v4", "v5", "v6", "v7",
2575 "v8", "v9", "v10", "v11",
2576 "v12", "v13", "v14", "v15",
2577 "v16", "v17", "v18", "v19",
2578 "v20", "v21", "v22", "v23",
2579 "v24", "v25", "v26", "v27",
2580 "v28", "v29", "v30", "v31",
2583 if (p_regnum
>= AARCH64_SVE_V0_REGNUM
2584 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2585 return sve_v_name
[p_regnum
- AARCH64_SVE_V0_REGNUM
];
2588 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2589 prevents it from being read by methods such as
2590 mi_cmd_trace_frame_collected. */
2591 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2594 internal_error (__FILE__
, __LINE__
,
2595 _("aarch64_pseudo_register_name: bad register number %d"),
2599 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2601 static struct type
*
2602 aarch64_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2604 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2606 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2608 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2609 return aarch64_vnq_type (gdbarch
);
2611 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2612 return aarch64_vnd_type (gdbarch
);
2614 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2615 return aarch64_vns_type (gdbarch
);
2617 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2618 return aarch64_vnh_type (gdbarch
);
2620 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2621 return aarch64_vnb_type (gdbarch
);
2623 if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2624 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2625 return aarch64_vnv_type (gdbarch
);
2627 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2628 return builtin_type (gdbarch
)->builtin_uint64
;
2630 internal_error (__FILE__
, __LINE__
,
2631 _("aarch64_pseudo_register_type: bad register number %d"),
2635 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2638 aarch64_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2639 struct reggroup
*group
)
2641 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2643 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2645 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2646 return group
== all_reggroup
|| group
== vector_reggroup
;
2647 else if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2648 return (group
== all_reggroup
|| group
== vector_reggroup
2649 || group
== float_reggroup
);
2650 else if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2651 return (group
== all_reggroup
|| group
== vector_reggroup
2652 || group
== float_reggroup
);
2653 else if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2654 return group
== all_reggroup
|| group
== vector_reggroup
;
2655 else if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2656 return group
== all_reggroup
|| group
== vector_reggroup
;
2657 else if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2658 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2659 return group
== all_reggroup
|| group
== vector_reggroup
;
2660 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2661 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2664 return group
== all_reggroup
;
2667 /* Helper for aarch64_pseudo_read_value. */
2669 static struct value
*
2670 aarch64_pseudo_read_value_1 (struct gdbarch
*gdbarch
,
2671 readable_regcache
*regcache
, int regnum_offset
,
2672 int regsize
, struct value
*result_value
)
2674 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2676 /* Enough space for a full vector register. */
2677 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2678 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2680 if (regcache
->raw_read (v_regnum
, reg_buf
) != REG_VALID
)
2681 mark_value_bytes_unavailable (result_value
, 0,
2682 TYPE_LENGTH (value_type (result_value
)));
2684 memcpy (value_contents_raw (result_value
), reg_buf
, regsize
);
2686 return result_value
;
2689 /* Implement the "pseudo_register_read_value" gdbarch method. */
2691 static struct value
*
2692 aarch64_pseudo_read_value (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2695 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2696 struct value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
2698 VALUE_LVAL (result_value
) = lval_register
;
2699 VALUE_REGNUM (result_value
) = regnum
;
2701 regnum
-= gdbarch_num_regs (gdbarch
);
2703 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2704 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2705 regnum
- AARCH64_Q0_REGNUM
,
2706 Q_REGISTER_SIZE
, result_value
);
2708 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2709 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2710 regnum
- AARCH64_D0_REGNUM
,
2711 D_REGISTER_SIZE
, result_value
);
2713 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2714 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2715 regnum
- AARCH64_S0_REGNUM
,
2716 S_REGISTER_SIZE
, result_value
);
2718 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2719 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2720 regnum
- AARCH64_H0_REGNUM
,
2721 H_REGISTER_SIZE
, result_value
);
2723 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2724 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2725 regnum
- AARCH64_B0_REGNUM
,
2726 B_REGISTER_SIZE
, result_value
);
2728 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2729 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2730 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2731 regnum
- AARCH64_SVE_V0_REGNUM
,
2732 V_REGISTER_SIZE
, result_value
);
2734 gdb_assert_not_reached ("regnum out of bound");
2737 /* Helper for aarch64_pseudo_write. */
2740 aarch64_pseudo_write_1 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2741 int regnum_offset
, int regsize
, const gdb_byte
*buf
)
2743 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2745 /* Enough space for a full vector register. */
2746 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2747 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2749 /* Ensure the register buffer is zero, we want gdb writes of the
2750 various 'scalar' pseudo registers to behavior like architectural
2751 writes, register width bytes are written the remainder are set to
2753 memset (reg_buf
, 0, register_size (gdbarch
, AARCH64_V0_REGNUM
));
2755 memcpy (reg_buf
, buf
, regsize
);
2756 regcache
->raw_write (v_regnum
, reg_buf
);
2759 /* Implement the "pseudo_register_write" gdbarch method. */
2762 aarch64_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2763 int regnum
, const gdb_byte
*buf
)
2765 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2766 regnum
-= gdbarch_num_regs (gdbarch
);
2768 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2769 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2770 regnum
- AARCH64_Q0_REGNUM
, Q_REGISTER_SIZE
,
2773 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2774 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2775 regnum
- AARCH64_D0_REGNUM
, D_REGISTER_SIZE
,
2778 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2779 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2780 regnum
- AARCH64_S0_REGNUM
, S_REGISTER_SIZE
,
2783 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2784 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2785 regnum
- AARCH64_H0_REGNUM
, H_REGISTER_SIZE
,
2788 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2789 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2790 regnum
- AARCH64_B0_REGNUM
, B_REGISTER_SIZE
,
2793 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2794 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2795 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2796 regnum
- AARCH64_SVE_V0_REGNUM
,
2797 V_REGISTER_SIZE
, buf
);
2799 gdb_assert_not_reached ("regnum out of bound");
2802 /* Callback function for user_reg_add. */
2804 static struct value
*
2805 value_of_aarch64_user_reg (struct frame_info
*frame
, const void *baton
)
2807 const int *reg_p
= (const int *) baton
;
2809 return value_of_register (*reg_p
, frame
);
2813 /* Implement the "software_single_step" gdbarch method, needed to
2814 single step through atomic sequences on AArch64. */
2816 static std::vector
<CORE_ADDR
>
2817 aarch64_software_single_step (struct regcache
*regcache
)
2819 struct gdbarch
*gdbarch
= regcache
->arch ();
2820 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2821 const int insn_size
= 4;
2822 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2823 CORE_ADDR pc
= regcache_read_pc (regcache
);
2824 CORE_ADDR breaks
[2] = { CORE_ADDR_MAX
, CORE_ADDR_MAX
};
2826 CORE_ADDR closing_insn
= 0;
2827 uint32_t insn
= read_memory_unsigned_integer (loc
, insn_size
,
2828 byte_order_for_code
);
2831 int bc_insn_count
= 0; /* Conditional branch instruction count. */
2832 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2835 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2838 /* Look for a Load Exclusive instruction which begins the sequence. */
2839 if (inst
.opcode
->iclass
!= ldstexcl
|| bit (insn
, 22) == 0)
2842 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2845 insn
= read_memory_unsigned_integer (loc
, insn_size
,
2846 byte_order_for_code
);
2848 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2850 /* Check if the instruction is a conditional branch. */
2851 if (inst
.opcode
->iclass
== condbranch
)
2853 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_ADDR_PCREL19
);
2855 if (bc_insn_count
>= 1)
2858 /* It is, so we'll try to set a breakpoint at the destination. */
2859 breaks
[1] = loc
+ inst
.operands
[0].imm
.value
;
2865 /* Look for the Store Exclusive which closes the atomic sequence. */
2866 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22) == 0)
2873 /* We didn't find a closing Store Exclusive instruction, fall back. */
2877 /* Insert breakpoint after the end of the atomic sequence. */
2878 breaks
[0] = loc
+ insn_size
;
2880 /* Check for duplicated breakpoints, and also check that the second
2881 breakpoint is not within the atomic sequence. */
2883 && (breaks
[1] == breaks
[0]
2884 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
2885 last_breakpoint
= 0;
2887 std::vector
<CORE_ADDR
> next_pcs
;
2889 /* Insert the breakpoint at the end of the sequence, and one at the
2890 destination of the conditional branch, if it exists. */
2891 for (index
= 0; index
<= last_breakpoint
; index
++)
2892 next_pcs
.push_back (breaks
[index
]);
2897 struct aarch64_displaced_step_copy_insn_closure
2898 : public displaced_step_copy_insn_closure
2900 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2901 is being displaced stepping. */
2904 /* PC adjustment offset after displaced stepping. If 0, then we don't
2905 write the PC back, assuming the PC is already the right address. */
2906 int32_t pc_adjust
= 0;
2909 /* Data when visiting instructions for displaced stepping. */
2911 struct aarch64_displaced_step_data
2913 struct aarch64_insn_data base
;
2915 /* The address where the instruction will be executed at. */
2917 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2918 uint32_t insn_buf
[AARCH64_DISPLACED_MODIFIED_INSNS
];
2919 /* Number of instructions in INSN_BUF. */
2920 unsigned insn_count
;
2921 /* Registers when doing displaced stepping. */
2922 struct regcache
*regs
;
2924 aarch64_displaced_step_copy_insn_closure
*dsc
;
2927 /* Implementation of aarch64_insn_visitor method "b". */
2930 aarch64_displaced_step_b (const int is_bl
, const int32_t offset
,
2931 struct aarch64_insn_data
*data
)
2933 struct aarch64_displaced_step_data
*dsd
2934 = (struct aarch64_displaced_step_data
*) data
;
2935 int64_t new_offset
= data
->insn_addr
- dsd
->new_addr
+ offset
;
2937 if (can_encode_int32 (new_offset
, 28))
2939 /* Emit B rather than BL, because executing BL on a new address
2940 will get the wrong address into LR. In order to avoid this,
2941 we emit B, and update LR if the instruction is BL. */
2942 emit_b (dsd
->insn_buf
, 0, new_offset
);
2948 emit_nop (dsd
->insn_buf
);
2950 dsd
->dsc
->pc_adjust
= offset
;
2956 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
2957 data
->insn_addr
+ 4);
2961 /* Implementation of aarch64_insn_visitor method "b_cond". */
2964 aarch64_displaced_step_b_cond (const unsigned cond
, const int32_t offset
,
2965 struct aarch64_insn_data
*data
)
2967 struct aarch64_displaced_step_data
*dsd
2968 = (struct aarch64_displaced_step_data
*) data
;
2970 /* GDB has to fix up PC after displaced step this instruction
2971 differently according to the condition is true or false. Instead
2972 of checking COND against conditional flags, we can use
2973 the following instructions, and GDB can tell how to fix up PC
2974 according to the PC value.
2976 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2982 emit_bcond (dsd
->insn_buf
, cond
, 8);
2983 dsd
->dsc
->cond
= true;
2984 dsd
->dsc
->pc_adjust
= offset
;
2985 dsd
->insn_count
= 1;
2988 /* Dynamically allocate a new register. If we know the register
2989 statically, we should make it a global as above instead of using this
2992 static struct aarch64_register
2993 aarch64_register (unsigned num
, int is64
)
2995 return (struct aarch64_register
) { num
, is64
};
2998 /* Implementation of aarch64_insn_visitor method "cb". */
3001 aarch64_displaced_step_cb (const int32_t offset
, const int is_cbnz
,
3002 const unsigned rn
, int is64
,
3003 struct aarch64_insn_data
*data
)
3005 struct aarch64_displaced_step_data
*dsd
3006 = (struct aarch64_displaced_step_data
*) data
;
3008 /* The offset is out of range for a compare and branch
3009 instruction. We can use the following instructions instead:
3011 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
3016 emit_cb (dsd
->insn_buf
, is_cbnz
, aarch64_register (rn
, is64
), 8);
3017 dsd
->insn_count
= 1;
3018 dsd
->dsc
->cond
= true;
3019 dsd
->dsc
->pc_adjust
= offset
;
3022 /* Implementation of aarch64_insn_visitor method "tb". */
3025 aarch64_displaced_step_tb (const int32_t offset
, int is_tbnz
,
3026 const unsigned rt
, unsigned bit
,
3027 struct aarch64_insn_data
*data
)
3029 struct aarch64_displaced_step_data
*dsd
3030 = (struct aarch64_displaced_step_data
*) data
;
3032 /* The offset is out of range for a test bit and branch
3033 instruction We can use the following instructions instead:
3035 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
3041 emit_tb (dsd
->insn_buf
, is_tbnz
, bit
, aarch64_register (rt
, 1), 8);
3042 dsd
->insn_count
= 1;
3043 dsd
->dsc
->cond
= true;
3044 dsd
->dsc
->pc_adjust
= offset
;
3047 /* Implementation of aarch64_insn_visitor method "adr". */
3050 aarch64_displaced_step_adr (const int32_t offset
, const unsigned rd
,
3051 const int is_adrp
, struct aarch64_insn_data
*data
)
3053 struct aarch64_displaced_step_data
*dsd
3054 = (struct aarch64_displaced_step_data
*) data
;
3055 /* We know exactly the address the ADR{P,} instruction will compute.
3056 We can just write it to the destination register. */
3057 CORE_ADDR address
= data
->insn_addr
+ offset
;
3061 /* Clear the lower 12 bits of the offset to get the 4K page. */
3062 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
3066 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
3069 dsd
->dsc
->pc_adjust
= 4;
3070 emit_nop (dsd
->insn_buf
);
3071 dsd
->insn_count
= 1;
3074 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
3077 aarch64_displaced_step_ldr_literal (const int32_t offset
, const int is_sw
,
3078 const unsigned rt
, const int is64
,
3079 struct aarch64_insn_data
*data
)
3081 struct aarch64_displaced_step_data
*dsd
3082 = (struct aarch64_displaced_step_data
*) data
;
3083 CORE_ADDR address
= data
->insn_addr
+ offset
;
3084 struct aarch64_memory_operand zero
= { MEMORY_OPERAND_OFFSET
, 0 };
3086 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rt
,
3090 dsd
->insn_count
= emit_ldrsw (dsd
->insn_buf
, aarch64_register (rt
, 1),
3091 aarch64_register (rt
, 1), zero
);
3093 dsd
->insn_count
= emit_ldr (dsd
->insn_buf
, aarch64_register (rt
, is64
),
3094 aarch64_register (rt
, 1), zero
);
3096 dsd
->dsc
->pc_adjust
= 4;
3099 /* Implementation of aarch64_insn_visitor method "others". */
3102 aarch64_displaced_step_others (const uint32_t insn
,
3103 struct aarch64_insn_data
*data
)
3105 struct aarch64_displaced_step_data
*dsd
3106 = (struct aarch64_displaced_step_data
*) data
;
3108 uint32_t masked_insn
= (insn
& CLEAR_Rn_MASK
);
3109 if (masked_insn
== BLR
)
3111 /* Emit a BR to the same register and then update LR to the original
3112 address (similar to aarch64_displaced_step_b). */
3113 aarch64_emit_insn (dsd
->insn_buf
, insn
& 0xffdfffff);
3114 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
3115 data
->insn_addr
+ 4);
3118 aarch64_emit_insn (dsd
->insn_buf
, insn
);
3119 dsd
->insn_count
= 1;
3121 if (masked_insn
== RET
|| masked_insn
== BR
|| masked_insn
== BLR
)
3122 dsd
->dsc
->pc_adjust
= 0;
3124 dsd
->dsc
->pc_adjust
= 4;
3127 static const struct aarch64_insn_visitor visitor
=
3129 aarch64_displaced_step_b
,
3130 aarch64_displaced_step_b_cond
,
3131 aarch64_displaced_step_cb
,
3132 aarch64_displaced_step_tb
,
3133 aarch64_displaced_step_adr
,
3134 aarch64_displaced_step_ldr_literal
,
3135 aarch64_displaced_step_others
,
3138 /* Implement the "displaced_step_copy_insn" gdbarch method. */
3140 displaced_step_copy_insn_closure_up
3141 aarch64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
3142 CORE_ADDR from
, CORE_ADDR to
,
3143 struct regcache
*regs
)
3145 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3146 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
3147 struct aarch64_displaced_step_data dsd
;
3150 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
3153 /* Look for a Load Exclusive instruction which begins the sequence. */
3154 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22))
3156 /* We can't displaced step atomic sequences. */
3160 std::unique_ptr
<aarch64_displaced_step_copy_insn_closure
> dsc
3161 (new aarch64_displaced_step_copy_insn_closure
);
3162 dsd
.base
.insn_addr
= from
;
3165 dsd
.dsc
= dsc
.get ();
3167 aarch64_relocate_instruction (insn
, &visitor
,
3168 (struct aarch64_insn_data
*) &dsd
);
3169 gdb_assert (dsd
.insn_count
<= AARCH64_DISPLACED_MODIFIED_INSNS
);
3171 if (dsd
.insn_count
!= 0)
3175 /* Instruction can be relocated to scratch pad. Copy
3176 relocated instruction(s) there. */
3177 for (i
= 0; i
< dsd
.insn_count
; i
++)
3179 displaced_debug_printf ("writing insn %.8x at %s",
3181 paddress (gdbarch
, to
+ i
* 4));
3183 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
3184 (ULONGEST
) dsd
.insn_buf
[i
]);
3192 /* This is a work around for a problem with g++ 4.8. */
3193 return displaced_step_copy_insn_closure_up (dsc
.release ());
3196 /* Implement the "displaced_step_fixup" gdbarch method. */
3199 aarch64_displaced_step_fixup (struct gdbarch
*gdbarch
,
3200 struct displaced_step_copy_insn_closure
*dsc_
,
3201 CORE_ADDR from
, CORE_ADDR to
,
3202 struct regcache
*regs
)
3204 aarch64_displaced_step_copy_insn_closure
*dsc
3205 = (aarch64_displaced_step_copy_insn_closure
*) dsc_
;
3209 regcache_cooked_read_unsigned (regs
, AARCH64_PC_REGNUM
, &pc
);
3211 displaced_debug_printf ("PC after stepping: %s (was %s).",
3212 paddress (gdbarch
, pc
), paddress (gdbarch
, to
));
3216 displaced_debug_printf ("[Conditional] pc_adjust before: %d",
3221 /* Condition is true. */
3223 else if (pc
- to
== 4)
3225 /* Condition is false. */
3229 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
3231 displaced_debug_printf ("[Conditional] pc_adjust after: %d",
3235 displaced_debug_printf ("%s PC by %d",
3236 dsc
->pc_adjust
? "adjusting" : "not adjusting",
3239 if (dsc
->pc_adjust
!= 0)
3241 /* Make sure the previous instruction was executed (that is, the PC
3242 has changed). If the PC didn't change, then discard the adjustment
3243 offset. Otherwise we may skip an instruction before its execution
3247 displaced_debug_printf ("PC did not move. Discarding PC adjustment.");
3251 displaced_debug_printf ("fixup: set PC to %s:%d",
3252 paddress (gdbarch
, from
), dsc
->pc_adjust
);
3254 regcache_cooked_write_unsigned (regs
, AARCH64_PC_REGNUM
,
3255 from
+ dsc
->pc_adjust
);
3259 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3262 aarch64_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
)
3267 /* Get the correct target description for the given VQ value.
3268 If VQ is zero then it is assumed SVE is not supported.
3269 (It is not possible to set VQ to zero on an SVE system).
3271 MTE_P indicates the presence of the Memory Tagging Extension feature. */
3274 aarch64_read_description (uint64_t vq
, bool pauth_p
, bool mte_p
)
3276 if (vq
> AARCH64_MAX_SVE_VQ
)
3277 error (_("VQ is %" PRIu64
", maximum supported value is %d"), vq
,
3278 AARCH64_MAX_SVE_VQ
);
3280 struct target_desc
*tdesc
= tdesc_aarch64_list
[vq
][pauth_p
][mte_p
];
3284 tdesc
= aarch64_create_target_description (vq
, pauth_p
, mte_p
);
3285 tdesc_aarch64_list
[vq
][pauth_p
][mte_p
] = tdesc
;
3291 /* Return the VQ used when creating the target description TDESC. */
3294 aarch64_get_tdesc_vq (const struct target_desc
*tdesc
)
3296 const struct tdesc_feature
*feature_sve
;
3298 if (!tdesc_has_registers (tdesc
))
3301 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3303 if (feature_sve
== nullptr)
3306 uint64_t vl
= tdesc_register_bitsize (feature_sve
,
3307 aarch64_sve_register_names
[0]) / 8;
3308 return sve_vq_from_vl (vl
);
3311 /* Add all the expected register sets into GDBARCH. */
3314 aarch64_add_reggroups (struct gdbarch
*gdbarch
)
3316 reggroup_add (gdbarch
, general_reggroup
);
3317 reggroup_add (gdbarch
, float_reggroup
);
3318 reggroup_add (gdbarch
, system_reggroup
);
3319 reggroup_add (gdbarch
, vector_reggroup
);
3320 reggroup_add (gdbarch
, all_reggroup
);
3321 reggroup_add (gdbarch
, save_reggroup
);
3322 reggroup_add (gdbarch
, restore_reggroup
);
3325 /* Implement the "cannot_store_register" gdbarch method. */
3328 aarch64_cannot_store_register (struct gdbarch
*gdbarch
, int regnum
)
3330 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3332 if (!tdep
->has_pauth ())
3335 /* Pointer authentication registers are read-only. */
3336 return (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
3337 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
));
3340 /* Initialize the current architecture based on INFO. If possible,
3341 re-use an architecture from ARCHES, which is a list of
3342 architectures already created during this debugging session.
3344 Called e.g. at program startup, when reading a core file, and when
3345 reading a binary file. */
3347 static struct gdbarch
*
3348 aarch64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3350 const struct tdesc_feature
*feature_core
, *feature_fpu
, *feature_sve
;
3351 const struct tdesc_feature
*feature_pauth
;
3352 bool valid_p
= true;
3353 int i
, num_regs
= 0, num_pseudo_regs
= 0;
3354 int first_pauth_regnum
= -1, pauth_ra_state_offset
= -1;
3355 int first_mte_regnum
= -1;
3357 /* Use the vector length passed via the target info. Here -1 is used for no
3358 SVE, and 0 is unset. If unset then use the vector length from the existing
3361 if (info
.id
== (int *) -1)
3363 else if (info
.id
!= 0)
3364 vq
= (uint64_t) info
.id
;
3366 vq
= aarch64_get_tdesc_vq (info
.target_desc
);
3368 if (vq
> AARCH64_MAX_SVE_VQ
)
3369 internal_error (__FILE__
, __LINE__
, _("VQ out of bounds: %s (max %d)"),
3370 pulongest (vq
), AARCH64_MAX_SVE_VQ
);
3372 /* If there is already a candidate, use it. */
3373 for (gdbarch_list
*best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3374 best_arch
!= nullptr;
3375 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3377 struct gdbarch_tdep
*tdep
= gdbarch_tdep (best_arch
->gdbarch
);
3378 if (tdep
&& tdep
->vq
== vq
)
3379 return best_arch
->gdbarch
;
3382 /* Ensure we always have a target descriptor, and that it is for the given VQ
3384 const struct target_desc
*tdesc
= info
.target_desc
;
3385 if (!tdesc_has_registers (tdesc
) || vq
!= aarch64_get_tdesc_vq (tdesc
))
3386 tdesc
= aarch64_read_description (vq
, false, false);
3389 feature_core
= tdesc_find_feature (tdesc
,"org.gnu.gdb.aarch64.core");
3390 feature_fpu
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.fpu");
3391 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3392 feature_pauth
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.pauth");
3393 const struct tdesc_feature
*feature_mte
3394 = tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.mte");
3396 if (feature_core
== nullptr)
3399 tdesc_arch_data_up tdesc_data
= tdesc_data_alloc ();
3401 /* Validate the description provides the mandatory core R registers
3402 and allocate their numbers. */
3403 for (i
= 0; i
< ARRAY_SIZE (aarch64_r_register_names
); i
++)
3404 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
.get (),
3405 AARCH64_X0_REGNUM
+ i
,
3406 aarch64_r_register_names
[i
]);
3408 num_regs
= AARCH64_X0_REGNUM
+ i
;
3410 /* Add the V registers. */
3411 if (feature_fpu
!= nullptr)
3413 if (feature_sve
!= nullptr)
3414 error (_("Program contains both fpu and SVE features."));
3416 /* Validate the description provides the mandatory V registers
3417 and allocate their numbers. */
3418 for (i
= 0; i
< ARRAY_SIZE (aarch64_v_register_names
); i
++)
3419 valid_p
&= tdesc_numbered_register (feature_fpu
, tdesc_data
.get (),
3420 AARCH64_V0_REGNUM
+ i
,
3421 aarch64_v_register_names
[i
]);
3423 num_regs
= AARCH64_V0_REGNUM
+ i
;
3426 /* Add the SVE registers. */
3427 if (feature_sve
!= nullptr)
3429 /* Validate the description provides the mandatory SVE registers
3430 and allocate their numbers. */
3431 for (i
= 0; i
< ARRAY_SIZE (aarch64_sve_register_names
); i
++)
3432 valid_p
&= tdesc_numbered_register (feature_sve
, tdesc_data
.get (),
3433 AARCH64_SVE_Z0_REGNUM
+ i
,
3434 aarch64_sve_register_names
[i
]);
3436 num_regs
= AARCH64_SVE_Z0_REGNUM
+ i
;
3437 num_pseudo_regs
+= 32; /* add the Vn register pseudos. */
3440 if (feature_fpu
!= nullptr || feature_sve
!= nullptr)
3442 num_pseudo_regs
+= 32; /* add the Qn scalar register pseudos */
3443 num_pseudo_regs
+= 32; /* add the Dn scalar register pseudos */
3444 num_pseudo_regs
+= 32; /* add the Sn scalar register pseudos */
3445 num_pseudo_regs
+= 32; /* add the Hn scalar register pseudos */
3446 num_pseudo_regs
+= 32; /* add the Bn scalar register pseudos */
3449 /* Add the pauth registers. */
3450 if (feature_pauth
!= NULL
)
3452 first_pauth_regnum
= num_regs
;
3453 pauth_ra_state_offset
= num_pseudo_regs
;
3454 /* Validate the descriptor provides the mandatory PAUTH registers and
3455 allocate their numbers. */
3456 for (i
= 0; i
< ARRAY_SIZE (aarch64_pauth_register_names
); i
++)
3457 valid_p
&= tdesc_numbered_register (feature_pauth
, tdesc_data
.get (),
3458 first_pauth_regnum
+ i
,
3459 aarch64_pauth_register_names
[i
]);
3462 num_pseudo_regs
+= 1; /* Count RA_STATE pseudo register. */
3465 /* Add the MTE registers. */
3466 if (feature_mte
!= NULL
)
3468 first_mte_regnum
= num_regs
;
3469 /* Validate the descriptor provides the mandatory MTE registers and
3470 allocate their numbers. */
3471 for (i
= 0; i
< ARRAY_SIZE (aarch64_mte_register_names
); i
++)
3472 valid_p
&= tdesc_numbered_register (feature_mte
, tdesc_data
.get (),
3473 first_mte_regnum
+ i
,
3474 aarch64_mte_register_names
[i
]);
3482 /* AArch64 code is always little-endian. */
3483 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
3485 struct gdbarch_tdep
*tdep
= XCNEW (struct gdbarch_tdep
);
3486 struct gdbarch
*gdbarch
= gdbarch_alloc (&info
, tdep
);
3488 /* This should be low enough for everything. */
3489 tdep
->lowest_pc
= 0x20;
3490 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3491 tdep
->jb_elt_size
= 8;
3493 tdep
->pauth_reg_base
= first_pauth_regnum
;
3494 tdep
->pauth_ra_state_regnum
= (feature_pauth
== NULL
) ? -1
3495 : pauth_ra_state_offset
+ num_regs
;
3496 tdep
->mte_reg_base
= first_mte_regnum
;
3498 set_gdbarch_push_dummy_call (gdbarch
, aarch64_push_dummy_call
);
3499 set_gdbarch_frame_align (gdbarch
, aarch64_frame_align
);
3501 /* Advance PC across function entry code. */
3502 set_gdbarch_skip_prologue (gdbarch
, aarch64_skip_prologue
);
3504 /* The stack grows downward. */
3505 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3507 /* Breakpoint manipulation. */
3508 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3509 aarch64_breakpoint::kind_from_pc
);
3510 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3511 aarch64_breakpoint::bp_from_kind
);
3512 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3513 set_gdbarch_software_single_step (gdbarch
, aarch64_software_single_step
);
3515 /* Information about registers, etc. */
3516 set_gdbarch_sp_regnum (gdbarch
, AARCH64_SP_REGNUM
);
3517 set_gdbarch_pc_regnum (gdbarch
, AARCH64_PC_REGNUM
);
3518 set_gdbarch_num_regs (gdbarch
, num_regs
);
3520 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3521 set_gdbarch_pseudo_register_read_value (gdbarch
, aarch64_pseudo_read_value
);
3522 set_gdbarch_pseudo_register_write (gdbarch
, aarch64_pseudo_write
);
3523 set_tdesc_pseudo_register_name (gdbarch
, aarch64_pseudo_register_name
);
3524 set_tdesc_pseudo_register_type (gdbarch
, aarch64_pseudo_register_type
);
3525 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3526 aarch64_pseudo_register_reggroup_p
);
3527 set_gdbarch_cannot_store_register (gdbarch
, aarch64_cannot_store_register
);
3530 set_gdbarch_short_bit (gdbarch
, 16);
3531 set_gdbarch_int_bit (gdbarch
, 32);
3532 set_gdbarch_float_bit (gdbarch
, 32);
3533 set_gdbarch_double_bit (gdbarch
, 64);
3534 set_gdbarch_long_double_bit (gdbarch
, 128);
3535 set_gdbarch_long_bit (gdbarch
, 64);
3536 set_gdbarch_long_long_bit (gdbarch
, 64);
3537 set_gdbarch_ptr_bit (gdbarch
, 64);
3538 set_gdbarch_char_signed (gdbarch
, 0);
3539 set_gdbarch_wchar_signed (gdbarch
, 0);
3540 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3541 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3542 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3543 set_gdbarch_type_align (gdbarch
, aarch64_type_align
);
3545 /* Internal <-> external register number maps. */
3546 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, aarch64_dwarf_reg_to_regnum
);
3548 /* Returning results. */
3549 set_gdbarch_return_value (gdbarch
, aarch64_return_value
);
3552 set_gdbarch_print_insn (gdbarch
, aarch64_gdb_print_insn
);
3554 /* Virtual tables. */
3555 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3557 /* Register architecture. */
3558 aarch64_add_reggroups (gdbarch
);
3560 /* Hook in the ABI-specific overrides, if they have been registered. */
3561 info
.target_desc
= tdesc
;
3562 info
.tdesc_data
= tdesc_data
.get ();
3563 gdbarch_init_osabi (info
, gdbarch
);
3565 dwarf2_frame_set_init_reg (gdbarch
, aarch64_dwarf2_frame_init_reg
);
3566 /* Register DWARF CFA vendor handler. */
3567 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch
,
3568 aarch64_execute_dwarf_cfa_vendor_op
);
3570 /* Permanent/Program breakpoint handling. */
3571 set_gdbarch_program_breakpoint_here_p (gdbarch
,
3572 aarch64_program_breakpoint_here_p
);
3574 /* Add some default predicates. */
3575 frame_unwind_append_unwinder (gdbarch
, &aarch64_stub_unwind
);
3576 dwarf2_append_unwinders (gdbarch
);
3577 frame_unwind_append_unwinder (gdbarch
, &aarch64_prologue_unwind
);
3579 frame_base_set_default (gdbarch
, &aarch64_normal_base
);
3581 /* Now we have tuned the configuration, set a few final things,
3582 based on what the OS ABI has told us. */
3584 if (tdep
->jb_pc
>= 0)
3585 set_gdbarch_get_longjmp_target (gdbarch
, aarch64_get_longjmp_target
);
3587 set_gdbarch_gen_return_address (gdbarch
, aarch64_gen_return_address
);
3589 set_gdbarch_get_pc_address_flags (gdbarch
, aarch64_get_pc_address_flags
);
3591 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
3593 /* Add standard register aliases. */
3594 for (i
= 0; i
< ARRAY_SIZE (aarch64_register_aliases
); i
++)
3595 user_reg_add (gdbarch
, aarch64_register_aliases
[i
].name
,
3596 value_of_aarch64_user_reg
,
3597 &aarch64_register_aliases
[i
].regnum
);
3599 register_aarch64_ravenscar_ops (gdbarch
);
3605 aarch64_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3607 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3612 fprintf_unfiltered (file
, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3613 paddress (gdbarch
, tdep
->lowest_pc
));
3619 static void aarch64_process_record_test (void);
3623 void _initialize_aarch64_tdep ();
3625 _initialize_aarch64_tdep ()
3627 gdbarch_register (bfd_arch_aarch64
, aarch64_gdbarch_init
,
3630 /* Debug this file's internals. */
3631 add_setshow_boolean_cmd ("aarch64", class_maintenance
, &aarch64_debug
, _("\
3632 Set AArch64 debugging."), _("\
3633 Show AArch64 debugging."), _("\
3634 When on, AArch64 specific debugging is enabled."),
3637 &setdebuglist
, &showdebuglist
);
3640 selftests::register_test ("aarch64-analyze-prologue",
3641 selftests::aarch64_analyze_prologue_test
);
3642 selftests::register_test ("aarch64-process-record",
3643 selftests::aarch64_process_record_test
);
3647 /* AArch64 process record-replay related structures, defines etc. */
3649 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3652 unsigned int reg_len = LENGTH; \
3655 REGS = XNEWVEC (uint32_t, reg_len); \
3656 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3661 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3664 unsigned int mem_len = LENGTH; \
3667 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3668 memcpy(&MEMS->len, &RECORD_BUF[0], \
3669 sizeof(struct aarch64_mem_r) * LENGTH); \
3674 /* AArch64 record/replay structures and enumerations. */
3676 struct aarch64_mem_r
3678 uint64_t len
; /* Record length. */
3679 uint64_t addr
; /* Memory address. */
3682 enum aarch64_record_result
3684 AARCH64_RECORD_SUCCESS
,
3685 AARCH64_RECORD_UNSUPPORTED
,
3686 AARCH64_RECORD_UNKNOWN
3689 typedef struct insn_decode_record_t
3691 struct gdbarch
*gdbarch
;
3692 struct regcache
*regcache
;
3693 CORE_ADDR this_addr
; /* Address of insn to be recorded. */
3694 uint32_t aarch64_insn
; /* Insn to be recorded. */
3695 uint32_t mem_rec_count
; /* Count of memory records. */
3696 uint32_t reg_rec_count
; /* Count of register records. */
3697 uint32_t *aarch64_regs
; /* Registers to be recorded. */
3698 struct aarch64_mem_r
*aarch64_mems
; /* Memory locations to be recorded. */
3699 } insn_decode_record
;
3701 /* Record handler for data processing - register instructions. */
3704 aarch64_record_data_proc_reg (insn_decode_record
*aarch64_insn_r
)
3706 uint8_t reg_rd
, insn_bits24_27
, insn_bits21_23
;
3707 uint32_t record_buf
[4];
3709 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3710 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3711 insn_bits21_23
= bits (aarch64_insn_r
->aarch64_insn
, 21, 23);
3713 if (!bit (aarch64_insn_r
->aarch64_insn
, 28))
3717 /* Logical (shifted register). */
3718 if (insn_bits24_27
== 0x0a)
3719 setflags
= (bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03);
3721 else if (insn_bits24_27
== 0x0b)
3722 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3724 return AARCH64_RECORD_UNKNOWN
;
3726 record_buf
[0] = reg_rd
;
3727 aarch64_insn_r
->reg_rec_count
= 1;
3729 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3733 if (insn_bits24_27
== 0x0b)
3735 /* Data-processing (3 source). */
3736 record_buf
[0] = reg_rd
;
3737 aarch64_insn_r
->reg_rec_count
= 1;
3739 else if (insn_bits24_27
== 0x0a)
3741 if (insn_bits21_23
== 0x00)
3743 /* Add/subtract (with carry). */
3744 record_buf
[0] = reg_rd
;
3745 aarch64_insn_r
->reg_rec_count
= 1;
3746 if (bit (aarch64_insn_r
->aarch64_insn
, 29))
3748 record_buf
[1] = AARCH64_CPSR_REGNUM
;
3749 aarch64_insn_r
->reg_rec_count
= 2;
3752 else if (insn_bits21_23
== 0x02)
3754 /* Conditional compare (register) and conditional compare
3755 (immediate) instructions. */
3756 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3757 aarch64_insn_r
->reg_rec_count
= 1;
3759 else if (insn_bits21_23
== 0x04 || insn_bits21_23
== 0x06)
3761 /* Conditional select. */
3762 /* Data-processing (2 source). */
3763 /* Data-processing (1 source). */
3764 record_buf
[0] = reg_rd
;
3765 aarch64_insn_r
->reg_rec_count
= 1;
3768 return AARCH64_RECORD_UNKNOWN
;
3772 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3774 return AARCH64_RECORD_SUCCESS
;
3777 /* Record handler for data processing - immediate instructions. */
3780 aarch64_record_data_proc_imm (insn_decode_record
*aarch64_insn_r
)
3782 uint8_t reg_rd
, insn_bit23
, insn_bits24_27
, setflags
;
3783 uint32_t record_buf
[4];
3785 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3786 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3787 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3789 if (insn_bits24_27
== 0x00 /* PC rel addressing. */
3790 || insn_bits24_27
== 0x03 /* Bitfield and Extract. */
3791 || (insn_bits24_27
== 0x02 && insn_bit23
)) /* Move wide (immediate). */
3793 record_buf
[0] = reg_rd
;
3794 aarch64_insn_r
->reg_rec_count
= 1;
3796 else if (insn_bits24_27
== 0x01)
3798 /* Add/Subtract (immediate). */
3799 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3800 record_buf
[0] = reg_rd
;
3801 aarch64_insn_r
->reg_rec_count
= 1;
3803 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3805 else if (insn_bits24_27
== 0x02 && !insn_bit23
)
3807 /* Logical (immediate). */
3808 setflags
= bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03;
3809 record_buf
[0] = reg_rd
;
3810 aarch64_insn_r
->reg_rec_count
= 1;
3812 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3815 return AARCH64_RECORD_UNKNOWN
;
3817 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3819 return AARCH64_RECORD_SUCCESS
;
3822 /* Record handler for branch, exception generation and system instructions. */
3825 aarch64_record_branch_except_sys (insn_decode_record
*aarch64_insn_r
)
3827 struct gdbarch_tdep
*tdep
= gdbarch_tdep (aarch64_insn_r
->gdbarch
);
3828 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits22_23
;
3829 uint32_t record_buf
[4];
3831 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3832 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
3833 insn_bits22_23
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3835 if (insn_bits28_31
== 0x0d)
3837 /* Exception generation instructions. */
3838 if (insn_bits24_27
== 0x04)
3840 if (!bits (aarch64_insn_r
->aarch64_insn
, 2, 4)
3841 && !bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
3842 && bits (aarch64_insn_r
->aarch64_insn
, 0, 1) == 0x01)
3844 ULONGEST svc_number
;
3846 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, 8,
3848 return tdep
->aarch64_syscall_record (aarch64_insn_r
->regcache
,
3852 return AARCH64_RECORD_UNSUPPORTED
;
3854 /* System instructions. */
3855 else if (insn_bits24_27
== 0x05 && insn_bits22_23
== 0x00)
3857 uint32_t reg_rt
, reg_crn
;
3859 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3860 reg_crn
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3862 /* Record rt in case of sysl and mrs instructions. */
3863 if (bit (aarch64_insn_r
->aarch64_insn
, 21))
3865 record_buf
[0] = reg_rt
;
3866 aarch64_insn_r
->reg_rec_count
= 1;
3868 /* Record cpsr for hint and msr(immediate) instructions. */
3869 else if (reg_crn
== 0x02 || reg_crn
== 0x04)
3871 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3872 aarch64_insn_r
->reg_rec_count
= 1;
3875 /* Unconditional branch (register). */
3876 else if((insn_bits24_27
& 0x0e) == 0x06)
3878 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3879 if (bits (aarch64_insn_r
->aarch64_insn
, 21, 22) == 0x01)
3880 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3883 return AARCH64_RECORD_UNKNOWN
;
3885 /* Unconditional branch (immediate). */
3886 else if ((insn_bits28_31
& 0x07) == 0x01 && (insn_bits24_27
& 0x0c) == 0x04)
3888 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3889 if (bit (aarch64_insn_r
->aarch64_insn
, 31))
3890 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3893 /* Compare & branch (immediate), Test & branch (immediate) and
3894 Conditional branch (immediate). */
3895 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3897 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3899 return AARCH64_RECORD_SUCCESS
;
3902 /* Record handler for advanced SIMD load and store instructions. */
3905 aarch64_record_asimd_load_store (insn_decode_record
*aarch64_insn_r
)
3908 uint64_t addr_offset
= 0;
3909 uint32_t record_buf
[24];
3910 uint64_t record_buf_mem
[24];
3911 uint32_t reg_rn
, reg_rt
;
3912 uint32_t reg_index
= 0, mem_index
= 0;
3913 uint8_t opcode_bits
, size_bits
;
3915 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3916 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3917 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3918 opcode_bits
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3919 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
, &address
);
3922 debug_printf ("Process record: Advanced SIMD load/store\n");
3924 /* Load/store single structure. */
3925 if (bit (aarch64_insn_r
->aarch64_insn
, 24))
3927 uint8_t sindex
, scale
, selem
, esize
, replicate
= 0;
3928 scale
= opcode_bits
>> 2;
3929 selem
= ((opcode_bits
& 0x02) |
3930 bit (aarch64_insn_r
->aarch64_insn
, 21)) + 1;
3934 if (size_bits
& 0x01)
3935 return AARCH64_RECORD_UNKNOWN
;
3938 if ((size_bits
>> 1) & 0x01)
3939 return AARCH64_RECORD_UNKNOWN
;
3940 if (size_bits
& 0x01)
3942 if (!((opcode_bits
>> 1) & 0x01))
3945 return AARCH64_RECORD_UNKNOWN
;
3949 if (bit (aarch64_insn_r
->aarch64_insn
, 22) && !(opcode_bits
& 0x01))
3956 return AARCH64_RECORD_UNKNOWN
;
3962 for (sindex
= 0; sindex
< selem
; sindex
++)
3964 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3965 reg_rt
= (reg_rt
+ 1) % 32;
3969 for (sindex
= 0; sindex
< selem
; sindex
++)
3971 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3972 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3975 record_buf_mem
[mem_index
++] = esize
/ 8;
3976 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3978 addr_offset
= addr_offset
+ (esize
/ 8);
3979 reg_rt
= (reg_rt
+ 1) % 32;
3983 /* Load/store multiple structure. */
3986 uint8_t selem
, esize
, rpt
, elements
;
3987 uint8_t eindex
, rindex
;
3989 esize
= 8 << size_bits
;
3990 if (bit (aarch64_insn_r
->aarch64_insn
, 30))
3991 elements
= 128 / esize
;
3993 elements
= 64 / esize
;
3995 switch (opcode_bits
)
3997 /*LD/ST4 (4 Registers). */
4002 /*LD/ST1 (4 Registers). */
4007 /*LD/ST3 (3 Registers). */
4012 /*LD/ST1 (3 Registers). */
4017 /*LD/ST1 (1 Register). */
4022 /*LD/ST2 (2 Registers). */
4027 /*LD/ST1 (2 Registers). */
4033 return AARCH64_RECORD_UNSUPPORTED
;
4036 for (rindex
= 0; rindex
< rpt
; rindex
++)
4037 for (eindex
= 0; eindex
< elements
; eindex
++)
4039 uint8_t reg_tt
, sindex
;
4040 reg_tt
= (reg_rt
+ rindex
) % 32;
4041 for (sindex
= 0; sindex
< selem
; sindex
++)
4043 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
4044 record_buf
[reg_index
++] = reg_tt
+ AARCH64_V0_REGNUM
;
4047 record_buf_mem
[mem_index
++] = esize
/ 8;
4048 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
4050 addr_offset
= addr_offset
+ (esize
/ 8);
4051 reg_tt
= (reg_tt
+ 1) % 32;
4056 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
4057 record_buf
[reg_index
++] = reg_rn
;
4059 aarch64_insn_r
->reg_rec_count
= reg_index
;
4060 aarch64_insn_r
->mem_rec_count
= mem_index
/ 2;
4061 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
4063 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4065 return AARCH64_RECORD_SUCCESS
;
4068 /* Record handler for load and store instructions. */
4071 aarch64_record_load_store (insn_decode_record
*aarch64_insn_r
)
4073 uint8_t insn_bits24_27
, insn_bits28_29
, insn_bits10_11
;
4074 uint8_t insn_bit23
, insn_bit21
;
4075 uint8_t opc
, size_bits
, ld_flag
, vector_flag
;
4076 uint32_t reg_rn
, reg_rt
, reg_rt2
;
4077 uint64_t datasize
, offset
;
4078 uint32_t record_buf
[8];
4079 uint64_t record_buf_mem
[8];
4082 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
4083 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
4084 insn_bits28_29
= bits (aarch64_insn_r
->aarch64_insn
, 28, 29);
4085 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
4086 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
4087 ld_flag
= bit (aarch64_insn_r
->aarch64_insn
, 22);
4088 vector_flag
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4089 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
4090 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
4091 reg_rt2
= bits (aarch64_insn_r
->aarch64_insn
, 10, 14);
4092 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 30, 31);
4094 /* Load/store exclusive. */
4095 if (insn_bits24_27
== 0x08 && insn_bits28_29
== 0x00)
4098 debug_printf ("Process record: load/store exclusive\n");
4102 record_buf
[0] = reg_rt
;
4103 aarch64_insn_r
->reg_rec_count
= 1;
4106 record_buf
[1] = reg_rt2
;
4107 aarch64_insn_r
->reg_rec_count
= 2;
4113 datasize
= (8 << size_bits
) * 2;
4115 datasize
= (8 << size_bits
);
4116 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4118 record_buf_mem
[0] = datasize
/ 8;
4119 record_buf_mem
[1] = address
;
4120 aarch64_insn_r
->mem_rec_count
= 1;
4123 /* Save register rs. */
4124 record_buf
[0] = bits (aarch64_insn_r
->aarch64_insn
, 16, 20);
4125 aarch64_insn_r
->reg_rec_count
= 1;
4129 /* Load register (literal) instructions decoding. */
4130 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x01)
4133 debug_printf ("Process record: load register (literal)\n");
4135 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4137 record_buf
[0] = reg_rt
;
4138 aarch64_insn_r
->reg_rec_count
= 1;
4140 /* All types of load/store pair instructions decoding. */
4141 else if ((insn_bits24_27
& 0x0a) == 0x08 && insn_bits28_29
== 0x02)
4144 debug_printf ("Process record: load/store pair\n");
4150 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4151 record_buf
[1] = reg_rt2
+ AARCH64_V0_REGNUM
;
4155 record_buf
[0] = reg_rt
;
4156 record_buf
[1] = reg_rt2
;
4158 aarch64_insn_r
->reg_rec_count
= 2;
4163 imm7_off
= bits (aarch64_insn_r
->aarch64_insn
, 15, 21);
4165 size_bits
= size_bits
>> 1;
4166 datasize
= 8 << (2 + size_bits
);
4167 offset
= (imm7_off
& 0x40) ? (~imm7_off
& 0x007f) + 1 : imm7_off
;
4168 offset
= offset
<< (2 + size_bits
);
4169 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4171 if (!((insn_bits24_27
& 0x0b) == 0x08 && insn_bit23
))
4173 if (imm7_off
& 0x40)
4174 address
= address
- offset
;
4176 address
= address
+ offset
;
4179 record_buf_mem
[0] = datasize
/ 8;
4180 record_buf_mem
[1] = address
;
4181 record_buf_mem
[2] = datasize
/ 8;
4182 record_buf_mem
[3] = address
+ (datasize
/ 8);
4183 aarch64_insn_r
->mem_rec_count
= 2;
4185 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
4186 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4188 /* Load/store register (unsigned immediate) instructions. */
4189 else if ((insn_bits24_27
& 0x0b) == 0x09 && insn_bits28_29
== 0x03)
4191 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4201 if (size_bits
== 0x3 && vector_flag
== 0x0 && opc
== 0x2)
4203 /* PRFM (immediate) */
4204 return AARCH64_RECORD_SUCCESS
;
4206 else if (size_bits
== 0x2 && vector_flag
== 0x0 && opc
== 0x2)
4208 /* LDRSW (immediate) */
4222 debug_printf ("Process record: load/store (unsigned immediate):"
4223 " size %x V %d opc %x\n", size_bits
, vector_flag
,
4229 offset
= bits (aarch64_insn_r
->aarch64_insn
, 10, 21);
4230 datasize
= 8 << size_bits
;
4231 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4233 offset
= offset
<< size_bits
;
4234 address
= address
+ offset
;
4236 record_buf_mem
[0] = datasize
>> 3;
4237 record_buf_mem
[1] = address
;
4238 aarch64_insn_r
->mem_rec_count
= 1;
4243 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4245 record_buf
[0] = reg_rt
;
4246 aarch64_insn_r
->reg_rec_count
= 1;
4249 /* Load/store register (register offset) instructions. */
4250 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4251 && insn_bits10_11
== 0x02 && insn_bit21
)
4254 debug_printf ("Process record: load/store (register offset)\n");
4255 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4262 if (size_bits
!= 0x03)
4265 return AARCH64_RECORD_UNKNOWN
;
4269 ULONGEST reg_rm_val
;
4271 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
,
4272 bits (aarch64_insn_r
->aarch64_insn
, 16, 20), ®_rm_val
);
4273 if (bit (aarch64_insn_r
->aarch64_insn
, 12))
4274 offset
= reg_rm_val
<< size_bits
;
4276 offset
= reg_rm_val
;
4277 datasize
= 8 << size_bits
;
4278 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4280 address
= address
+ offset
;
4281 record_buf_mem
[0] = datasize
>> 3;
4282 record_buf_mem
[1] = address
;
4283 aarch64_insn_r
->mem_rec_count
= 1;
4288 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4290 record_buf
[0] = reg_rt
;
4291 aarch64_insn_r
->reg_rec_count
= 1;
4294 /* Load/store register (immediate and unprivileged) instructions. */
4295 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4300 debug_printf ("Process record: load/store "
4301 "(immediate and unprivileged)\n");
4303 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4310 if (size_bits
!= 0x03)
4313 return AARCH64_RECORD_UNKNOWN
;
4318 imm9_off
= bits (aarch64_insn_r
->aarch64_insn
, 12, 20);
4319 offset
= (imm9_off
& 0x0100) ? (((~imm9_off
) & 0x01ff) + 1) : imm9_off
;
4320 datasize
= 8 << size_bits
;
4321 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4323 if (insn_bits10_11
!= 0x01)
4325 if (imm9_off
& 0x0100)
4326 address
= address
- offset
;
4328 address
= address
+ offset
;
4330 record_buf_mem
[0] = datasize
>> 3;
4331 record_buf_mem
[1] = address
;
4332 aarch64_insn_r
->mem_rec_count
= 1;
4337 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4339 record_buf
[0] = reg_rt
;
4340 aarch64_insn_r
->reg_rec_count
= 1;
4342 if (insn_bits10_11
== 0x01 || insn_bits10_11
== 0x03)
4343 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4345 /* Advanced SIMD load/store instructions. */
4347 return aarch64_record_asimd_load_store (aarch64_insn_r
);
4349 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
4351 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4353 return AARCH64_RECORD_SUCCESS
;
4356 /* Record handler for data processing SIMD and floating point instructions. */
4359 aarch64_record_data_proc_simd_fp (insn_decode_record
*aarch64_insn_r
)
4361 uint8_t insn_bit21
, opcode
, rmode
, reg_rd
;
4362 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits10_11
, insn_bits12_15
;
4363 uint8_t insn_bits11_14
;
4364 uint32_t record_buf
[2];
4366 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
4367 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
4368 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
4369 insn_bits12_15
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
4370 insn_bits11_14
= bits (aarch64_insn_r
->aarch64_insn
, 11, 14);
4371 opcode
= bits (aarch64_insn_r
->aarch64_insn
, 16, 18);
4372 rmode
= bits (aarch64_insn_r
->aarch64_insn
, 19, 20);
4373 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
4374 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
4377 debug_printf ("Process record: data processing SIMD/FP: ");
4379 if ((insn_bits28_31
& 0x05) == 0x01 && insn_bits24_27
== 0x0e)
4381 /* Floating point - fixed point conversion instructions. */
4385 debug_printf ("FP - fixed point conversion");
4387 if ((opcode
>> 1) == 0x0 && rmode
== 0x03)
4388 record_buf
[0] = reg_rd
;
4390 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4392 /* Floating point - conditional compare instructions. */
4393 else if (insn_bits10_11
== 0x01)
4396 debug_printf ("FP - conditional compare");
4398 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4400 /* Floating point - data processing (2-source) and
4401 conditional select instructions. */
4402 else if (insn_bits10_11
== 0x02 || insn_bits10_11
== 0x03)
4405 debug_printf ("FP - DP (2-source)");
4407 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4409 else if (insn_bits10_11
== 0x00)
4411 /* Floating point - immediate instructions. */
4412 if ((insn_bits12_15
& 0x01) == 0x01
4413 || (insn_bits12_15
& 0x07) == 0x04)
4416 debug_printf ("FP - immediate");
4417 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4419 /* Floating point - compare instructions. */
4420 else if ((insn_bits12_15
& 0x03) == 0x02)
4423 debug_printf ("FP - immediate");
4424 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4426 /* Floating point - integer conversions instructions. */
4427 else if (insn_bits12_15
== 0x00)
4429 /* Convert float to integer instruction. */
4430 if (!(opcode
>> 1) || ((opcode
>> 1) == 0x02 && !rmode
))
4433 debug_printf ("float to int conversion");
4435 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4437 /* Convert integer to float instruction. */
4438 else if ((opcode
>> 1) == 0x01 && !rmode
)
4441 debug_printf ("int to float conversion");
4443 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4445 /* Move float to integer instruction. */
4446 else if ((opcode
>> 1) == 0x03)
4449 debug_printf ("move float to int");
4451 if (!(opcode
& 0x01))
4452 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4454 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4457 return AARCH64_RECORD_UNKNOWN
;
4460 return AARCH64_RECORD_UNKNOWN
;
4463 return AARCH64_RECORD_UNKNOWN
;
4465 else if ((insn_bits28_31
& 0x09) == 0x00 && insn_bits24_27
== 0x0e)
4468 debug_printf ("SIMD copy");
4470 /* Advanced SIMD copy instructions. */
4471 if (!bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
4472 && !bit (aarch64_insn_r
->aarch64_insn
, 15)
4473 && bit (aarch64_insn_r
->aarch64_insn
, 10))
4475 if (insn_bits11_14
== 0x05 || insn_bits11_14
== 0x07)
4476 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4478 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4481 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4483 /* All remaining floating point or advanced SIMD instructions. */
4487 debug_printf ("all remain");
4489 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4493 debug_printf ("\n");
4495 /* Record the V/X register. */
4496 aarch64_insn_r
->reg_rec_count
++;
4498 /* Some of these instructions may set bits in the FPSR, so record it
4500 record_buf
[1] = AARCH64_FPSR_REGNUM
;
4501 aarch64_insn_r
->reg_rec_count
++;
4503 gdb_assert (aarch64_insn_r
->reg_rec_count
== 2);
4504 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4506 return AARCH64_RECORD_SUCCESS
;
4509 /* Decodes insns type and invokes its record handler. */
4512 aarch64_record_decode_insn_handler (insn_decode_record
*aarch64_insn_r
)
4514 uint32_t ins_bit25
, ins_bit26
, ins_bit27
, ins_bit28
;
4516 ins_bit25
= bit (aarch64_insn_r
->aarch64_insn
, 25);
4517 ins_bit26
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4518 ins_bit27
= bit (aarch64_insn_r
->aarch64_insn
, 27);
4519 ins_bit28
= bit (aarch64_insn_r
->aarch64_insn
, 28);
4521 /* Data processing - immediate instructions. */
4522 if (!ins_bit26
&& !ins_bit27
&& ins_bit28
)
4523 return aarch64_record_data_proc_imm (aarch64_insn_r
);
4525 /* Branch, exception generation and system instructions. */
4526 if (ins_bit26
&& !ins_bit27
&& ins_bit28
)
4527 return aarch64_record_branch_except_sys (aarch64_insn_r
);
4529 /* Load and store instructions. */
4530 if (!ins_bit25
&& ins_bit27
)
4531 return aarch64_record_load_store (aarch64_insn_r
);
4533 /* Data processing - register instructions. */
4534 if (ins_bit25
&& !ins_bit26
&& ins_bit27
)
4535 return aarch64_record_data_proc_reg (aarch64_insn_r
);
4537 /* Data processing - SIMD and floating point instructions. */
4538 if (ins_bit25
&& ins_bit26
&& ins_bit27
)
4539 return aarch64_record_data_proc_simd_fp (aarch64_insn_r
);
4541 return AARCH64_RECORD_UNSUPPORTED
;
4544 /* Cleans up local record registers and memory allocations. */
4547 deallocate_reg_mem (insn_decode_record
*record
)
4549 xfree (record
->aarch64_regs
);
4550 xfree (record
->aarch64_mems
);
4554 namespace selftests
{
4557 aarch64_process_record_test (void)
4559 struct gdbarch_info info
;
4562 gdbarch_info_init (&info
);
4563 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
4565 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
4566 SELF_CHECK (gdbarch
!= NULL
);
4568 insn_decode_record aarch64_record
;
4570 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4571 aarch64_record
.regcache
= NULL
;
4572 aarch64_record
.this_addr
= 0;
4573 aarch64_record
.gdbarch
= gdbarch
;
4575 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4576 aarch64_record
.aarch64_insn
= 0xf9800020;
4577 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4578 SELF_CHECK (ret
== AARCH64_RECORD_SUCCESS
);
4579 SELF_CHECK (aarch64_record
.reg_rec_count
== 0);
4580 SELF_CHECK (aarch64_record
.mem_rec_count
== 0);
4582 deallocate_reg_mem (&aarch64_record
);
4585 } // namespace selftests
4586 #endif /* GDB_SELF_TEST */
4588 /* Parse the current instruction and record the values of the registers and
4589 memory that will be changed in current instruction to record_arch_list
4590 return -1 if something is wrong. */
4593 aarch64_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4594 CORE_ADDR insn_addr
)
4596 uint32_t rec_no
= 0;
4597 uint8_t insn_size
= 4;
4599 gdb_byte buf
[insn_size
];
4600 insn_decode_record aarch64_record
;
4602 memset (&buf
[0], 0, insn_size
);
4603 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4604 target_read_memory (insn_addr
, &buf
[0], insn_size
);
4605 aarch64_record
.aarch64_insn
4606 = (uint32_t) extract_unsigned_integer (&buf
[0],
4608 gdbarch_byte_order (gdbarch
));
4609 aarch64_record
.regcache
= regcache
;
4610 aarch64_record
.this_addr
= insn_addr
;
4611 aarch64_record
.gdbarch
= gdbarch
;
4613 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4614 if (ret
== AARCH64_RECORD_UNSUPPORTED
)
4616 printf_unfiltered (_("Process record does not support instruction "
4617 "0x%0x at address %s.\n"),
4618 aarch64_record
.aarch64_insn
,
4619 paddress (gdbarch
, insn_addr
));
4625 /* Record registers. */
4626 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4628 /* Always record register CPSR. */
4629 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4630 AARCH64_CPSR_REGNUM
);
4631 if (aarch64_record
.aarch64_regs
)
4632 for (rec_no
= 0; rec_no
< aarch64_record
.reg_rec_count
; rec_no
++)
4633 if (record_full_arch_list_add_reg (aarch64_record
.regcache
,
4634 aarch64_record
.aarch64_regs
[rec_no
]))
4637 /* Record memories. */
4638 if (aarch64_record
.aarch64_mems
)
4639 for (rec_no
= 0; rec_no
< aarch64_record
.mem_rec_count
; rec_no
++)
4640 if (record_full_arch_list_add_mem
4641 ((CORE_ADDR
)aarch64_record
.aarch64_mems
[rec_no
].addr
,
4642 aarch64_record
.aarch64_mems
[rec_no
].len
))
4645 if (record_full_arch_list_add_end ())
4649 deallocate_reg_mem (&aarch64_record
);