1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "reggroups.h"
31 #include "arch-utils.h"
33 #include "frame-unwind.h"
34 #include "frame-base.h"
35 #include "trad-frame.h"
37 #include "dwarf2-frame.h"
39 #include "prologue-value.h"
40 #include "target-descriptions.h"
41 #include "user-regs.h"
46 #include "common/selftest.h"
48 #include "aarch64-tdep.h"
49 #include "aarch64-ravenscar-thread.h"
52 #include "elf/aarch64.h"
54 #include "common/vec.h"
57 #include "record-full.h"
58 #include "arch/aarch64-insn.h"
60 #include "opcode/aarch64.h"
63 #define submask(x) ((1L << ((x) + 1)) - 1)
64 #define bit(obj,st) (((obj) >> (st)) & 1)
65 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
67 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
69 #define HA_MAX_NUM_FLDS 4
71 /* All possible aarch64 target descriptors. */
72 struct target_desc
*tdesc_aarch64_list
[AARCH64_MAX_SVE_VQ
+ 1];
74 /* The standard register names, and all the valid aliases for them. */
77 const char *const name
;
79 } aarch64_register_aliases
[] =
81 /* 64-bit register names. */
82 {"fp", AARCH64_FP_REGNUM
},
83 {"lr", AARCH64_LR_REGNUM
},
84 {"sp", AARCH64_SP_REGNUM
},
86 /* 32-bit register names. */
87 {"w0", AARCH64_X0_REGNUM
+ 0},
88 {"w1", AARCH64_X0_REGNUM
+ 1},
89 {"w2", AARCH64_X0_REGNUM
+ 2},
90 {"w3", AARCH64_X0_REGNUM
+ 3},
91 {"w4", AARCH64_X0_REGNUM
+ 4},
92 {"w5", AARCH64_X0_REGNUM
+ 5},
93 {"w6", AARCH64_X0_REGNUM
+ 6},
94 {"w7", AARCH64_X0_REGNUM
+ 7},
95 {"w8", AARCH64_X0_REGNUM
+ 8},
96 {"w9", AARCH64_X0_REGNUM
+ 9},
97 {"w10", AARCH64_X0_REGNUM
+ 10},
98 {"w11", AARCH64_X0_REGNUM
+ 11},
99 {"w12", AARCH64_X0_REGNUM
+ 12},
100 {"w13", AARCH64_X0_REGNUM
+ 13},
101 {"w14", AARCH64_X0_REGNUM
+ 14},
102 {"w15", AARCH64_X0_REGNUM
+ 15},
103 {"w16", AARCH64_X0_REGNUM
+ 16},
104 {"w17", AARCH64_X0_REGNUM
+ 17},
105 {"w18", AARCH64_X0_REGNUM
+ 18},
106 {"w19", AARCH64_X0_REGNUM
+ 19},
107 {"w20", AARCH64_X0_REGNUM
+ 20},
108 {"w21", AARCH64_X0_REGNUM
+ 21},
109 {"w22", AARCH64_X0_REGNUM
+ 22},
110 {"w23", AARCH64_X0_REGNUM
+ 23},
111 {"w24", AARCH64_X0_REGNUM
+ 24},
112 {"w25", AARCH64_X0_REGNUM
+ 25},
113 {"w26", AARCH64_X0_REGNUM
+ 26},
114 {"w27", AARCH64_X0_REGNUM
+ 27},
115 {"w28", AARCH64_X0_REGNUM
+ 28},
116 {"w29", AARCH64_X0_REGNUM
+ 29},
117 {"w30", AARCH64_X0_REGNUM
+ 30},
120 {"ip0", AARCH64_X0_REGNUM
+ 16},
121 {"ip1", AARCH64_X0_REGNUM
+ 17}
124 /* The required core 'R' registers. */
125 static const char *const aarch64_r_register_names
[] =
127 /* These registers must appear in consecutive RAW register number
128 order and they must begin with AARCH64_X0_REGNUM! */
129 "x0", "x1", "x2", "x3",
130 "x4", "x5", "x6", "x7",
131 "x8", "x9", "x10", "x11",
132 "x12", "x13", "x14", "x15",
133 "x16", "x17", "x18", "x19",
134 "x20", "x21", "x22", "x23",
135 "x24", "x25", "x26", "x27",
136 "x28", "x29", "x30", "sp",
140 /* The FP/SIMD 'V' registers. */
141 static const char *const aarch64_v_register_names
[] =
143 /* These registers must appear in consecutive RAW register number
144 order and they must begin with AARCH64_V0_REGNUM! */
145 "v0", "v1", "v2", "v3",
146 "v4", "v5", "v6", "v7",
147 "v8", "v9", "v10", "v11",
148 "v12", "v13", "v14", "v15",
149 "v16", "v17", "v18", "v19",
150 "v20", "v21", "v22", "v23",
151 "v24", "v25", "v26", "v27",
152 "v28", "v29", "v30", "v31",
157 /* The SVE 'Z' and 'P' registers. */
158 static const char *const aarch64_sve_register_names
[] =
160 /* These registers must appear in consecutive RAW register number
161 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
162 "z0", "z1", "z2", "z3",
163 "z4", "z5", "z6", "z7",
164 "z8", "z9", "z10", "z11",
165 "z12", "z13", "z14", "z15",
166 "z16", "z17", "z18", "z19",
167 "z20", "z21", "z22", "z23",
168 "z24", "z25", "z26", "z27",
169 "z28", "z29", "z30", "z31",
171 "p0", "p1", "p2", "p3",
172 "p4", "p5", "p6", "p7",
173 "p8", "p9", "p10", "p11",
174 "p12", "p13", "p14", "p15",
178 /* AArch64 prologue cache structure. */
179 struct aarch64_prologue_cache
181 /* The program counter at the start of the function. It is used to
182 identify this frame as a prologue frame. */
185 /* The program counter at the time this frame was created; i.e. where
186 this function was called from. It is used to identify this frame as a
190 /* The stack pointer at the time this frame was created; i.e. the
191 caller's stack pointer when this function was called. It is used
192 to identify this frame. */
195 /* Is the target available to read from? */
198 /* The frame base for this frame is just prev_sp - frame size.
199 FRAMESIZE is the distance from the frame pointer to the
200 initial stack pointer. */
203 /* The register used to hold the frame pointer for this frame. */
206 /* Saved register offsets. */
207 struct trad_frame_saved_reg
*saved_regs
;
211 show_aarch64_debug (struct ui_file
*file
, int from_tty
,
212 struct cmd_list_element
*c
, const char *value
)
214 fprintf_filtered (file
, _("AArch64 debugging is %s.\n"), value
);
219 /* Abstract instruction reader. */
221 class abstract_instruction_reader
224 /* Read in one instruction. */
225 virtual ULONGEST
read (CORE_ADDR memaddr
, int len
,
226 enum bfd_endian byte_order
) = 0;
229 /* Instruction reader from real target. */
231 class instruction_reader
: public abstract_instruction_reader
234 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
237 return read_code_unsigned_integer (memaddr
, len
, byte_order
);
243 /* Analyze a prologue, looking for a recognizable stack frame
244 and frame pointer. Scan until we encounter a store that could
245 clobber the stack frame unexpectedly, or an unknown instruction. */
248 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
249 CORE_ADDR start
, CORE_ADDR limit
,
250 struct aarch64_prologue_cache
*cache
,
251 abstract_instruction_reader
& reader
)
253 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
255 /* Track X registers and D registers in prologue. */
256 pv_t regs
[AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
];
258 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
; i
++)
259 regs
[i
] = pv_register (i
, 0);
260 pv_area
stack (AARCH64_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
262 for (; start
< limit
; start
+= 4)
267 insn
= reader
.read (start
, 4, byte_order_for_code
);
269 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
272 if (inst
.opcode
->iclass
== addsub_imm
273 && (inst
.opcode
->op
== OP_ADD
274 || strcmp ("sub", inst
.opcode
->name
) == 0))
276 unsigned rd
= inst
.operands
[0].reg
.regno
;
277 unsigned rn
= inst
.operands
[1].reg
.regno
;
279 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 3);
280 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd_SP
);
281 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn_SP
);
282 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_AIMM
);
284 if (inst
.opcode
->op
== OP_ADD
)
286 regs
[rd
] = pv_add_constant (regs
[rn
],
287 inst
.operands
[2].imm
.value
);
291 regs
[rd
] = pv_add_constant (regs
[rn
],
292 -inst
.operands
[2].imm
.value
);
295 else if (inst
.opcode
->iclass
== pcreladdr
296 && inst
.operands
[1].type
== AARCH64_OPND_ADDR_ADRP
)
298 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
299 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
301 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
303 else if (inst
.opcode
->iclass
== branch_imm
)
305 /* Stop analysis on branch. */
308 else if (inst
.opcode
->iclass
== condbranch
)
310 /* Stop analysis on branch. */
313 else if (inst
.opcode
->iclass
== branch_reg
)
315 /* Stop analysis on branch. */
318 else if (inst
.opcode
->iclass
== compbranch
)
320 /* Stop analysis on branch. */
323 else if (inst
.opcode
->op
== OP_MOVZ
)
325 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
326 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
328 else if (inst
.opcode
->iclass
== log_shift
329 && strcmp (inst
.opcode
->name
, "orr") == 0)
331 unsigned rd
= inst
.operands
[0].reg
.regno
;
332 unsigned rn
= inst
.operands
[1].reg
.regno
;
333 unsigned rm
= inst
.operands
[2].reg
.regno
;
335 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
336 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn
);
337 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_Rm_SFT
);
339 if (inst
.operands
[2].shifter
.amount
== 0
340 && rn
== AARCH64_SP_REGNUM
)
346 debug_printf ("aarch64: prologue analysis gave up "
347 "addr=%s opcode=0x%x (orr x register)\n",
348 core_addr_to_string_nz (start
), insn
);
353 else if (inst
.opcode
->op
== OP_STUR
)
355 unsigned rt
= inst
.operands
[0].reg
.regno
;
356 unsigned rn
= inst
.operands
[1].addr
.base_regno
;
358 = (aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
) == 8);
360 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
361 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
);
362 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_ADDR_SIMM9
);
363 gdb_assert (!inst
.operands
[1].addr
.offset
.is_reg
);
365 stack
.store (pv_add_constant (regs
[rn
],
366 inst
.operands
[1].addr
.offset
.imm
),
367 is64
? 8 : 4, regs
[rt
]);
369 else if ((inst
.opcode
->iclass
== ldstpair_off
370 || (inst
.opcode
->iclass
== ldstpair_indexed
371 && inst
.operands
[2].addr
.preind
))
372 && strcmp ("stp", inst
.opcode
->name
) == 0)
374 /* STP with addressing mode Pre-indexed and Base register. */
377 unsigned rn
= inst
.operands
[2].addr
.base_regno
;
378 int32_t imm
= inst
.operands
[2].addr
.offset
.imm
;
380 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
381 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
382 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rt2
383 || inst
.operands
[1].type
== AARCH64_OPND_Ft2
);
384 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_ADDR_SIMM7
);
385 gdb_assert (!inst
.operands
[2].addr
.offset
.is_reg
);
387 /* If recording this store would invalidate the store area
388 (perhaps because rn is not known) then we should abandon
389 further prologue analysis. */
390 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
)))
393 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
+ 8)))
396 rt1
= inst
.operands
[0].reg
.regno
;
397 rt2
= inst
.operands
[1].reg
.regno
;
398 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
400 /* Only bottom 64-bit of each V register (D register) need
402 gdb_assert (inst
.operands
[0].qualifier
== AARCH64_OPND_QLF_S_D
);
403 rt1
+= AARCH64_X_REGISTER_COUNT
;
404 rt2
+= AARCH64_X_REGISTER_COUNT
;
407 stack
.store (pv_add_constant (regs
[rn
], imm
), 8,
409 stack
.store (pv_add_constant (regs
[rn
], imm
+ 8), 8,
412 if (inst
.operands
[2].addr
.writeback
)
413 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
416 else if ((inst
.opcode
->iclass
== ldst_imm9
/* Signed immediate. */
417 || (inst
.opcode
->iclass
== ldst_pos
/* Unsigned immediate. */
418 && (inst
.opcode
->op
== OP_STR_POS
419 || inst
.opcode
->op
== OP_STRF_POS
)))
420 && inst
.operands
[1].addr
.base_regno
== AARCH64_SP_REGNUM
421 && strcmp ("str", inst
.opcode
->name
) == 0)
423 /* STR (immediate) */
424 unsigned int rt
= inst
.operands
[0].reg
.regno
;
425 int32_t imm
= inst
.operands
[1].addr
.offset
.imm
;
426 unsigned int rn
= inst
.operands
[1].addr
.base_regno
;
428 = (aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
) == 8);
429 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
430 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
432 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
434 /* Only bottom 64-bit of each V register (D register) need
436 gdb_assert (inst
.operands
[0].qualifier
== AARCH64_OPND_QLF_S_D
);
437 rt
+= AARCH64_X_REGISTER_COUNT
;
440 stack
.store (pv_add_constant (regs
[rn
], imm
),
441 is64
? 8 : 4, regs
[rt
]);
442 if (inst
.operands
[1].addr
.writeback
)
443 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
445 else if (inst
.opcode
->iclass
== testbranch
)
447 /* Stop analysis on branch. */
454 debug_printf ("aarch64: prologue analysis gave up addr=%s"
456 core_addr_to_string_nz (start
), insn
);
465 if (pv_is_register (regs
[AARCH64_FP_REGNUM
], AARCH64_SP_REGNUM
))
467 /* Frame pointer is fp. Frame size is constant. */
468 cache
->framereg
= AARCH64_FP_REGNUM
;
469 cache
->framesize
= -regs
[AARCH64_FP_REGNUM
].k
;
471 else if (pv_is_register (regs
[AARCH64_SP_REGNUM
], AARCH64_SP_REGNUM
))
473 /* Try the stack pointer. */
474 cache
->framesize
= -regs
[AARCH64_SP_REGNUM
].k
;
475 cache
->framereg
= AARCH64_SP_REGNUM
;
479 /* We're just out of luck. We don't know where the frame is. */
480 cache
->framereg
= -1;
481 cache
->framesize
= 0;
484 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
488 if (stack
.find_reg (gdbarch
, i
, &offset
))
489 cache
->saved_regs
[i
].addr
= offset
;
492 for (i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
494 int regnum
= gdbarch_num_regs (gdbarch
);
497 if (stack
.find_reg (gdbarch
, i
+ AARCH64_X_REGISTER_COUNT
,
499 cache
->saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
= offset
;
506 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
507 CORE_ADDR start
, CORE_ADDR limit
,
508 struct aarch64_prologue_cache
*cache
)
510 instruction_reader reader
;
512 return aarch64_analyze_prologue (gdbarch
, start
, limit
, cache
,
518 namespace selftests
{
520 /* Instruction reader from manually cooked instruction sequences. */
522 class instruction_reader_test
: public abstract_instruction_reader
525 template<size_t SIZE
>
526 explicit instruction_reader_test (const uint32_t (&insns
)[SIZE
])
527 : m_insns (insns
), m_insns_size (SIZE
)
530 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
533 SELF_CHECK (len
== 4);
534 SELF_CHECK (memaddr
% 4 == 0);
535 SELF_CHECK (memaddr
/ 4 < m_insns_size
);
537 return m_insns
[memaddr
/ 4];
541 const uint32_t *m_insns
;
546 aarch64_analyze_prologue_test (void)
548 struct gdbarch_info info
;
550 gdbarch_info_init (&info
);
551 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
553 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
554 SELF_CHECK (gdbarch
!= NULL
);
556 /* Test the simple prologue in which frame pointer is used. */
558 struct aarch64_prologue_cache cache
;
559 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
561 static const uint32_t insns
[] = {
562 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
563 0x910003fd, /* mov x29, sp */
564 0x97ffffe6, /* bl 0x400580 */
566 instruction_reader_test
reader (insns
);
568 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
569 SELF_CHECK (end
== 4 * 2);
571 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
572 SELF_CHECK (cache
.framesize
== 272);
574 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
576 if (i
== AARCH64_FP_REGNUM
)
577 SELF_CHECK (cache
.saved_regs
[i
].addr
== -272);
578 else if (i
== AARCH64_LR_REGNUM
)
579 SELF_CHECK (cache
.saved_regs
[i
].addr
== -264);
581 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
584 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
586 int regnum
= gdbarch_num_regs (gdbarch
);
588 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
593 /* Test a prologue in which STR is used and frame pointer is not
596 struct aarch64_prologue_cache cache
;
597 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
599 static const uint32_t insns
[] = {
600 0xf81d0ff3, /* str x19, [sp, #-48]! */
601 0xb9002fe0, /* str w0, [sp, #44] */
602 0xf90013e1, /* str x1, [sp, #32]*/
603 0xfd000fe0, /* str d0, [sp, #24] */
604 0xaa0203f3, /* mov x19, x2 */
605 0xf94013e0, /* ldr x0, [sp, #32] */
607 instruction_reader_test
reader (insns
);
609 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
611 SELF_CHECK (end
== 4 * 5);
613 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
614 SELF_CHECK (cache
.framesize
== 48);
616 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
619 SELF_CHECK (cache
.saved_regs
[i
].addr
== -16);
621 SELF_CHECK (cache
.saved_regs
[i
].addr
== -48);
623 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
626 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
628 int regnum
= gdbarch_num_regs (gdbarch
);
631 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
634 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
639 } // namespace selftests
640 #endif /* GDB_SELF_TEST */
642 /* Implement the "skip_prologue" gdbarch method. */
645 aarch64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
647 CORE_ADDR func_addr
, limit_pc
;
649 /* See if we can determine the end of the prologue via the symbol
650 table. If so, then return either PC, or the PC after the
651 prologue, whichever is greater. */
652 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
654 CORE_ADDR post_prologue_pc
655 = skip_prologue_using_sal (gdbarch
, func_addr
);
657 if (post_prologue_pc
!= 0)
658 return std::max (pc
, post_prologue_pc
);
661 /* Can't determine prologue from the symbol table, need to examine
664 /* Find an upper limit on the function prologue using the debug
665 information. If the debug information could not be used to
666 provide that bound, then use an arbitrary large number as the
668 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
670 limit_pc
= pc
+ 128; /* Magic. */
672 /* Try disassembling prologue. */
673 return aarch64_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
676 /* Scan the function prologue for THIS_FRAME and populate the prologue
680 aarch64_scan_prologue (struct frame_info
*this_frame
,
681 struct aarch64_prologue_cache
*cache
)
683 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
684 CORE_ADDR prologue_start
;
685 CORE_ADDR prologue_end
;
686 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
687 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
689 cache
->prev_pc
= prev_pc
;
691 /* Assume we do not find a frame. */
692 cache
->framereg
= -1;
693 cache
->framesize
= 0;
695 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
698 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
702 /* No line info so use the current PC. */
703 prologue_end
= prev_pc
;
705 else if (sal
.end
< prologue_end
)
707 /* The next line begins after the function end. */
708 prologue_end
= sal
.end
;
711 prologue_end
= std::min (prologue_end
, prev_pc
);
712 aarch64_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
718 frame_loc
= get_frame_register_unsigned (this_frame
, AARCH64_FP_REGNUM
);
722 cache
->framereg
= AARCH64_FP_REGNUM
;
723 cache
->framesize
= 16;
724 cache
->saved_regs
[29].addr
= 0;
725 cache
->saved_regs
[30].addr
= 8;
729 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
730 function may throw an exception if the inferior's registers or memory is
734 aarch64_make_prologue_cache_1 (struct frame_info
*this_frame
,
735 struct aarch64_prologue_cache
*cache
)
737 CORE_ADDR unwound_fp
;
740 aarch64_scan_prologue (this_frame
, cache
);
742 if (cache
->framereg
== -1)
745 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
749 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
751 /* Calculate actual addresses of saved registers using offsets
752 determined by aarch64_analyze_prologue. */
753 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
754 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
755 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
757 cache
->func
= get_frame_func (this_frame
);
759 cache
->available_p
= 1;
762 /* Allocate and fill in *THIS_CACHE with information about the prologue of
763 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
764 Return a pointer to the current aarch64_prologue_cache in
767 static struct aarch64_prologue_cache
*
768 aarch64_make_prologue_cache (struct frame_info
*this_frame
, void **this_cache
)
770 struct aarch64_prologue_cache
*cache
;
772 if (*this_cache
!= NULL
)
773 return (struct aarch64_prologue_cache
*) *this_cache
;
775 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
776 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
781 aarch64_make_prologue_cache_1 (this_frame
, cache
);
783 CATCH (ex
, RETURN_MASK_ERROR
)
785 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
786 throw_exception (ex
);
793 /* Implement the "stop_reason" frame_unwind method. */
795 static enum unwind_stop_reason
796 aarch64_prologue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
799 struct aarch64_prologue_cache
*cache
800 = aarch64_make_prologue_cache (this_frame
, this_cache
);
802 if (!cache
->available_p
)
803 return UNWIND_UNAVAILABLE
;
805 /* Halt the backtrace at "_start". */
806 if (cache
->prev_pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
807 return UNWIND_OUTERMOST
;
809 /* We've hit a wall, stop. */
810 if (cache
->prev_sp
== 0)
811 return UNWIND_OUTERMOST
;
813 return UNWIND_NO_REASON
;
816 /* Our frame ID for a normal frame is the current function's starting
817 PC and the caller's SP when we were called. */
820 aarch64_prologue_this_id (struct frame_info
*this_frame
,
821 void **this_cache
, struct frame_id
*this_id
)
823 struct aarch64_prologue_cache
*cache
824 = aarch64_make_prologue_cache (this_frame
, this_cache
);
826 if (!cache
->available_p
)
827 *this_id
= frame_id_build_unavailable_stack (cache
->func
);
829 *this_id
= frame_id_build (cache
->prev_sp
, cache
->func
);
832 /* Implement the "prev_register" frame_unwind method. */
834 static struct value
*
835 aarch64_prologue_prev_register (struct frame_info
*this_frame
,
836 void **this_cache
, int prev_regnum
)
838 struct aarch64_prologue_cache
*cache
839 = aarch64_make_prologue_cache (this_frame
, this_cache
);
841 /* If we are asked to unwind the PC, then we need to return the LR
842 instead. The prologue may save PC, but it will point into this
843 frame's prologue, not the next frame's resume location. */
844 if (prev_regnum
== AARCH64_PC_REGNUM
)
848 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
849 return frame_unwind_got_constant (this_frame
, prev_regnum
, lr
);
852 /* SP is generally not saved to the stack, but this frame is
853 identified by the next frame's stack pointer at the time of the
854 call. The value was already reconstructed into PREV_SP. */
867 if (prev_regnum
== AARCH64_SP_REGNUM
)
868 return frame_unwind_got_constant (this_frame
, prev_regnum
,
871 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
875 /* AArch64 prologue unwinder. */
876 struct frame_unwind aarch64_prologue_unwind
=
879 aarch64_prologue_frame_unwind_stop_reason
,
880 aarch64_prologue_this_id
,
881 aarch64_prologue_prev_register
,
883 default_frame_sniffer
886 /* Allocate and fill in *THIS_CACHE with information about the prologue of
887 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
888 Return a pointer to the current aarch64_prologue_cache in
891 static struct aarch64_prologue_cache
*
892 aarch64_make_stub_cache (struct frame_info
*this_frame
, void **this_cache
)
894 struct aarch64_prologue_cache
*cache
;
896 if (*this_cache
!= NULL
)
897 return (struct aarch64_prologue_cache
*) *this_cache
;
899 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
900 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
905 cache
->prev_sp
= get_frame_register_unsigned (this_frame
,
907 cache
->prev_pc
= get_frame_pc (this_frame
);
908 cache
->available_p
= 1;
910 CATCH (ex
, RETURN_MASK_ERROR
)
912 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
913 throw_exception (ex
);
920 /* Implement the "stop_reason" frame_unwind method. */
922 static enum unwind_stop_reason
923 aarch64_stub_frame_unwind_stop_reason (struct frame_info
*this_frame
,
926 struct aarch64_prologue_cache
*cache
927 = aarch64_make_stub_cache (this_frame
, this_cache
);
929 if (!cache
->available_p
)
930 return UNWIND_UNAVAILABLE
;
932 return UNWIND_NO_REASON
;
935 /* Our frame ID for a stub frame is the current SP and LR. */
938 aarch64_stub_this_id (struct frame_info
*this_frame
,
939 void **this_cache
, struct frame_id
*this_id
)
941 struct aarch64_prologue_cache
*cache
942 = aarch64_make_stub_cache (this_frame
, this_cache
);
944 if (cache
->available_p
)
945 *this_id
= frame_id_build (cache
->prev_sp
, cache
->prev_pc
);
947 *this_id
= frame_id_build_unavailable_stack (cache
->prev_pc
);
950 /* Implement the "sniffer" frame_unwind method. */
953 aarch64_stub_unwind_sniffer (const struct frame_unwind
*self
,
954 struct frame_info
*this_frame
,
955 void **this_prologue_cache
)
957 CORE_ADDR addr_in_block
;
960 addr_in_block
= get_frame_address_in_block (this_frame
);
961 if (in_plt_section (addr_in_block
)
962 /* We also use the stub winder if the target memory is unreadable
963 to avoid having the prologue unwinder trying to read it. */
964 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
970 /* AArch64 stub unwinder. */
971 struct frame_unwind aarch64_stub_unwind
=
974 aarch64_stub_frame_unwind_stop_reason
,
975 aarch64_stub_this_id
,
976 aarch64_prologue_prev_register
,
978 aarch64_stub_unwind_sniffer
981 /* Return the frame base address of *THIS_FRAME. */
984 aarch64_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
986 struct aarch64_prologue_cache
*cache
987 = aarch64_make_prologue_cache (this_frame
, this_cache
);
989 return cache
->prev_sp
- cache
->framesize
;
992 /* AArch64 default frame base information. */
993 struct frame_base aarch64_normal_base
=
995 &aarch64_prologue_unwind
,
996 aarch64_normal_frame_base
,
997 aarch64_normal_frame_base
,
998 aarch64_normal_frame_base
1001 /* Return the value of the REGNUM register in the previous frame of
1004 static struct value
*
1005 aarch64_dwarf2_prev_register (struct frame_info
*this_frame
,
1006 void **this_cache
, int regnum
)
1012 case AARCH64_PC_REGNUM
:
1013 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1014 return frame_unwind_got_constant (this_frame
, regnum
, lr
);
1017 internal_error (__FILE__
, __LINE__
,
1018 _("Unexpected register %d"), regnum
);
1022 /* Implement the "init_reg" dwarf2_frame_ops method. */
1025 aarch64_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1026 struct dwarf2_frame_state_reg
*reg
,
1027 struct frame_info
*this_frame
)
1031 case AARCH64_PC_REGNUM
:
1032 reg
->how
= DWARF2_FRAME_REG_FN
;
1033 reg
->loc
.fn
= aarch64_dwarf2_prev_register
;
1035 case AARCH64_SP_REGNUM
:
1036 reg
->how
= DWARF2_FRAME_REG_CFA
;
1041 /* When arguments must be pushed onto the stack, they go on in reverse
1042 order. The code below implements a FILO (stack) to do this. */
1046 /* Value to pass on stack. It can be NULL if this item is for stack
1048 const gdb_byte
*data
;
1050 /* Size in bytes of value to pass on stack. */
1054 DEF_VEC_O (stack_item_t
);
1056 /* Return the alignment (in bytes) of the given type. */
1059 aarch64_type_align (struct type
*t
)
1065 t
= check_typedef (t
);
1066 switch (TYPE_CODE (t
))
1069 /* Should never happen. */
1070 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1074 case TYPE_CODE_ENUM
:
1078 case TYPE_CODE_RANGE
:
1079 case TYPE_CODE_BITSTRING
:
1081 case TYPE_CODE_RVALUE_REF
:
1082 case TYPE_CODE_CHAR
:
1083 case TYPE_CODE_BOOL
:
1084 return TYPE_LENGTH (t
);
1086 case TYPE_CODE_ARRAY
:
1087 if (TYPE_VECTOR (t
))
1089 /* Use the natural alignment for vector types (the same for
1090 scalar type), but the maximum alignment is 128-bit. */
1091 if (TYPE_LENGTH (t
) > 16)
1094 return TYPE_LENGTH (t
);
1097 return aarch64_type_align (TYPE_TARGET_TYPE (t
));
1098 case TYPE_CODE_COMPLEX
:
1099 return aarch64_type_align (TYPE_TARGET_TYPE (t
));
1101 case TYPE_CODE_STRUCT
:
1102 case TYPE_CODE_UNION
:
1104 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1106 falign
= aarch64_type_align (TYPE_FIELD_TYPE (t
, n
));
1114 /* Worker function for aapcs_is_vfp_call_or_return_candidate.
1116 Return the number of register required, or -1 on failure.
1118 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1119 to the element, else fail if the type of this element does not match the
1123 aapcs_is_vfp_call_or_return_candidate_1 (struct type
*type
,
1124 struct type
**fundamental_type
)
1126 if (type
== nullptr)
1129 switch (TYPE_CODE (type
))
1132 if (TYPE_LENGTH (type
) > 16)
1135 if (*fundamental_type
== nullptr)
1136 *fundamental_type
= type
;
1137 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1138 || TYPE_CODE (type
) != TYPE_CODE (*fundamental_type
))
1143 case TYPE_CODE_COMPLEX
:
1145 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
1146 if (TYPE_LENGTH (target_type
) > 16)
1149 if (*fundamental_type
== nullptr)
1150 *fundamental_type
= target_type
;
1151 else if (TYPE_LENGTH (target_type
) != TYPE_LENGTH (*fundamental_type
)
1152 || TYPE_CODE (target_type
) != TYPE_CODE (*fundamental_type
))
1158 case TYPE_CODE_ARRAY
:
1160 if (TYPE_VECTOR (type
))
1162 if (TYPE_LENGTH (type
) != 8 && TYPE_LENGTH (type
) != 16)
1165 if (*fundamental_type
== nullptr)
1166 *fundamental_type
= type
;
1167 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1168 || TYPE_CODE (type
) != TYPE_CODE (*fundamental_type
))
1175 struct type
*target_type
= TYPE_TARGET_TYPE (type
);
1176 int count
= aapcs_is_vfp_call_or_return_candidate_1
1177 (target_type
, fundamental_type
);
1182 count
*= (TYPE_LENGTH (type
) / TYPE_LENGTH (target_type
));
1187 case TYPE_CODE_STRUCT
:
1188 case TYPE_CODE_UNION
:
1192 for (int i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1194 /* Ignore any static fields. */
1195 if (field_is_static (&TYPE_FIELD (type
, i
)))
1198 struct type
*member
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
1200 int sub_count
= aapcs_is_vfp_call_or_return_candidate_1
1201 (member
, fundamental_type
);
1202 if (sub_count
== -1)
1207 /* Ensure there is no padding between the fields (allowing for empty
1208 zero length structs) */
1209 int ftype_length
= (*fundamental_type
== nullptr)
1210 ? 0 : TYPE_LENGTH (*fundamental_type
);
1211 if (count
* ftype_length
!= TYPE_LENGTH (type
))
1224 /* Return true if an argument, whose type is described by TYPE, can be passed or
1225 returned in simd/fp registers, providing enough parameter passing registers
1226 are available. This is as described in the AAPCS64.
1228 Upon successful return, *COUNT returns the number of needed registers,
1229 *FUNDAMENTAL_TYPE contains the type of those registers.
1231 Candidate as per the AAPCS64 5.4.2.C is either a:
1234 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1235 all the members are floats and has at most 4 members.
1236 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1237 all the members are short vectors and has at most 4 members.
1240 Note that HFAs and HVAs can include nested structures and arrays. */
1243 aapcs_is_vfp_call_or_return_candidate (struct type
*type
, int *count
,
1244 struct type
**fundamental_type
)
1246 if (type
== nullptr)
1249 *fundamental_type
= nullptr;
1251 int ag_count
= aapcs_is_vfp_call_or_return_candidate_1 (type
,
1254 if (ag_count
> 0 && ag_count
<= HA_MAX_NUM_FLDS
)
1263 /* AArch64 function call information structure. */
1264 struct aarch64_call_info
1266 /* the current argument number. */
1269 /* The next general purpose register number, equivalent to NGRN as
1270 described in the AArch64 Procedure Call Standard. */
1273 /* The next SIMD and floating point register number, equivalent to
1274 NSRN as described in the AArch64 Procedure Call Standard. */
1277 /* The next stacked argument address, equivalent to NSAA as
1278 described in the AArch64 Procedure Call Standard. */
1281 /* Stack item vector. */
1282 VEC(stack_item_t
) *si
;
1285 /* Pass a value in a sequence of consecutive X registers. The caller
1286 is responsbile for ensuring sufficient registers are available. */
1289 pass_in_x (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1290 struct aarch64_call_info
*info
, struct type
*type
,
1293 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1294 int len
= TYPE_LENGTH (type
);
1295 enum type_code typecode
= TYPE_CODE (type
);
1296 int regnum
= AARCH64_X0_REGNUM
+ info
->ngrn
;
1297 const bfd_byte
*buf
= value_contents (arg
);
1303 int partial_len
= len
< X_REGISTER_SIZE
? len
: X_REGISTER_SIZE
;
1304 CORE_ADDR regval
= extract_unsigned_integer (buf
, partial_len
,
1308 /* Adjust sub-word struct/union args when big-endian. */
1309 if (byte_order
== BFD_ENDIAN_BIG
1310 && partial_len
< X_REGISTER_SIZE
1311 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1312 regval
<<= ((X_REGISTER_SIZE
- partial_len
) * TARGET_CHAR_BIT
);
1316 debug_printf ("arg %d in %s = 0x%s\n", info
->argnum
,
1317 gdbarch_register_name (gdbarch
, regnum
),
1318 phex (regval
, X_REGISTER_SIZE
));
1320 regcache_cooked_write_unsigned (regcache
, regnum
, regval
);
1327 /* Attempt to marshall a value in a V register. Return 1 if
1328 successful, or 0 if insufficient registers are available. This
1329 function, unlike the equivalent pass_in_x() function does not
1330 handle arguments spread across multiple registers. */
1333 pass_in_v (struct gdbarch
*gdbarch
,
1334 struct regcache
*regcache
,
1335 struct aarch64_call_info
*info
,
1336 int len
, const bfd_byte
*buf
)
1340 int regnum
= AARCH64_V0_REGNUM
+ info
->nsrn
;
1341 /* Enough space for a full vector register. */
1342 gdb_byte reg
[register_size (gdbarch
, regnum
)];
1343 gdb_assert (len
<= sizeof (reg
));
1348 memset (reg
, 0, sizeof (reg
));
1349 /* PCS C.1, the argument is allocated to the least significant
1350 bits of V register. */
1351 memcpy (reg
, buf
, len
);
1352 regcache
->cooked_write (regnum
, reg
);
1356 debug_printf ("arg %d in %s\n", info
->argnum
,
1357 gdbarch_register_name (gdbarch
, regnum
));
1365 /* Marshall an argument onto the stack. */
1368 pass_on_stack (struct aarch64_call_info
*info
, struct type
*type
,
1371 const bfd_byte
*buf
= value_contents (arg
);
1372 int len
= TYPE_LENGTH (type
);
1378 align
= aarch64_type_align (type
);
1380 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1381 Natural alignment of the argument's type. */
1382 align
= align_up (align
, 8);
1384 /* The AArch64 PCS requires at most doubleword alignment. */
1390 debug_printf ("arg %d len=%d @ sp + %d\n", info
->argnum
, len
,
1396 VEC_safe_push (stack_item_t
, info
->si
, &item
);
1399 if (info
->nsaa
& (align
- 1))
1401 /* Push stack alignment padding. */
1402 int pad
= align
- (info
->nsaa
& (align
- 1));
1407 VEC_safe_push (stack_item_t
, info
->si
, &item
);
1412 /* Marshall an argument into a sequence of one or more consecutive X
1413 registers or, if insufficient X registers are available then onto
1417 pass_in_x_or_stack (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1418 struct aarch64_call_info
*info
, struct type
*type
,
1421 int len
= TYPE_LENGTH (type
);
1422 int nregs
= (len
+ X_REGISTER_SIZE
- 1) / X_REGISTER_SIZE
;
1424 /* PCS C.13 - Pass in registers if we have enough spare */
1425 if (info
->ngrn
+ nregs
<= 8)
1427 pass_in_x (gdbarch
, regcache
, info
, type
, arg
);
1428 info
->ngrn
+= nregs
;
1433 pass_on_stack (info
, type
, arg
);
1437 /* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1438 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1439 registers. A return value of false is an error state as the value will have
1440 been partially passed to the stack. */
1442 pass_in_v_vfp_candidate (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1443 struct aarch64_call_info
*info
, struct type
*arg_type
,
1446 switch (TYPE_CODE (arg_type
))
1449 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1450 value_contents (arg
));
1453 case TYPE_CODE_COMPLEX
:
1455 const bfd_byte
*buf
= value_contents (arg
);
1456 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (arg_type
));
1458 if (!pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1462 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1463 buf
+ TYPE_LENGTH (target_type
));
1466 case TYPE_CODE_ARRAY
:
1467 if (TYPE_VECTOR (arg_type
))
1468 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1469 value_contents (arg
));
1472 case TYPE_CODE_STRUCT
:
1473 case TYPE_CODE_UNION
:
1474 for (int i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
1476 /* Don't include static fields. */
1477 if (field_is_static (&TYPE_FIELD (arg_type
, i
)))
1480 struct value
*field
= value_primitive_field (arg
, 0, i
, arg_type
);
1481 struct type
*field_type
= check_typedef (value_type (field
));
1483 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, info
, field_type
,
1494 /* Implement the "push_dummy_call" gdbarch method. */
1497 aarch64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1498 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1500 struct value
**args
, CORE_ADDR sp
,
1501 function_call_return_method return_method
,
1502 CORE_ADDR struct_addr
)
1505 struct aarch64_call_info info
;
1507 memset (&info
, 0, sizeof (info
));
1509 /* We need to know what the type of the called function is in order
1510 to determine the number of named/anonymous arguments for the
1511 actual argument placement, and the return type in order to handle
1512 return value correctly.
1514 The generic code above us views the decision of return in memory
1515 or return in registers as a two stage processes. The language
1516 handler is consulted first and may decide to return in memory (eg
1517 class with copy constructor returned by value), this will cause
1518 the generic code to allocate space AND insert an initial leading
1521 If the language code does not decide to pass in memory then the
1522 target code is consulted.
1524 If the language code decides to pass in memory we want to move
1525 the pointer inserted as the initial argument from the argument
1526 list and into X8, the conventional AArch64 struct return pointer
1529 /* Set the return address. For the AArch64, the return breakpoint
1530 is always at BP_ADDR. */
1531 regcache_cooked_write_unsigned (regcache
, AARCH64_LR_REGNUM
, bp_addr
);
1533 /* If we were given an initial argument for the return slot, lose it. */
1534 if (return_method
== return_method_hidden_param
)
1540 /* The struct_return pointer occupies X8. */
1541 if (return_method
!= return_method_normal
)
1545 debug_printf ("struct return in %s = 0x%s\n",
1546 gdbarch_register_name (gdbarch
,
1547 AARCH64_STRUCT_RETURN_REGNUM
),
1548 paddress (gdbarch
, struct_addr
));
1550 regcache_cooked_write_unsigned (regcache
, AARCH64_STRUCT_RETURN_REGNUM
,
1554 for (argnum
= 0; argnum
< nargs
; argnum
++)
1556 struct value
*arg
= args
[argnum
];
1557 struct type
*arg_type
, *fundamental_type
;
1560 arg_type
= check_typedef (value_type (arg
));
1561 len
= TYPE_LENGTH (arg_type
);
1563 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1564 if there are enough spare registers. */
1565 if (aapcs_is_vfp_call_or_return_candidate (arg_type
, &elements
,
1568 if (info
.nsrn
+ elements
<= 8)
1570 /* We know that we have sufficient registers available therefore
1571 this will never need to fallback to the stack. */
1572 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, &info
, arg_type
,
1574 gdb_assert_not_reached ("Failed to push args");
1579 pass_on_stack (&info
, arg_type
, arg
);
1584 switch (TYPE_CODE (arg_type
))
1587 case TYPE_CODE_BOOL
:
1588 case TYPE_CODE_CHAR
:
1589 case TYPE_CODE_RANGE
:
1590 case TYPE_CODE_ENUM
:
1593 /* Promote to 32 bit integer. */
1594 if (TYPE_UNSIGNED (arg_type
))
1595 arg_type
= builtin_type (gdbarch
)->builtin_uint32
;
1597 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
1598 arg
= value_cast (arg_type
, arg
);
1600 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1603 case TYPE_CODE_STRUCT
:
1604 case TYPE_CODE_ARRAY
:
1605 case TYPE_CODE_UNION
:
1608 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1609 invisible reference. */
1611 /* Allocate aligned storage. */
1612 sp
= align_down (sp
- len
, 16);
1614 /* Write the real data into the stack. */
1615 write_memory (sp
, value_contents (arg
), len
);
1617 /* Construct the indirection. */
1618 arg_type
= lookup_pointer_type (arg_type
);
1619 arg
= value_from_pointer (arg_type
, sp
);
1620 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1623 /* PCS C.15 / C.18 multiple values pass. */
1624 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1628 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1633 /* Make sure stack retains 16 byte alignment. */
1635 sp
-= 16 - (info
.nsaa
& 15);
1637 while (!VEC_empty (stack_item_t
, info
.si
))
1639 stack_item_t
*si
= VEC_last (stack_item_t
, info
.si
);
1642 if (si
->data
!= NULL
)
1643 write_memory (sp
, si
->data
, si
->len
);
1644 VEC_pop (stack_item_t
, info
.si
);
1647 VEC_free (stack_item_t
, info
.si
);
1649 /* Finally, update the SP register. */
1650 regcache_cooked_write_unsigned (regcache
, AARCH64_SP_REGNUM
, sp
);
1655 /* Implement the "frame_align" gdbarch method. */
1658 aarch64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1660 /* Align the stack to sixteen bytes. */
1661 return sp
& ~(CORE_ADDR
) 15;
1664 /* Return the type for an AdvSISD Q register. */
1666 static struct type
*
1667 aarch64_vnq_type (struct gdbarch
*gdbarch
)
1669 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1671 if (tdep
->vnq_type
== NULL
)
1676 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1679 elem
= builtin_type (gdbarch
)->builtin_uint128
;
1680 append_composite_type_field (t
, "u", elem
);
1682 elem
= builtin_type (gdbarch
)->builtin_int128
;
1683 append_composite_type_field (t
, "s", elem
);
1688 return tdep
->vnq_type
;
1691 /* Return the type for an AdvSISD D register. */
1693 static struct type
*
1694 aarch64_vnd_type (struct gdbarch
*gdbarch
)
1696 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1698 if (tdep
->vnd_type
== NULL
)
1703 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1706 elem
= builtin_type (gdbarch
)->builtin_double
;
1707 append_composite_type_field (t
, "f", elem
);
1709 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1710 append_composite_type_field (t
, "u", elem
);
1712 elem
= builtin_type (gdbarch
)->builtin_int64
;
1713 append_composite_type_field (t
, "s", elem
);
1718 return tdep
->vnd_type
;
1721 /* Return the type for an AdvSISD S register. */
1723 static struct type
*
1724 aarch64_vns_type (struct gdbarch
*gdbarch
)
1726 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1728 if (tdep
->vns_type
== NULL
)
1733 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
1736 elem
= builtin_type (gdbarch
)->builtin_float
;
1737 append_composite_type_field (t
, "f", elem
);
1739 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1740 append_composite_type_field (t
, "u", elem
);
1742 elem
= builtin_type (gdbarch
)->builtin_int32
;
1743 append_composite_type_field (t
, "s", elem
);
1748 return tdep
->vns_type
;
1751 /* Return the type for an AdvSISD H register. */
1753 static struct type
*
1754 aarch64_vnh_type (struct gdbarch
*gdbarch
)
1756 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1758 if (tdep
->vnh_type
== NULL
)
1763 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
1766 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1767 append_composite_type_field (t
, "u", elem
);
1769 elem
= builtin_type (gdbarch
)->builtin_int16
;
1770 append_composite_type_field (t
, "s", elem
);
1775 return tdep
->vnh_type
;
1778 /* Return the type for an AdvSISD B register. */
1780 static struct type
*
1781 aarch64_vnb_type (struct gdbarch
*gdbarch
)
1783 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1785 if (tdep
->vnb_type
== NULL
)
1790 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
1793 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1794 append_composite_type_field (t
, "u", elem
);
1796 elem
= builtin_type (gdbarch
)->builtin_int8
;
1797 append_composite_type_field (t
, "s", elem
);
1802 return tdep
->vnb_type
;
1805 /* Return the type for an AdvSISD V register. */
1807 static struct type
*
1808 aarch64_vnv_type (struct gdbarch
*gdbarch
)
1810 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1812 if (tdep
->vnv_type
== NULL
)
1814 struct type
*t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnv",
1817 append_composite_type_field (t
, "d", aarch64_vnd_type (gdbarch
));
1818 append_composite_type_field (t
, "s", aarch64_vns_type (gdbarch
));
1819 append_composite_type_field (t
, "h", aarch64_vnh_type (gdbarch
));
1820 append_composite_type_field (t
, "b", aarch64_vnb_type (gdbarch
));
1821 append_composite_type_field (t
, "q", aarch64_vnq_type (gdbarch
));
1826 return tdep
->vnv_type
;
1829 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1832 aarch64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1834 if (reg
>= AARCH64_DWARF_X0
&& reg
<= AARCH64_DWARF_X0
+ 30)
1835 return AARCH64_X0_REGNUM
+ reg
- AARCH64_DWARF_X0
;
1837 if (reg
== AARCH64_DWARF_SP
)
1838 return AARCH64_SP_REGNUM
;
1840 if (reg
>= AARCH64_DWARF_V0
&& reg
<= AARCH64_DWARF_V0
+ 31)
1841 return AARCH64_V0_REGNUM
+ reg
- AARCH64_DWARF_V0
;
1843 if (reg
== AARCH64_DWARF_SVE_VG
)
1844 return AARCH64_SVE_VG_REGNUM
;
1846 if (reg
== AARCH64_DWARF_SVE_FFR
)
1847 return AARCH64_SVE_FFR_REGNUM
;
1849 if (reg
>= AARCH64_DWARF_SVE_P0
&& reg
<= AARCH64_DWARF_SVE_P0
+ 15)
1850 return AARCH64_SVE_P0_REGNUM
+ reg
- AARCH64_DWARF_SVE_P0
;
1852 if (reg
>= AARCH64_DWARF_SVE_Z0
&& reg
<= AARCH64_DWARF_SVE_Z0
+ 15)
1853 return AARCH64_SVE_Z0_REGNUM
+ reg
- AARCH64_DWARF_SVE_Z0
;
1858 /* Implement the "print_insn" gdbarch method. */
1861 aarch64_gdb_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
1863 info
->symbols
= NULL
;
1864 return default_print_insn (memaddr
, info
);
1867 /* AArch64 BRK software debug mode instruction.
1868 Note that AArch64 code is always little-endian.
1869 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
1870 constexpr gdb_byte aarch64_default_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
1872 typedef BP_MANIPULATION (aarch64_default_breakpoint
) aarch64_breakpoint
;
1874 /* Extract from an array REGS containing the (raw) register state a
1875 function return value of type TYPE, and copy that, in virtual
1876 format, into VALBUF. */
1879 aarch64_extract_return_value (struct type
*type
, struct regcache
*regs
,
1882 struct gdbarch
*gdbarch
= regs
->arch ();
1883 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1885 struct type
*fundamental_type
;
1887 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
1890 int len
= TYPE_LENGTH (fundamental_type
);
1892 for (int i
= 0; i
< elements
; i
++)
1894 int regno
= AARCH64_V0_REGNUM
+ i
;
1895 /* Enough space for a full vector register. */
1896 gdb_byte buf
[register_size (gdbarch
, regno
)];
1897 gdb_assert (len
<= sizeof (buf
));
1901 debug_printf ("read HFA or HVA return value element %d from %s\n",
1903 gdbarch_register_name (gdbarch
, regno
));
1905 regs
->cooked_read (regno
, buf
);
1907 memcpy (valbuf
, buf
, len
);
1911 else if (TYPE_CODE (type
) == TYPE_CODE_INT
1912 || TYPE_CODE (type
) == TYPE_CODE_CHAR
1913 || TYPE_CODE (type
) == TYPE_CODE_BOOL
1914 || TYPE_CODE (type
) == TYPE_CODE_PTR
1915 || TYPE_IS_REFERENCE (type
)
1916 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
1918 /* If the type is a plain integer, then the access is
1919 straight-forward. Otherwise we have to play around a bit
1921 int len
= TYPE_LENGTH (type
);
1922 int regno
= AARCH64_X0_REGNUM
;
1927 /* By using store_unsigned_integer we avoid having to do
1928 anything special for small big-endian values. */
1929 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
1930 store_unsigned_integer (valbuf
,
1931 (len
> X_REGISTER_SIZE
1932 ? X_REGISTER_SIZE
: len
), byte_order
, tmp
);
1933 len
-= X_REGISTER_SIZE
;
1934 valbuf
+= X_REGISTER_SIZE
;
1939 /* For a structure or union the behaviour is as if the value had
1940 been stored to word-aligned memory and then loaded into
1941 registers with 64-bit load instruction(s). */
1942 int len
= TYPE_LENGTH (type
);
1943 int regno
= AARCH64_X0_REGNUM
;
1944 bfd_byte buf
[X_REGISTER_SIZE
];
1948 regs
->cooked_read (regno
++, buf
);
1949 memcpy (valbuf
, buf
, len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
1950 len
-= X_REGISTER_SIZE
;
1951 valbuf
+= X_REGISTER_SIZE
;
1957 /* Will a function return an aggregate type in memory or in a
1958 register? Return 0 if an aggregate type can be returned in a
1959 register, 1 if it must be returned in memory. */
1962 aarch64_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
1964 type
= check_typedef (type
);
1966 struct type
*fundamental_type
;
1968 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
1971 /* v0-v7 are used to return values and one register is allocated
1972 for one member. However, HFA or HVA has at most four members. */
1976 if (TYPE_LENGTH (type
) > 16)
1978 /* PCS B.6 Aggregates larger than 16 bytes are passed by
1979 invisible reference. */
1987 /* Write into appropriate registers a function return value of type
1988 TYPE, given in virtual format. */
1991 aarch64_store_return_value (struct type
*type
, struct regcache
*regs
,
1992 const gdb_byte
*valbuf
)
1994 struct gdbarch
*gdbarch
= regs
->arch ();
1995 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1997 struct type
*fundamental_type
;
1999 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2002 int len
= TYPE_LENGTH (fundamental_type
);
2004 for (int i
= 0; i
< elements
; i
++)
2006 int regno
= AARCH64_V0_REGNUM
+ i
;
2007 /* Enough space for a full vector register. */
2008 gdb_byte tmpbuf
[register_size (gdbarch
, regno
)];
2009 gdb_assert (len
<= sizeof (tmpbuf
));
2013 debug_printf ("write HFA or HVA return value element %d to %s\n",
2015 gdbarch_register_name (gdbarch
, regno
));
2018 memcpy (tmpbuf
, valbuf
,
2019 len
> V_REGISTER_SIZE
? V_REGISTER_SIZE
: len
);
2020 regs
->cooked_write (regno
, tmpbuf
);
2024 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2025 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2026 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2027 || TYPE_CODE (type
) == TYPE_CODE_PTR
2028 || TYPE_IS_REFERENCE (type
)
2029 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2031 if (TYPE_LENGTH (type
) <= X_REGISTER_SIZE
)
2033 /* Values of one word or less are zero/sign-extended and
2035 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2036 LONGEST val
= unpack_long (type
, valbuf
);
2038 store_signed_integer (tmpbuf
, X_REGISTER_SIZE
, byte_order
, val
);
2039 regs
->cooked_write (AARCH64_X0_REGNUM
, tmpbuf
);
2043 /* Integral values greater than one word are stored in
2044 consecutive registers starting with r0. This will always
2045 be a multiple of the regiser size. */
2046 int len
= TYPE_LENGTH (type
);
2047 int regno
= AARCH64_X0_REGNUM
;
2051 regs
->cooked_write (regno
++, valbuf
);
2052 len
-= X_REGISTER_SIZE
;
2053 valbuf
+= X_REGISTER_SIZE
;
2059 /* For a structure or union the behaviour is as if the value had
2060 been stored to word-aligned memory and then loaded into
2061 registers with 64-bit load instruction(s). */
2062 int len
= TYPE_LENGTH (type
);
2063 int regno
= AARCH64_X0_REGNUM
;
2064 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2068 memcpy (tmpbuf
, valbuf
,
2069 len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2070 regs
->cooked_write (regno
++, tmpbuf
);
2071 len
-= X_REGISTER_SIZE
;
2072 valbuf
+= X_REGISTER_SIZE
;
2077 /* Implement the "return_value" gdbarch method. */
2079 static enum return_value_convention
2080 aarch64_return_value (struct gdbarch
*gdbarch
, struct value
*func_value
,
2081 struct type
*valtype
, struct regcache
*regcache
,
2082 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2085 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2086 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2087 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2089 if (aarch64_return_in_memory (gdbarch
, valtype
))
2092 debug_printf ("return value in memory\n");
2093 return RETURN_VALUE_STRUCT_CONVENTION
;
2098 aarch64_store_return_value (valtype
, regcache
, writebuf
);
2101 aarch64_extract_return_value (valtype
, regcache
, readbuf
);
2104 debug_printf ("return value in registers\n");
2106 return RETURN_VALUE_REGISTER_CONVENTION
;
2109 /* Implement the "get_longjmp_target" gdbarch method. */
2112 aarch64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2115 gdb_byte buf
[X_REGISTER_SIZE
];
2116 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2117 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2118 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2120 jb_addr
= get_frame_register_unsigned (frame
, AARCH64_X0_REGNUM
);
2122 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2126 *pc
= extract_unsigned_integer (buf
, X_REGISTER_SIZE
, byte_order
);
2130 /* Implement the "gen_return_address" gdbarch method. */
2133 aarch64_gen_return_address (struct gdbarch
*gdbarch
,
2134 struct agent_expr
*ax
, struct axs_value
*value
,
2137 value
->type
= register_type (gdbarch
, AARCH64_LR_REGNUM
);
2138 value
->kind
= axs_lvalue_register
;
2139 value
->u
.reg
= AARCH64_LR_REGNUM
;
2143 /* Return the pseudo register name corresponding to register regnum. */
2146 aarch64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
2148 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2150 static const char *const q_name
[] =
2152 "q0", "q1", "q2", "q3",
2153 "q4", "q5", "q6", "q7",
2154 "q8", "q9", "q10", "q11",
2155 "q12", "q13", "q14", "q15",
2156 "q16", "q17", "q18", "q19",
2157 "q20", "q21", "q22", "q23",
2158 "q24", "q25", "q26", "q27",
2159 "q28", "q29", "q30", "q31",
2162 static const char *const d_name
[] =
2164 "d0", "d1", "d2", "d3",
2165 "d4", "d5", "d6", "d7",
2166 "d8", "d9", "d10", "d11",
2167 "d12", "d13", "d14", "d15",
2168 "d16", "d17", "d18", "d19",
2169 "d20", "d21", "d22", "d23",
2170 "d24", "d25", "d26", "d27",
2171 "d28", "d29", "d30", "d31",
2174 static const char *const s_name
[] =
2176 "s0", "s1", "s2", "s3",
2177 "s4", "s5", "s6", "s7",
2178 "s8", "s9", "s10", "s11",
2179 "s12", "s13", "s14", "s15",
2180 "s16", "s17", "s18", "s19",
2181 "s20", "s21", "s22", "s23",
2182 "s24", "s25", "s26", "s27",
2183 "s28", "s29", "s30", "s31",
2186 static const char *const h_name
[] =
2188 "h0", "h1", "h2", "h3",
2189 "h4", "h5", "h6", "h7",
2190 "h8", "h9", "h10", "h11",
2191 "h12", "h13", "h14", "h15",
2192 "h16", "h17", "h18", "h19",
2193 "h20", "h21", "h22", "h23",
2194 "h24", "h25", "h26", "h27",
2195 "h28", "h29", "h30", "h31",
2198 static const char *const b_name
[] =
2200 "b0", "b1", "b2", "b3",
2201 "b4", "b5", "b6", "b7",
2202 "b8", "b9", "b10", "b11",
2203 "b12", "b13", "b14", "b15",
2204 "b16", "b17", "b18", "b19",
2205 "b20", "b21", "b22", "b23",
2206 "b24", "b25", "b26", "b27",
2207 "b28", "b29", "b30", "b31",
2210 regnum
-= gdbarch_num_regs (gdbarch
);
2212 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2213 return q_name
[regnum
- AARCH64_Q0_REGNUM
];
2215 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2216 return d_name
[regnum
- AARCH64_D0_REGNUM
];
2218 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2219 return s_name
[regnum
- AARCH64_S0_REGNUM
];
2221 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2222 return h_name
[regnum
- AARCH64_H0_REGNUM
];
2224 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2225 return b_name
[regnum
- AARCH64_B0_REGNUM
];
2227 if (tdep
->has_sve ())
2229 static const char *const sve_v_name
[] =
2231 "v0", "v1", "v2", "v3",
2232 "v4", "v5", "v6", "v7",
2233 "v8", "v9", "v10", "v11",
2234 "v12", "v13", "v14", "v15",
2235 "v16", "v17", "v18", "v19",
2236 "v20", "v21", "v22", "v23",
2237 "v24", "v25", "v26", "v27",
2238 "v28", "v29", "v30", "v31",
2241 if (regnum
>= AARCH64_SVE_V0_REGNUM
2242 && regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2243 return sve_v_name
[regnum
- AARCH64_SVE_V0_REGNUM
];
2246 internal_error (__FILE__
, __LINE__
,
2247 _("aarch64_pseudo_register_name: bad register number %d"),
2251 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2253 static struct type
*
2254 aarch64_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2256 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2258 regnum
-= gdbarch_num_regs (gdbarch
);
2260 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2261 return aarch64_vnq_type (gdbarch
);
2263 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2264 return aarch64_vnd_type (gdbarch
);
2266 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2267 return aarch64_vns_type (gdbarch
);
2269 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2270 return aarch64_vnh_type (gdbarch
);
2272 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2273 return aarch64_vnb_type (gdbarch
);
2275 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2276 && regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2277 return aarch64_vnv_type (gdbarch
);
2279 internal_error (__FILE__
, __LINE__
,
2280 _("aarch64_pseudo_register_type: bad register number %d"),
2284 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2287 aarch64_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2288 struct reggroup
*group
)
2290 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2292 regnum
-= gdbarch_num_regs (gdbarch
);
2294 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2295 return group
== all_reggroup
|| group
== vector_reggroup
;
2296 else if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2297 return (group
== all_reggroup
|| group
== vector_reggroup
2298 || group
== float_reggroup
);
2299 else if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2300 return (group
== all_reggroup
|| group
== vector_reggroup
2301 || group
== float_reggroup
);
2302 else if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2303 return group
== all_reggroup
|| group
== vector_reggroup
;
2304 else if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2305 return group
== all_reggroup
|| group
== vector_reggroup
;
2306 else if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2307 && regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2308 return group
== all_reggroup
|| group
== vector_reggroup
;
2310 return group
== all_reggroup
;
2313 /* Helper for aarch64_pseudo_read_value. */
2315 static struct value
*
2316 aarch64_pseudo_read_value_1 (struct gdbarch
*gdbarch
,
2317 readable_regcache
*regcache
, int regnum_offset
,
2318 int regsize
, struct value
*result_value
)
2320 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2322 /* Enough space for a full vector register. */
2323 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2324 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2326 if (regcache
->raw_read (v_regnum
, reg_buf
) != REG_VALID
)
2327 mark_value_bytes_unavailable (result_value
, 0,
2328 TYPE_LENGTH (value_type (result_value
)));
2330 memcpy (value_contents_raw (result_value
), reg_buf
, regsize
);
2332 return result_value
;
2335 /* Implement the "pseudo_register_read_value" gdbarch method. */
2337 static struct value
*
2338 aarch64_pseudo_read_value (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2341 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2342 struct value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
2344 VALUE_LVAL (result_value
) = lval_register
;
2345 VALUE_REGNUM (result_value
) = regnum
;
2347 regnum
-= gdbarch_num_regs (gdbarch
);
2349 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2350 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2351 regnum
- AARCH64_Q0_REGNUM
,
2352 Q_REGISTER_SIZE
, result_value
);
2354 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2355 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2356 regnum
- AARCH64_D0_REGNUM
,
2357 D_REGISTER_SIZE
, result_value
);
2359 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2360 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2361 regnum
- AARCH64_S0_REGNUM
,
2362 S_REGISTER_SIZE
, result_value
);
2364 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2365 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2366 regnum
- AARCH64_H0_REGNUM
,
2367 H_REGISTER_SIZE
, result_value
);
2369 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2370 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2371 regnum
- AARCH64_B0_REGNUM
,
2372 B_REGISTER_SIZE
, result_value
);
2374 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2375 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2376 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2377 regnum
- AARCH64_SVE_V0_REGNUM
,
2378 V_REGISTER_SIZE
, result_value
);
2380 gdb_assert_not_reached ("regnum out of bound");
2383 /* Helper for aarch64_pseudo_write. */
2386 aarch64_pseudo_write_1 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2387 int regnum_offset
, int regsize
, const gdb_byte
*buf
)
2389 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2391 /* Enough space for a full vector register. */
2392 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2393 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2395 /* Ensure the register buffer is zero, we want gdb writes of the
2396 various 'scalar' pseudo registers to behavior like architectural
2397 writes, register width bytes are written the remainder are set to
2399 memset (reg_buf
, 0, register_size (gdbarch
, AARCH64_V0_REGNUM
));
2401 memcpy (reg_buf
, buf
, regsize
);
2402 regcache
->raw_write (v_regnum
, reg_buf
);
2405 /* Implement the "pseudo_register_write" gdbarch method. */
2408 aarch64_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2409 int regnum
, const gdb_byte
*buf
)
2411 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2412 regnum
-= gdbarch_num_regs (gdbarch
);
2414 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2415 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2416 regnum
- AARCH64_Q0_REGNUM
, Q_REGISTER_SIZE
,
2419 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2420 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2421 regnum
- AARCH64_D0_REGNUM
, D_REGISTER_SIZE
,
2424 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2425 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2426 regnum
- AARCH64_S0_REGNUM
, S_REGISTER_SIZE
,
2429 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2430 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2431 regnum
- AARCH64_H0_REGNUM
, H_REGISTER_SIZE
,
2434 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2435 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2436 regnum
- AARCH64_B0_REGNUM
, B_REGISTER_SIZE
,
2439 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2440 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2441 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2442 regnum
- AARCH64_SVE_V0_REGNUM
,
2443 V_REGISTER_SIZE
, buf
);
2445 gdb_assert_not_reached ("regnum out of bound");
2448 /* Callback function for user_reg_add. */
2450 static struct value
*
2451 value_of_aarch64_user_reg (struct frame_info
*frame
, const void *baton
)
2453 const int *reg_p
= (const int *) baton
;
2455 return value_of_register (*reg_p
, frame
);
2459 /* Implement the "software_single_step" gdbarch method, needed to
2460 single step through atomic sequences on AArch64. */
2462 static std::vector
<CORE_ADDR
>
2463 aarch64_software_single_step (struct regcache
*regcache
)
2465 struct gdbarch
*gdbarch
= regcache
->arch ();
2466 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2467 const int insn_size
= 4;
2468 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2469 CORE_ADDR pc
= regcache_read_pc (regcache
);
2470 CORE_ADDR breaks
[2] = { CORE_ADDR_MAX
, CORE_ADDR_MAX
};
2472 CORE_ADDR closing_insn
= 0;
2473 uint32_t insn
= read_memory_unsigned_integer (loc
, insn_size
,
2474 byte_order_for_code
);
2477 int bc_insn_count
= 0; /* Conditional branch instruction count. */
2478 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2481 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2484 /* Look for a Load Exclusive instruction which begins the sequence. */
2485 if (inst
.opcode
->iclass
!= ldstexcl
|| bit (insn
, 22) == 0)
2488 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2491 insn
= read_memory_unsigned_integer (loc
, insn_size
,
2492 byte_order_for_code
);
2494 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2496 /* Check if the instruction is a conditional branch. */
2497 if (inst
.opcode
->iclass
== condbranch
)
2499 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_ADDR_PCREL19
);
2501 if (bc_insn_count
>= 1)
2504 /* It is, so we'll try to set a breakpoint at the destination. */
2505 breaks
[1] = loc
+ inst
.operands
[0].imm
.value
;
2511 /* Look for the Store Exclusive which closes the atomic sequence. */
2512 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22) == 0)
2519 /* We didn't find a closing Store Exclusive instruction, fall back. */
2523 /* Insert breakpoint after the end of the atomic sequence. */
2524 breaks
[0] = loc
+ insn_size
;
2526 /* Check for duplicated breakpoints, and also check that the second
2527 breakpoint is not within the atomic sequence. */
2529 && (breaks
[1] == breaks
[0]
2530 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
2531 last_breakpoint
= 0;
2533 std::vector
<CORE_ADDR
> next_pcs
;
2535 /* Insert the breakpoint at the end of the sequence, and one at the
2536 destination of the conditional branch, if it exists. */
2537 for (index
= 0; index
<= last_breakpoint
; index
++)
2538 next_pcs
.push_back (breaks
[index
]);
2543 struct aarch64_displaced_step_closure
: public displaced_step_closure
2545 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2546 is being displaced stepping. */
2549 /* PC adjustment offset after displaced stepping. */
2550 int32_t pc_adjust
= 0;
2553 /* Data when visiting instructions for displaced stepping. */
2555 struct aarch64_displaced_step_data
2557 struct aarch64_insn_data base
;
2559 /* The address where the instruction will be executed at. */
2561 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2562 uint32_t insn_buf
[DISPLACED_MODIFIED_INSNS
];
2563 /* Number of instructions in INSN_BUF. */
2564 unsigned insn_count
;
2565 /* Registers when doing displaced stepping. */
2566 struct regcache
*regs
;
2568 aarch64_displaced_step_closure
*dsc
;
2571 /* Implementation of aarch64_insn_visitor method "b". */
2574 aarch64_displaced_step_b (const int is_bl
, const int32_t offset
,
2575 struct aarch64_insn_data
*data
)
2577 struct aarch64_displaced_step_data
*dsd
2578 = (struct aarch64_displaced_step_data
*) data
;
2579 int64_t new_offset
= data
->insn_addr
- dsd
->new_addr
+ offset
;
2581 if (can_encode_int32 (new_offset
, 28))
2583 /* Emit B rather than BL, because executing BL on a new address
2584 will get the wrong address into LR. In order to avoid this,
2585 we emit B, and update LR if the instruction is BL. */
2586 emit_b (dsd
->insn_buf
, 0, new_offset
);
2592 emit_nop (dsd
->insn_buf
);
2594 dsd
->dsc
->pc_adjust
= offset
;
2600 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
2601 data
->insn_addr
+ 4);
2605 /* Implementation of aarch64_insn_visitor method "b_cond". */
2608 aarch64_displaced_step_b_cond (const unsigned cond
, const int32_t offset
,
2609 struct aarch64_insn_data
*data
)
2611 struct aarch64_displaced_step_data
*dsd
2612 = (struct aarch64_displaced_step_data
*) data
;
2614 /* GDB has to fix up PC after displaced step this instruction
2615 differently according to the condition is true or false. Instead
2616 of checking COND against conditional flags, we can use
2617 the following instructions, and GDB can tell how to fix up PC
2618 according to the PC value.
2620 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2626 emit_bcond (dsd
->insn_buf
, cond
, 8);
2628 dsd
->dsc
->pc_adjust
= offset
;
2629 dsd
->insn_count
= 1;
2632 /* Dynamically allocate a new register. If we know the register
2633 statically, we should make it a global as above instead of using this
2636 static struct aarch64_register
2637 aarch64_register (unsigned num
, int is64
)
2639 return (struct aarch64_register
) { num
, is64
};
2642 /* Implementation of aarch64_insn_visitor method "cb". */
2645 aarch64_displaced_step_cb (const int32_t offset
, const int is_cbnz
,
2646 const unsigned rn
, int is64
,
2647 struct aarch64_insn_data
*data
)
2649 struct aarch64_displaced_step_data
*dsd
2650 = (struct aarch64_displaced_step_data
*) data
;
2652 /* The offset is out of range for a compare and branch
2653 instruction. We can use the following instructions instead:
2655 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2660 emit_cb (dsd
->insn_buf
, is_cbnz
, aarch64_register (rn
, is64
), 8);
2661 dsd
->insn_count
= 1;
2663 dsd
->dsc
->pc_adjust
= offset
;
2666 /* Implementation of aarch64_insn_visitor method "tb". */
2669 aarch64_displaced_step_tb (const int32_t offset
, int is_tbnz
,
2670 const unsigned rt
, unsigned bit
,
2671 struct aarch64_insn_data
*data
)
2673 struct aarch64_displaced_step_data
*dsd
2674 = (struct aarch64_displaced_step_data
*) data
;
2676 /* The offset is out of range for a test bit and branch
2677 instruction We can use the following instructions instead:
2679 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2685 emit_tb (dsd
->insn_buf
, is_tbnz
, bit
, aarch64_register (rt
, 1), 8);
2686 dsd
->insn_count
= 1;
2688 dsd
->dsc
->pc_adjust
= offset
;
2691 /* Implementation of aarch64_insn_visitor method "adr". */
2694 aarch64_displaced_step_adr (const int32_t offset
, const unsigned rd
,
2695 const int is_adrp
, struct aarch64_insn_data
*data
)
2697 struct aarch64_displaced_step_data
*dsd
2698 = (struct aarch64_displaced_step_data
*) data
;
2699 /* We know exactly the address the ADR{P,} instruction will compute.
2700 We can just write it to the destination register. */
2701 CORE_ADDR address
= data
->insn_addr
+ offset
;
2705 /* Clear the lower 12 bits of the offset to get the 4K page. */
2706 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2710 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2713 dsd
->dsc
->pc_adjust
= 4;
2714 emit_nop (dsd
->insn_buf
);
2715 dsd
->insn_count
= 1;
2718 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2721 aarch64_displaced_step_ldr_literal (const int32_t offset
, const int is_sw
,
2722 const unsigned rt
, const int is64
,
2723 struct aarch64_insn_data
*data
)
2725 struct aarch64_displaced_step_data
*dsd
2726 = (struct aarch64_displaced_step_data
*) data
;
2727 CORE_ADDR address
= data
->insn_addr
+ offset
;
2728 struct aarch64_memory_operand zero
= { MEMORY_OPERAND_OFFSET
, 0 };
2730 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rt
,
2734 dsd
->insn_count
= emit_ldrsw (dsd
->insn_buf
, aarch64_register (rt
, 1),
2735 aarch64_register (rt
, 1), zero
);
2737 dsd
->insn_count
= emit_ldr (dsd
->insn_buf
, aarch64_register (rt
, is64
),
2738 aarch64_register (rt
, 1), zero
);
2740 dsd
->dsc
->pc_adjust
= 4;
2743 /* Implementation of aarch64_insn_visitor method "others". */
2746 aarch64_displaced_step_others (const uint32_t insn
,
2747 struct aarch64_insn_data
*data
)
2749 struct aarch64_displaced_step_data
*dsd
2750 = (struct aarch64_displaced_step_data
*) data
;
2752 aarch64_emit_insn (dsd
->insn_buf
, insn
);
2753 dsd
->insn_count
= 1;
2755 if ((insn
& 0xfffffc1f) == 0xd65f0000)
2758 dsd
->dsc
->pc_adjust
= 0;
2761 dsd
->dsc
->pc_adjust
= 4;
2764 static const struct aarch64_insn_visitor visitor
=
2766 aarch64_displaced_step_b
,
2767 aarch64_displaced_step_b_cond
,
2768 aarch64_displaced_step_cb
,
2769 aarch64_displaced_step_tb
,
2770 aarch64_displaced_step_adr
,
2771 aarch64_displaced_step_ldr_literal
,
2772 aarch64_displaced_step_others
,
2775 /* Implement the "displaced_step_copy_insn" gdbarch method. */
2777 struct displaced_step_closure
*
2778 aarch64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
2779 CORE_ADDR from
, CORE_ADDR to
,
2780 struct regcache
*regs
)
2782 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2783 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
2784 struct aarch64_displaced_step_data dsd
;
2787 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2790 /* Look for a Load Exclusive instruction which begins the sequence. */
2791 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22))
2793 /* We can't displaced step atomic sequences. */
2797 std::unique_ptr
<aarch64_displaced_step_closure
> dsc
2798 (new aarch64_displaced_step_closure
);
2799 dsd
.base
.insn_addr
= from
;
2802 dsd
.dsc
= dsc
.get ();
2804 aarch64_relocate_instruction (insn
, &visitor
,
2805 (struct aarch64_insn_data
*) &dsd
);
2806 gdb_assert (dsd
.insn_count
<= DISPLACED_MODIFIED_INSNS
);
2808 if (dsd
.insn_count
!= 0)
2812 /* Instruction can be relocated to scratch pad. Copy
2813 relocated instruction(s) there. */
2814 for (i
= 0; i
< dsd
.insn_count
; i
++)
2816 if (debug_displaced
)
2818 debug_printf ("displaced: writing insn ");
2819 debug_printf ("%.8x", dsd
.insn_buf
[i
]);
2820 debug_printf (" at %s\n", paddress (gdbarch
, to
+ i
* 4));
2822 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
2823 (ULONGEST
) dsd
.insn_buf
[i
]);
2831 return dsc
.release ();
2834 /* Implement the "displaced_step_fixup" gdbarch method. */
2837 aarch64_displaced_step_fixup (struct gdbarch
*gdbarch
,
2838 struct displaced_step_closure
*dsc_
,
2839 CORE_ADDR from
, CORE_ADDR to
,
2840 struct regcache
*regs
)
2842 aarch64_displaced_step_closure
*dsc
= (aarch64_displaced_step_closure
*) dsc_
;
2848 regcache_cooked_read_unsigned (regs
, AARCH64_PC_REGNUM
, &pc
);
2851 /* Condition is true. */
2853 else if (pc
- to
== 4)
2855 /* Condition is false. */
2859 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
2862 if (dsc
->pc_adjust
!= 0)
2864 if (debug_displaced
)
2866 debug_printf ("displaced: fixup: set PC to %s:%d\n",
2867 paddress (gdbarch
, from
), dsc
->pc_adjust
);
2869 regcache_cooked_write_unsigned (regs
, AARCH64_PC_REGNUM
,
2870 from
+ dsc
->pc_adjust
);
2874 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
2877 aarch64_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
2878 struct displaced_step_closure
*closure
)
2883 /* Get the correct target description for the given VQ value.
2884 If VQ is zero then it is assumed SVE is not supported.
2885 (It is not possible to set VQ to zero on an SVE system). */
2888 aarch64_read_description (uint64_t vq
)
2890 if (vq
> AARCH64_MAX_SVE_VQ
)
2891 error (_("VQ is %" PRIu64
", maximum supported value is %d"), vq
,
2892 AARCH64_MAX_SVE_VQ
);
2894 struct target_desc
*tdesc
= tdesc_aarch64_list
[vq
];
2898 tdesc
= aarch64_create_target_description (vq
);
2899 tdesc_aarch64_list
[vq
] = tdesc
;
2905 /* Return the VQ used when creating the target description TDESC. */
2908 aarch64_get_tdesc_vq (const struct target_desc
*tdesc
)
2910 const struct tdesc_feature
*feature_sve
;
2912 if (!tdesc_has_registers (tdesc
))
2915 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
2917 if (feature_sve
== nullptr)
2920 uint64_t vl
= tdesc_register_bitsize (feature_sve
,
2921 aarch64_sve_register_names
[0]) / 8;
2922 return sve_vq_from_vl (vl
);
2925 /* Add all the expected register sets into GDBARCH. */
2928 aarch64_add_reggroups (struct gdbarch
*gdbarch
)
2930 reggroup_add (gdbarch
, general_reggroup
);
2931 reggroup_add (gdbarch
, float_reggroup
);
2932 reggroup_add (gdbarch
, system_reggroup
);
2933 reggroup_add (gdbarch
, vector_reggroup
);
2934 reggroup_add (gdbarch
, all_reggroup
);
2935 reggroup_add (gdbarch
, save_reggroup
);
2936 reggroup_add (gdbarch
, restore_reggroup
);
2939 /* Initialize the current architecture based on INFO. If possible,
2940 re-use an architecture from ARCHES, which is a list of
2941 architectures already created during this debugging session.
2943 Called e.g. at program startup, when reading a core file, and when
2944 reading a binary file. */
2946 static struct gdbarch
*
2947 aarch64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2949 struct gdbarch_tdep
*tdep
;
2950 struct gdbarch
*gdbarch
;
2951 struct gdbarch_list
*best_arch
;
2952 struct tdesc_arch_data
*tdesc_data
= NULL
;
2953 const struct target_desc
*tdesc
= info
.target_desc
;
2956 const struct tdesc_feature
*feature_core
;
2957 const struct tdesc_feature
*feature_fpu
;
2958 const struct tdesc_feature
*feature_sve
;
2960 int num_pseudo_regs
= 0;
2962 /* Ensure we always have a target description. */
2963 if (!tdesc_has_registers (tdesc
))
2964 tdesc
= aarch64_read_description (0);
2967 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.core");
2968 feature_fpu
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.fpu");
2969 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
2971 if (feature_core
== NULL
)
2974 tdesc_data
= tdesc_data_alloc ();
2976 /* Validate the description provides the mandatory core R registers
2977 and allocate their numbers. */
2978 for (i
= 0; i
< ARRAY_SIZE (aarch64_r_register_names
); i
++)
2979 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
,
2980 AARCH64_X0_REGNUM
+ i
,
2981 aarch64_r_register_names
[i
]);
2983 num_regs
= AARCH64_X0_REGNUM
+ i
;
2985 /* Add the V registers. */
2986 if (feature_fpu
!= NULL
)
2988 if (feature_sve
!= NULL
)
2989 error (_("Program contains both fpu and SVE features."));
2991 /* Validate the description provides the mandatory V registers
2992 and allocate their numbers. */
2993 for (i
= 0; i
< ARRAY_SIZE (aarch64_v_register_names
); i
++)
2994 valid_p
&= tdesc_numbered_register (feature_fpu
, tdesc_data
,
2995 AARCH64_V0_REGNUM
+ i
,
2996 aarch64_v_register_names
[i
]);
2998 num_regs
= AARCH64_V0_REGNUM
+ i
;
3001 /* Add the SVE registers. */
3002 if (feature_sve
!= NULL
)
3004 /* Validate the description provides the mandatory SVE registers
3005 and allocate their numbers. */
3006 for (i
= 0; i
< ARRAY_SIZE (aarch64_sve_register_names
); i
++)
3007 valid_p
&= tdesc_numbered_register (feature_sve
, tdesc_data
,
3008 AARCH64_SVE_Z0_REGNUM
+ i
,
3009 aarch64_sve_register_names
[i
]);
3011 num_regs
= AARCH64_SVE_Z0_REGNUM
+ i
;
3012 num_pseudo_regs
+= 32; /* add the Vn register pseudos. */
3015 if (feature_fpu
!= NULL
|| feature_sve
!= NULL
)
3017 num_pseudo_regs
+= 32; /* add the Qn scalar register pseudos */
3018 num_pseudo_regs
+= 32; /* add the Dn scalar register pseudos */
3019 num_pseudo_regs
+= 32; /* add the Sn scalar register pseudos */
3020 num_pseudo_regs
+= 32; /* add the Hn scalar register pseudos */
3021 num_pseudo_regs
+= 32; /* add the Bn scalar register pseudos */
3026 tdesc_data_cleanup (tdesc_data
);
3030 /* AArch64 code is always little-endian. */
3031 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
3033 /* If there is already a candidate, use it. */
3034 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3036 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3038 /* Found a match. */
3042 if (best_arch
!= NULL
)
3044 if (tdesc_data
!= NULL
)
3045 tdesc_data_cleanup (tdesc_data
);
3046 return best_arch
->gdbarch
;
3049 tdep
= XCNEW (struct gdbarch_tdep
);
3050 gdbarch
= gdbarch_alloc (&info
, tdep
);
3052 /* This should be low enough for everything. */
3053 tdep
->lowest_pc
= 0x20;
3054 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3055 tdep
->jb_elt_size
= 8;
3056 tdep
->vq
= aarch64_get_tdesc_vq (tdesc
);
3058 set_gdbarch_push_dummy_call (gdbarch
, aarch64_push_dummy_call
);
3059 set_gdbarch_frame_align (gdbarch
, aarch64_frame_align
);
3061 /* Advance PC across function entry code. */
3062 set_gdbarch_skip_prologue (gdbarch
, aarch64_skip_prologue
);
3064 /* The stack grows downward. */
3065 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3067 /* Breakpoint manipulation. */
3068 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3069 aarch64_breakpoint::kind_from_pc
);
3070 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3071 aarch64_breakpoint::bp_from_kind
);
3072 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3073 set_gdbarch_software_single_step (gdbarch
, aarch64_software_single_step
);
3075 /* Information about registers, etc. */
3076 set_gdbarch_sp_regnum (gdbarch
, AARCH64_SP_REGNUM
);
3077 set_gdbarch_pc_regnum (gdbarch
, AARCH64_PC_REGNUM
);
3078 set_gdbarch_num_regs (gdbarch
, num_regs
);
3080 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3081 set_gdbarch_pseudo_register_read_value (gdbarch
, aarch64_pseudo_read_value
);
3082 set_gdbarch_pseudo_register_write (gdbarch
, aarch64_pseudo_write
);
3083 set_tdesc_pseudo_register_name (gdbarch
, aarch64_pseudo_register_name
);
3084 set_tdesc_pseudo_register_type (gdbarch
, aarch64_pseudo_register_type
);
3085 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3086 aarch64_pseudo_register_reggroup_p
);
3089 set_gdbarch_short_bit (gdbarch
, 16);
3090 set_gdbarch_int_bit (gdbarch
, 32);
3091 set_gdbarch_float_bit (gdbarch
, 32);
3092 set_gdbarch_double_bit (gdbarch
, 64);
3093 set_gdbarch_long_double_bit (gdbarch
, 128);
3094 set_gdbarch_long_bit (gdbarch
, 64);
3095 set_gdbarch_long_long_bit (gdbarch
, 64);
3096 set_gdbarch_ptr_bit (gdbarch
, 64);
3097 set_gdbarch_char_signed (gdbarch
, 0);
3098 set_gdbarch_wchar_signed (gdbarch
, 0);
3099 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3100 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3101 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3103 /* Internal <-> external register number maps. */
3104 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, aarch64_dwarf_reg_to_regnum
);
3106 /* Returning results. */
3107 set_gdbarch_return_value (gdbarch
, aarch64_return_value
);
3110 set_gdbarch_print_insn (gdbarch
, aarch64_gdb_print_insn
);
3112 /* Virtual tables. */
3113 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3115 /* Register architecture. */
3116 aarch64_add_reggroups (gdbarch
);
3118 /* Hook in the ABI-specific overrides, if they have been registered. */
3119 info
.target_desc
= tdesc
;
3120 info
.tdesc_data
= tdesc_data
;
3121 gdbarch_init_osabi (info
, gdbarch
);
3123 dwarf2_frame_set_init_reg (gdbarch
, aarch64_dwarf2_frame_init_reg
);
3125 /* Add some default predicates. */
3126 frame_unwind_append_unwinder (gdbarch
, &aarch64_stub_unwind
);
3127 dwarf2_append_unwinders (gdbarch
);
3128 frame_unwind_append_unwinder (gdbarch
, &aarch64_prologue_unwind
);
3130 frame_base_set_default (gdbarch
, &aarch64_normal_base
);
3132 /* Now we have tuned the configuration, set a few final things,
3133 based on what the OS ABI has told us. */
3135 if (tdep
->jb_pc
>= 0)
3136 set_gdbarch_get_longjmp_target (gdbarch
, aarch64_get_longjmp_target
);
3138 set_gdbarch_gen_return_address (gdbarch
, aarch64_gen_return_address
);
3140 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3142 /* Add standard register aliases. */
3143 for (i
= 0; i
< ARRAY_SIZE (aarch64_register_aliases
); i
++)
3144 user_reg_add (gdbarch
, aarch64_register_aliases
[i
].name
,
3145 value_of_aarch64_user_reg
,
3146 &aarch64_register_aliases
[i
].regnum
);
3148 register_aarch64_ravenscar_ops (gdbarch
);
3154 aarch64_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3156 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3161 fprintf_unfiltered (file
, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3162 paddress (gdbarch
, tdep
->lowest_pc
));
3168 static void aarch64_process_record_test (void);
3173 _initialize_aarch64_tdep (void)
3175 gdbarch_register (bfd_arch_aarch64
, aarch64_gdbarch_init
,
3178 /* Debug this file's internals. */
3179 add_setshow_boolean_cmd ("aarch64", class_maintenance
, &aarch64_debug
, _("\
3180 Set AArch64 debugging."), _("\
3181 Show AArch64 debugging."), _("\
3182 When on, AArch64 specific debugging is enabled."),
3185 &setdebuglist
, &showdebuglist
);
3188 selftests::register_test ("aarch64-analyze-prologue",
3189 selftests::aarch64_analyze_prologue_test
);
3190 selftests::register_test ("aarch64-process-record",
3191 selftests::aarch64_process_record_test
);
3192 selftests::record_xml_tdesc ("aarch64.xml",
3193 aarch64_create_target_description (0));
3197 /* AArch64 process record-replay related structures, defines etc. */
3199 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3202 unsigned int reg_len = LENGTH; \
3205 REGS = XNEWVEC (uint32_t, reg_len); \
3206 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3211 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3214 unsigned int mem_len = LENGTH; \
3217 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3218 memcpy(&MEMS->len, &RECORD_BUF[0], \
3219 sizeof(struct aarch64_mem_r) * LENGTH); \
3224 /* AArch64 record/replay structures and enumerations. */
3226 struct aarch64_mem_r
3228 uint64_t len
; /* Record length. */
3229 uint64_t addr
; /* Memory address. */
3232 enum aarch64_record_result
3234 AARCH64_RECORD_SUCCESS
,
3235 AARCH64_RECORD_UNSUPPORTED
,
3236 AARCH64_RECORD_UNKNOWN
3239 typedef struct insn_decode_record_t
3241 struct gdbarch
*gdbarch
;
3242 struct regcache
*regcache
;
3243 CORE_ADDR this_addr
; /* Address of insn to be recorded. */
3244 uint32_t aarch64_insn
; /* Insn to be recorded. */
3245 uint32_t mem_rec_count
; /* Count of memory records. */
3246 uint32_t reg_rec_count
; /* Count of register records. */
3247 uint32_t *aarch64_regs
; /* Registers to be recorded. */
3248 struct aarch64_mem_r
*aarch64_mems
; /* Memory locations to be recorded. */
3249 } insn_decode_record
;
3251 /* Record handler for data processing - register instructions. */
3254 aarch64_record_data_proc_reg (insn_decode_record
*aarch64_insn_r
)
3256 uint8_t reg_rd
, insn_bits24_27
, insn_bits21_23
;
3257 uint32_t record_buf
[4];
3259 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3260 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3261 insn_bits21_23
= bits (aarch64_insn_r
->aarch64_insn
, 21, 23);
3263 if (!bit (aarch64_insn_r
->aarch64_insn
, 28))
3267 /* Logical (shifted register). */
3268 if (insn_bits24_27
== 0x0a)
3269 setflags
= (bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03);
3271 else if (insn_bits24_27
== 0x0b)
3272 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3274 return AARCH64_RECORD_UNKNOWN
;
3276 record_buf
[0] = reg_rd
;
3277 aarch64_insn_r
->reg_rec_count
= 1;
3279 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3283 if (insn_bits24_27
== 0x0b)
3285 /* Data-processing (3 source). */
3286 record_buf
[0] = reg_rd
;
3287 aarch64_insn_r
->reg_rec_count
= 1;
3289 else if (insn_bits24_27
== 0x0a)
3291 if (insn_bits21_23
== 0x00)
3293 /* Add/subtract (with carry). */
3294 record_buf
[0] = reg_rd
;
3295 aarch64_insn_r
->reg_rec_count
= 1;
3296 if (bit (aarch64_insn_r
->aarch64_insn
, 29))
3298 record_buf
[1] = AARCH64_CPSR_REGNUM
;
3299 aarch64_insn_r
->reg_rec_count
= 2;
3302 else if (insn_bits21_23
== 0x02)
3304 /* Conditional compare (register) and conditional compare
3305 (immediate) instructions. */
3306 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3307 aarch64_insn_r
->reg_rec_count
= 1;
3309 else if (insn_bits21_23
== 0x04 || insn_bits21_23
== 0x06)
3311 /* CConditional select. */
3312 /* Data-processing (2 source). */
3313 /* Data-processing (1 source). */
3314 record_buf
[0] = reg_rd
;
3315 aarch64_insn_r
->reg_rec_count
= 1;
3318 return AARCH64_RECORD_UNKNOWN
;
3322 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3324 return AARCH64_RECORD_SUCCESS
;
3327 /* Record handler for data processing - immediate instructions. */
3330 aarch64_record_data_proc_imm (insn_decode_record
*aarch64_insn_r
)
3332 uint8_t reg_rd
, insn_bit23
, insn_bits24_27
, setflags
;
3333 uint32_t record_buf
[4];
3335 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3336 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3337 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3339 if (insn_bits24_27
== 0x00 /* PC rel addressing. */
3340 || insn_bits24_27
== 0x03 /* Bitfield and Extract. */
3341 || (insn_bits24_27
== 0x02 && insn_bit23
)) /* Move wide (immediate). */
3343 record_buf
[0] = reg_rd
;
3344 aarch64_insn_r
->reg_rec_count
= 1;
3346 else if (insn_bits24_27
== 0x01)
3348 /* Add/Subtract (immediate). */
3349 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3350 record_buf
[0] = reg_rd
;
3351 aarch64_insn_r
->reg_rec_count
= 1;
3353 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3355 else if (insn_bits24_27
== 0x02 && !insn_bit23
)
3357 /* Logical (immediate). */
3358 setflags
= bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03;
3359 record_buf
[0] = reg_rd
;
3360 aarch64_insn_r
->reg_rec_count
= 1;
3362 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3365 return AARCH64_RECORD_UNKNOWN
;
3367 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3369 return AARCH64_RECORD_SUCCESS
;
3372 /* Record handler for branch, exception generation and system instructions. */
3375 aarch64_record_branch_except_sys (insn_decode_record
*aarch64_insn_r
)
3377 struct gdbarch_tdep
*tdep
= gdbarch_tdep (aarch64_insn_r
->gdbarch
);
3378 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits22_23
;
3379 uint32_t record_buf
[4];
3381 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3382 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
3383 insn_bits22_23
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3385 if (insn_bits28_31
== 0x0d)
3387 /* Exception generation instructions. */
3388 if (insn_bits24_27
== 0x04)
3390 if (!bits (aarch64_insn_r
->aarch64_insn
, 2, 4)
3391 && !bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
3392 && bits (aarch64_insn_r
->aarch64_insn
, 0, 1) == 0x01)
3394 ULONGEST svc_number
;
3396 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, 8,
3398 return tdep
->aarch64_syscall_record (aarch64_insn_r
->regcache
,
3402 return AARCH64_RECORD_UNSUPPORTED
;
3404 /* System instructions. */
3405 else if (insn_bits24_27
== 0x05 && insn_bits22_23
== 0x00)
3407 uint32_t reg_rt
, reg_crn
;
3409 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3410 reg_crn
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3412 /* Record rt in case of sysl and mrs instructions. */
3413 if (bit (aarch64_insn_r
->aarch64_insn
, 21))
3415 record_buf
[0] = reg_rt
;
3416 aarch64_insn_r
->reg_rec_count
= 1;
3418 /* Record cpsr for hint and msr(immediate) instructions. */
3419 else if (reg_crn
== 0x02 || reg_crn
== 0x04)
3421 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3422 aarch64_insn_r
->reg_rec_count
= 1;
3425 /* Unconditional branch (register). */
3426 else if((insn_bits24_27
& 0x0e) == 0x06)
3428 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3429 if (bits (aarch64_insn_r
->aarch64_insn
, 21, 22) == 0x01)
3430 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3433 return AARCH64_RECORD_UNKNOWN
;
3435 /* Unconditional branch (immediate). */
3436 else if ((insn_bits28_31
& 0x07) == 0x01 && (insn_bits24_27
& 0x0c) == 0x04)
3438 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3439 if (bit (aarch64_insn_r
->aarch64_insn
, 31))
3440 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3443 /* Compare & branch (immediate), Test & branch (immediate) and
3444 Conditional branch (immediate). */
3445 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3447 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3449 return AARCH64_RECORD_SUCCESS
;
3452 /* Record handler for advanced SIMD load and store instructions. */
3455 aarch64_record_asimd_load_store (insn_decode_record
*aarch64_insn_r
)
3458 uint64_t addr_offset
= 0;
3459 uint32_t record_buf
[24];
3460 uint64_t record_buf_mem
[24];
3461 uint32_t reg_rn
, reg_rt
;
3462 uint32_t reg_index
= 0, mem_index
= 0;
3463 uint8_t opcode_bits
, size_bits
;
3465 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3466 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3467 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3468 opcode_bits
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3469 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
, &address
);
3472 debug_printf ("Process record: Advanced SIMD load/store\n");
3474 /* Load/store single structure. */
3475 if (bit (aarch64_insn_r
->aarch64_insn
, 24))
3477 uint8_t sindex
, scale
, selem
, esize
, replicate
= 0;
3478 scale
= opcode_bits
>> 2;
3479 selem
= ((opcode_bits
& 0x02) |
3480 bit (aarch64_insn_r
->aarch64_insn
, 21)) + 1;
3484 if (size_bits
& 0x01)
3485 return AARCH64_RECORD_UNKNOWN
;
3488 if ((size_bits
>> 1) & 0x01)
3489 return AARCH64_RECORD_UNKNOWN
;
3490 if (size_bits
& 0x01)
3492 if (!((opcode_bits
>> 1) & 0x01))
3495 return AARCH64_RECORD_UNKNOWN
;
3499 if (bit (aarch64_insn_r
->aarch64_insn
, 22) && !(opcode_bits
& 0x01))
3506 return AARCH64_RECORD_UNKNOWN
;
3512 for (sindex
= 0; sindex
< selem
; sindex
++)
3514 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3515 reg_rt
= (reg_rt
+ 1) % 32;
3519 for (sindex
= 0; sindex
< selem
; sindex
++)
3521 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3522 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3525 record_buf_mem
[mem_index
++] = esize
/ 8;
3526 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3528 addr_offset
= addr_offset
+ (esize
/ 8);
3529 reg_rt
= (reg_rt
+ 1) % 32;
3533 /* Load/store multiple structure. */
3536 uint8_t selem
, esize
, rpt
, elements
;
3537 uint8_t eindex
, rindex
;
3539 esize
= 8 << size_bits
;
3540 if (bit (aarch64_insn_r
->aarch64_insn
, 30))
3541 elements
= 128 / esize
;
3543 elements
= 64 / esize
;
3545 switch (opcode_bits
)
3547 /*LD/ST4 (4 Registers). */
3552 /*LD/ST1 (4 Registers). */
3557 /*LD/ST3 (3 Registers). */
3562 /*LD/ST1 (3 Registers). */
3567 /*LD/ST1 (1 Register). */
3572 /*LD/ST2 (2 Registers). */
3577 /*LD/ST1 (2 Registers). */
3583 return AARCH64_RECORD_UNSUPPORTED
;
3586 for (rindex
= 0; rindex
< rpt
; rindex
++)
3587 for (eindex
= 0; eindex
< elements
; eindex
++)
3589 uint8_t reg_tt
, sindex
;
3590 reg_tt
= (reg_rt
+ rindex
) % 32;
3591 for (sindex
= 0; sindex
< selem
; sindex
++)
3593 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3594 record_buf
[reg_index
++] = reg_tt
+ AARCH64_V0_REGNUM
;
3597 record_buf_mem
[mem_index
++] = esize
/ 8;
3598 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3600 addr_offset
= addr_offset
+ (esize
/ 8);
3601 reg_tt
= (reg_tt
+ 1) % 32;
3606 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
3607 record_buf
[reg_index
++] = reg_rn
;
3609 aarch64_insn_r
->reg_rec_count
= reg_index
;
3610 aarch64_insn_r
->mem_rec_count
= mem_index
/ 2;
3611 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
3613 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3615 return AARCH64_RECORD_SUCCESS
;
3618 /* Record handler for load and store instructions. */
3621 aarch64_record_load_store (insn_decode_record
*aarch64_insn_r
)
3623 uint8_t insn_bits24_27
, insn_bits28_29
, insn_bits10_11
;
3624 uint8_t insn_bit23
, insn_bit21
;
3625 uint8_t opc
, size_bits
, ld_flag
, vector_flag
;
3626 uint32_t reg_rn
, reg_rt
, reg_rt2
;
3627 uint64_t datasize
, offset
;
3628 uint32_t record_buf
[8];
3629 uint64_t record_buf_mem
[8];
3632 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3633 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3634 insn_bits28_29
= bits (aarch64_insn_r
->aarch64_insn
, 28, 29);
3635 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
3636 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3637 ld_flag
= bit (aarch64_insn_r
->aarch64_insn
, 22);
3638 vector_flag
= bit (aarch64_insn_r
->aarch64_insn
, 26);
3639 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3640 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3641 reg_rt2
= bits (aarch64_insn_r
->aarch64_insn
, 10, 14);
3642 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 30, 31);
3644 /* Load/store exclusive. */
3645 if (insn_bits24_27
== 0x08 && insn_bits28_29
== 0x00)
3648 debug_printf ("Process record: load/store exclusive\n");
3652 record_buf
[0] = reg_rt
;
3653 aarch64_insn_r
->reg_rec_count
= 1;
3656 record_buf
[1] = reg_rt2
;
3657 aarch64_insn_r
->reg_rec_count
= 2;
3663 datasize
= (8 << size_bits
) * 2;
3665 datasize
= (8 << size_bits
);
3666 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3668 record_buf_mem
[0] = datasize
/ 8;
3669 record_buf_mem
[1] = address
;
3670 aarch64_insn_r
->mem_rec_count
= 1;
3673 /* Save register rs. */
3674 record_buf
[0] = bits (aarch64_insn_r
->aarch64_insn
, 16, 20);
3675 aarch64_insn_r
->reg_rec_count
= 1;
3679 /* Load register (literal) instructions decoding. */
3680 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x01)
3683 debug_printf ("Process record: load register (literal)\n");
3685 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3687 record_buf
[0] = reg_rt
;
3688 aarch64_insn_r
->reg_rec_count
= 1;
3690 /* All types of load/store pair instructions decoding. */
3691 else if ((insn_bits24_27
& 0x0a) == 0x08 && insn_bits28_29
== 0x02)
3694 debug_printf ("Process record: load/store pair\n");
3700 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3701 record_buf
[1] = reg_rt2
+ AARCH64_V0_REGNUM
;
3705 record_buf
[0] = reg_rt
;
3706 record_buf
[1] = reg_rt2
;
3708 aarch64_insn_r
->reg_rec_count
= 2;
3713 imm7_off
= bits (aarch64_insn_r
->aarch64_insn
, 15, 21);
3715 size_bits
= size_bits
>> 1;
3716 datasize
= 8 << (2 + size_bits
);
3717 offset
= (imm7_off
& 0x40) ? (~imm7_off
& 0x007f) + 1 : imm7_off
;
3718 offset
= offset
<< (2 + size_bits
);
3719 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3721 if (!((insn_bits24_27
& 0x0b) == 0x08 && insn_bit23
))
3723 if (imm7_off
& 0x40)
3724 address
= address
- offset
;
3726 address
= address
+ offset
;
3729 record_buf_mem
[0] = datasize
/ 8;
3730 record_buf_mem
[1] = address
;
3731 record_buf_mem
[2] = datasize
/ 8;
3732 record_buf_mem
[3] = address
+ (datasize
/ 8);
3733 aarch64_insn_r
->mem_rec_count
= 2;
3735 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
3736 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
3738 /* Load/store register (unsigned immediate) instructions. */
3739 else if ((insn_bits24_27
& 0x0b) == 0x09 && insn_bits28_29
== 0x03)
3741 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3751 if (size_bits
== 0x3 && vector_flag
== 0x0 && opc
== 0x2)
3753 /* PRFM (immediate) */
3754 return AARCH64_RECORD_SUCCESS
;
3756 else if (size_bits
== 0x2 && vector_flag
== 0x0 && opc
== 0x2)
3758 /* LDRSW (immediate) */
3772 debug_printf ("Process record: load/store (unsigned immediate):"
3773 " size %x V %d opc %x\n", size_bits
, vector_flag
,
3779 offset
= bits (aarch64_insn_r
->aarch64_insn
, 10, 21);
3780 datasize
= 8 << size_bits
;
3781 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3783 offset
= offset
<< size_bits
;
3784 address
= address
+ offset
;
3786 record_buf_mem
[0] = datasize
>> 3;
3787 record_buf_mem
[1] = address
;
3788 aarch64_insn_r
->mem_rec_count
= 1;
3793 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3795 record_buf
[0] = reg_rt
;
3796 aarch64_insn_r
->reg_rec_count
= 1;
3799 /* Load/store register (register offset) instructions. */
3800 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
3801 && insn_bits10_11
== 0x02 && insn_bit21
)
3804 debug_printf ("Process record: load/store (register offset)\n");
3805 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3812 if (size_bits
!= 0x03)
3815 return AARCH64_RECORD_UNKNOWN
;
3819 ULONGEST reg_rm_val
;
3821 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
,
3822 bits (aarch64_insn_r
->aarch64_insn
, 16, 20), ®_rm_val
);
3823 if (bit (aarch64_insn_r
->aarch64_insn
, 12))
3824 offset
= reg_rm_val
<< size_bits
;
3826 offset
= reg_rm_val
;
3827 datasize
= 8 << size_bits
;
3828 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3830 address
= address
+ offset
;
3831 record_buf_mem
[0] = datasize
>> 3;
3832 record_buf_mem
[1] = address
;
3833 aarch64_insn_r
->mem_rec_count
= 1;
3838 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3840 record_buf
[0] = reg_rt
;
3841 aarch64_insn_r
->reg_rec_count
= 1;
3844 /* Load/store register (immediate and unprivileged) instructions. */
3845 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
3850 debug_printf ("Process record: load/store "
3851 "(immediate and unprivileged)\n");
3853 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3860 if (size_bits
!= 0x03)
3863 return AARCH64_RECORD_UNKNOWN
;
3868 imm9_off
= bits (aarch64_insn_r
->aarch64_insn
, 12, 20);
3869 offset
= (imm9_off
& 0x0100) ? (((~imm9_off
) & 0x01ff) + 1) : imm9_off
;
3870 datasize
= 8 << size_bits
;
3871 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3873 if (insn_bits10_11
!= 0x01)
3875 if (imm9_off
& 0x0100)
3876 address
= address
- offset
;
3878 address
= address
+ offset
;
3880 record_buf_mem
[0] = datasize
>> 3;
3881 record_buf_mem
[1] = address
;
3882 aarch64_insn_r
->mem_rec_count
= 1;
3887 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3889 record_buf
[0] = reg_rt
;
3890 aarch64_insn_r
->reg_rec_count
= 1;
3892 if (insn_bits10_11
== 0x01 || insn_bits10_11
== 0x03)
3893 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
3895 /* Advanced SIMD load/store instructions. */
3897 return aarch64_record_asimd_load_store (aarch64_insn_r
);
3899 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
3901 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3903 return AARCH64_RECORD_SUCCESS
;
3906 /* Record handler for data processing SIMD and floating point instructions. */
3909 aarch64_record_data_proc_simd_fp (insn_decode_record
*aarch64_insn_r
)
3911 uint8_t insn_bit21
, opcode
, rmode
, reg_rd
;
3912 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits10_11
, insn_bits12_15
;
3913 uint8_t insn_bits11_14
;
3914 uint32_t record_buf
[2];
3916 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3917 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
3918 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3919 insn_bits12_15
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3920 insn_bits11_14
= bits (aarch64_insn_r
->aarch64_insn
, 11, 14);
3921 opcode
= bits (aarch64_insn_r
->aarch64_insn
, 16, 18);
3922 rmode
= bits (aarch64_insn_r
->aarch64_insn
, 19, 20);
3923 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3924 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
3927 debug_printf ("Process record: data processing SIMD/FP: ");
3929 if ((insn_bits28_31
& 0x05) == 0x01 && insn_bits24_27
== 0x0e)
3931 /* Floating point - fixed point conversion instructions. */
3935 debug_printf ("FP - fixed point conversion");
3937 if ((opcode
>> 1) == 0x0 && rmode
== 0x03)
3938 record_buf
[0] = reg_rd
;
3940 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
3942 /* Floating point - conditional compare instructions. */
3943 else if (insn_bits10_11
== 0x01)
3946 debug_printf ("FP - conditional compare");
3948 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3950 /* Floating point - data processing (2-source) and
3951 conditional select instructions. */
3952 else if (insn_bits10_11
== 0x02 || insn_bits10_11
== 0x03)
3955 debug_printf ("FP - DP (2-source)");
3957 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
3959 else if (insn_bits10_11
== 0x00)
3961 /* Floating point - immediate instructions. */
3962 if ((insn_bits12_15
& 0x01) == 0x01
3963 || (insn_bits12_15
& 0x07) == 0x04)
3966 debug_printf ("FP - immediate");
3967 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
3969 /* Floating point - compare instructions. */
3970 else if ((insn_bits12_15
& 0x03) == 0x02)
3973 debug_printf ("FP - immediate");
3974 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3976 /* Floating point - integer conversions instructions. */
3977 else if (insn_bits12_15
== 0x00)
3979 /* Convert float to integer instruction. */
3980 if (!(opcode
>> 1) || ((opcode
>> 1) == 0x02 && !rmode
))
3983 debug_printf ("float to int conversion");
3985 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
3987 /* Convert integer to float instruction. */
3988 else if ((opcode
>> 1) == 0x01 && !rmode
)
3991 debug_printf ("int to float conversion");
3993 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
3995 /* Move float to integer instruction. */
3996 else if ((opcode
>> 1) == 0x03)
3999 debug_printf ("move float to int");
4001 if (!(opcode
& 0x01))
4002 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4004 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4007 return AARCH64_RECORD_UNKNOWN
;
4010 return AARCH64_RECORD_UNKNOWN
;
4013 return AARCH64_RECORD_UNKNOWN
;
4015 else if ((insn_bits28_31
& 0x09) == 0x00 && insn_bits24_27
== 0x0e)
4018 debug_printf ("SIMD copy");
4020 /* Advanced SIMD copy instructions. */
4021 if (!bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
4022 && !bit (aarch64_insn_r
->aarch64_insn
, 15)
4023 && bit (aarch64_insn_r
->aarch64_insn
, 10))
4025 if (insn_bits11_14
== 0x05 || insn_bits11_14
== 0x07)
4026 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4028 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4031 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4033 /* All remaining floating point or advanced SIMD instructions. */
4037 debug_printf ("all remain");
4039 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4043 debug_printf ("\n");
4045 aarch64_insn_r
->reg_rec_count
++;
4046 gdb_assert (aarch64_insn_r
->reg_rec_count
== 1);
4047 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4049 return AARCH64_RECORD_SUCCESS
;
4052 /* Decodes insns type and invokes its record handler. */
4055 aarch64_record_decode_insn_handler (insn_decode_record
*aarch64_insn_r
)
4057 uint32_t ins_bit25
, ins_bit26
, ins_bit27
, ins_bit28
;
4059 ins_bit25
= bit (aarch64_insn_r
->aarch64_insn
, 25);
4060 ins_bit26
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4061 ins_bit27
= bit (aarch64_insn_r
->aarch64_insn
, 27);
4062 ins_bit28
= bit (aarch64_insn_r
->aarch64_insn
, 28);
4064 /* Data processing - immediate instructions. */
4065 if (!ins_bit26
&& !ins_bit27
&& ins_bit28
)
4066 return aarch64_record_data_proc_imm (aarch64_insn_r
);
4068 /* Branch, exception generation and system instructions. */
4069 if (ins_bit26
&& !ins_bit27
&& ins_bit28
)
4070 return aarch64_record_branch_except_sys (aarch64_insn_r
);
4072 /* Load and store instructions. */
4073 if (!ins_bit25
&& ins_bit27
)
4074 return aarch64_record_load_store (aarch64_insn_r
);
4076 /* Data processing - register instructions. */
4077 if (ins_bit25
&& !ins_bit26
&& ins_bit27
)
4078 return aarch64_record_data_proc_reg (aarch64_insn_r
);
4080 /* Data processing - SIMD and floating point instructions. */
4081 if (ins_bit25
&& ins_bit26
&& ins_bit27
)
4082 return aarch64_record_data_proc_simd_fp (aarch64_insn_r
);
4084 return AARCH64_RECORD_UNSUPPORTED
;
4087 /* Cleans up local record registers and memory allocations. */
4090 deallocate_reg_mem (insn_decode_record
*record
)
4092 xfree (record
->aarch64_regs
);
4093 xfree (record
->aarch64_mems
);
4097 namespace selftests
{
4100 aarch64_process_record_test (void)
4102 struct gdbarch_info info
;
4105 gdbarch_info_init (&info
);
4106 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
4108 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
4109 SELF_CHECK (gdbarch
!= NULL
);
4111 insn_decode_record aarch64_record
;
4113 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4114 aarch64_record
.regcache
= NULL
;
4115 aarch64_record
.this_addr
= 0;
4116 aarch64_record
.gdbarch
= gdbarch
;
4118 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4119 aarch64_record
.aarch64_insn
= 0xf9800020;
4120 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4121 SELF_CHECK (ret
== AARCH64_RECORD_SUCCESS
);
4122 SELF_CHECK (aarch64_record
.reg_rec_count
== 0);
4123 SELF_CHECK (aarch64_record
.mem_rec_count
== 0);
4125 deallocate_reg_mem (&aarch64_record
);
4128 } // namespace selftests
4129 #endif /* GDB_SELF_TEST */
4131 /* Parse the current instruction and record the values of the registers and
4132 memory that will be changed in current instruction to record_arch_list
4133 return -1 if something is wrong. */
4136 aarch64_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4137 CORE_ADDR insn_addr
)
4139 uint32_t rec_no
= 0;
4140 uint8_t insn_size
= 4;
4142 gdb_byte buf
[insn_size
];
4143 insn_decode_record aarch64_record
;
4145 memset (&buf
[0], 0, insn_size
);
4146 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4147 target_read_memory (insn_addr
, &buf
[0], insn_size
);
4148 aarch64_record
.aarch64_insn
4149 = (uint32_t) extract_unsigned_integer (&buf
[0],
4151 gdbarch_byte_order (gdbarch
));
4152 aarch64_record
.regcache
= regcache
;
4153 aarch64_record
.this_addr
= insn_addr
;
4154 aarch64_record
.gdbarch
= gdbarch
;
4156 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4157 if (ret
== AARCH64_RECORD_UNSUPPORTED
)
4159 printf_unfiltered (_("Process record does not support instruction "
4160 "0x%0x at address %s.\n"),
4161 aarch64_record
.aarch64_insn
,
4162 paddress (gdbarch
, insn_addr
));
4168 /* Record registers. */
4169 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4171 /* Always record register CPSR. */
4172 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4173 AARCH64_CPSR_REGNUM
);
4174 if (aarch64_record
.aarch64_regs
)
4175 for (rec_no
= 0; rec_no
< aarch64_record
.reg_rec_count
; rec_no
++)
4176 if (record_full_arch_list_add_reg (aarch64_record
.regcache
,
4177 aarch64_record
.aarch64_regs
[rec_no
]))
4180 /* Record memories. */
4181 if (aarch64_record
.aarch64_mems
)
4182 for (rec_no
= 0; rec_no
< aarch64_record
.mem_rec_count
; rec_no
++)
4183 if (record_full_arch_list_add_mem
4184 ((CORE_ADDR
)aarch64_record
.aarch64_mems
[rec_no
].addr
,
4185 aarch64_record
.aarch64_mems
[rec_no
].len
))
4188 if (record_full_arch_list_add_end ())
4192 deallocate_reg_mem (&aarch64_record
);