1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
28 #include "reggroups.h"
30 #include "arch-utils.h"
32 #include "frame-unwind.h"
33 #include "frame-base.h"
34 #include "trad-frame.h"
37 #include "dwarf2/frame.h"
39 #include "prologue-value.h"
40 #include "target-descriptions.h"
41 #include "user-regs.h"
43 #include "gdbsupport/selftest.h"
45 #include "aarch64-tdep.h"
46 #include "aarch64-ravenscar-thread.h"
49 #include "record-full.h"
50 #include "arch/aarch64-insn.h"
53 #include "opcode/aarch64.h"
56 #define submask(x) ((1L << ((x) + 1)) - 1)
57 #define bit(obj,st) (((obj) >> (st)) & 1)
58 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
60 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
62 #define HA_MAX_NUM_FLDS 4
64 /* All possible aarch64 target descriptors. */
65 struct target_desc
*tdesc_aarch64_list
[AARCH64_MAX_SVE_VQ
+ 1][2/*pauth*/];
67 /* The standard register names, and all the valid aliases for them. */
70 const char *const name
;
72 } aarch64_register_aliases
[] =
74 /* 64-bit register names. */
75 {"fp", AARCH64_FP_REGNUM
},
76 {"lr", AARCH64_LR_REGNUM
},
77 {"sp", AARCH64_SP_REGNUM
},
79 /* 32-bit register names. */
80 {"w0", AARCH64_X0_REGNUM
+ 0},
81 {"w1", AARCH64_X0_REGNUM
+ 1},
82 {"w2", AARCH64_X0_REGNUM
+ 2},
83 {"w3", AARCH64_X0_REGNUM
+ 3},
84 {"w4", AARCH64_X0_REGNUM
+ 4},
85 {"w5", AARCH64_X0_REGNUM
+ 5},
86 {"w6", AARCH64_X0_REGNUM
+ 6},
87 {"w7", AARCH64_X0_REGNUM
+ 7},
88 {"w8", AARCH64_X0_REGNUM
+ 8},
89 {"w9", AARCH64_X0_REGNUM
+ 9},
90 {"w10", AARCH64_X0_REGNUM
+ 10},
91 {"w11", AARCH64_X0_REGNUM
+ 11},
92 {"w12", AARCH64_X0_REGNUM
+ 12},
93 {"w13", AARCH64_X0_REGNUM
+ 13},
94 {"w14", AARCH64_X0_REGNUM
+ 14},
95 {"w15", AARCH64_X0_REGNUM
+ 15},
96 {"w16", AARCH64_X0_REGNUM
+ 16},
97 {"w17", AARCH64_X0_REGNUM
+ 17},
98 {"w18", AARCH64_X0_REGNUM
+ 18},
99 {"w19", AARCH64_X0_REGNUM
+ 19},
100 {"w20", AARCH64_X0_REGNUM
+ 20},
101 {"w21", AARCH64_X0_REGNUM
+ 21},
102 {"w22", AARCH64_X0_REGNUM
+ 22},
103 {"w23", AARCH64_X0_REGNUM
+ 23},
104 {"w24", AARCH64_X0_REGNUM
+ 24},
105 {"w25", AARCH64_X0_REGNUM
+ 25},
106 {"w26", AARCH64_X0_REGNUM
+ 26},
107 {"w27", AARCH64_X0_REGNUM
+ 27},
108 {"w28", AARCH64_X0_REGNUM
+ 28},
109 {"w29", AARCH64_X0_REGNUM
+ 29},
110 {"w30", AARCH64_X0_REGNUM
+ 30},
113 {"ip0", AARCH64_X0_REGNUM
+ 16},
114 {"ip1", AARCH64_X0_REGNUM
+ 17}
117 /* The required core 'R' registers. */
118 static const char *const aarch64_r_register_names
[] =
120 /* These registers must appear in consecutive RAW register number
121 order and they must begin with AARCH64_X0_REGNUM! */
122 "x0", "x1", "x2", "x3",
123 "x4", "x5", "x6", "x7",
124 "x8", "x9", "x10", "x11",
125 "x12", "x13", "x14", "x15",
126 "x16", "x17", "x18", "x19",
127 "x20", "x21", "x22", "x23",
128 "x24", "x25", "x26", "x27",
129 "x28", "x29", "x30", "sp",
133 /* The FP/SIMD 'V' registers. */
134 static const char *const aarch64_v_register_names
[] =
136 /* These registers must appear in consecutive RAW register number
137 order and they must begin with AARCH64_V0_REGNUM! */
138 "v0", "v1", "v2", "v3",
139 "v4", "v5", "v6", "v7",
140 "v8", "v9", "v10", "v11",
141 "v12", "v13", "v14", "v15",
142 "v16", "v17", "v18", "v19",
143 "v20", "v21", "v22", "v23",
144 "v24", "v25", "v26", "v27",
145 "v28", "v29", "v30", "v31",
150 /* The SVE 'Z' and 'P' registers. */
151 static const char *const aarch64_sve_register_names
[] =
153 /* These registers must appear in consecutive RAW register number
154 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
155 "z0", "z1", "z2", "z3",
156 "z4", "z5", "z6", "z7",
157 "z8", "z9", "z10", "z11",
158 "z12", "z13", "z14", "z15",
159 "z16", "z17", "z18", "z19",
160 "z20", "z21", "z22", "z23",
161 "z24", "z25", "z26", "z27",
162 "z28", "z29", "z30", "z31",
164 "p0", "p1", "p2", "p3",
165 "p4", "p5", "p6", "p7",
166 "p8", "p9", "p10", "p11",
167 "p12", "p13", "p14", "p15",
171 static const char *const aarch64_pauth_register_names
[] =
173 /* Authentication mask for data pointer. */
175 /* Authentication mask for code pointer. */
179 /* AArch64 prologue cache structure. */
180 struct aarch64_prologue_cache
182 /* The program counter at the start of the function. It is used to
183 identify this frame as a prologue frame. */
186 /* The program counter at the time this frame was created; i.e. where
187 this function was called from. It is used to identify this frame as a
191 /* The stack pointer at the time this frame was created; i.e. the
192 caller's stack pointer when this function was called. It is used
193 to identify this frame. */
196 /* Is the target available to read from? */
199 /* The frame base for this frame is just prev_sp - frame size.
200 FRAMESIZE is the distance from the frame pointer to the
201 initial stack pointer. */
204 /* The register used to hold the frame pointer for this frame. */
207 /* Saved register offsets. */
208 struct trad_frame_saved_reg
*saved_regs
;
212 show_aarch64_debug (struct ui_file
*file
, int from_tty
,
213 struct cmd_list_element
*c
, const char *value
)
215 fprintf_filtered (file
, _("AArch64 debugging is %s.\n"), value
);
220 /* Abstract instruction reader. */
222 class abstract_instruction_reader
225 /* Read in one instruction. */
226 virtual ULONGEST
read (CORE_ADDR memaddr
, int len
,
227 enum bfd_endian byte_order
) = 0;
230 /* Instruction reader from real target. */
232 class instruction_reader
: public abstract_instruction_reader
235 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
238 return read_code_unsigned_integer (memaddr
, len
, byte_order
);
244 /* If address signing is enabled, mask off the signature bits from the link
245 register, which is passed by value in ADDR, using the register values in
249 aarch64_frame_unmask_lr (struct gdbarch_tdep
*tdep
,
250 struct frame_info
*this_frame
, CORE_ADDR addr
)
252 if (tdep
->has_pauth ()
253 && frame_unwind_register_unsigned (this_frame
,
254 tdep
->pauth_ra_state_regnum
))
256 int cmask_num
= AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
);
257 CORE_ADDR cmask
= frame_unwind_register_unsigned (this_frame
, cmask_num
);
258 addr
= addr
& ~cmask
;
260 /* Record in the frame that the link register required unmasking. */
261 set_frame_previous_pc_masked (this_frame
);
267 /* Implement the "get_pc_address_flags" gdbarch method. */
270 aarch64_get_pc_address_flags (frame_info
*frame
, CORE_ADDR pc
)
272 if (pc
!= 0 && get_frame_pc_masked (frame
))
278 /* Analyze a prologue, looking for a recognizable stack frame
279 and frame pointer. Scan until we encounter a store that could
280 clobber the stack frame unexpectedly, or an unknown instruction. */
283 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
284 CORE_ADDR start
, CORE_ADDR limit
,
285 struct aarch64_prologue_cache
*cache
,
286 abstract_instruction_reader
& reader
)
288 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
291 /* Whether the stack has been set. This should be true when we notice a SP
292 to FP move or if we are using the SP as the base register for storing
293 data, in case the FP is ommitted. */
294 bool seen_stack_set
= false;
296 /* Track X registers and D registers in prologue. */
297 pv_t regs
[AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
];
299 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
; i
++)
300 regs
[i
] = pv_register (i
, 0);
301 pv_area
stack (AARCH64_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
303 for (; start
< limit
; start
+= 4)
308 insn
= reader
.read (start
, 4, byte_order_for_code
);
310 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
313 if (inst
.opcode
->iclass
== addsub_imm
314 && (inst
.opcode
->op
== OP_ADD
315 || strcmp ("sub", inst
.opcode
->name
) == 0))
317 unsigned rd
= inst
.operands
[0].reg
.regno
;
318 unsigned rn
= inst
.operands
[1].reg
.regno
;
320 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 3);
321 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd_SP
);
322 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn_SP
);
323 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_AIMM
);
325 if (inst
.opcode
->op
== OP_ADD
)
327 regs
[rd
] = pv_add_constant (regs
[rn
],
328 inst
.operands
[2].imm
.value
);
332 regs
[rd
] = pv_add_constant (regs
[rn
],
333 -inst
.operands
[2].imm
.value
);
336 /* Did we move SP to FP? */
337 if (rn
== AARCH64_SP_REGNUM
&& rd
== AARCH64_FP_REGNUM
)
338 seen_stack_set
= true;
340 else if (inst
.opcode
->iclass
== pcreladdr
341 && inst
.operands
[1].type
== AARCH64_OPND_ADDR_ADRP
)
343 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
344 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
346 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
348 else if (inst
.opcode
->iclass
== branch_imm
)
350 /* Stop analysis on branch. */
353 else if (inst
.opcode
->iclass
== condbranch
)
355 /* Stop analysis on branch. */
358 else if (inst
.opcode
->iclass
== branch_reg
)
360 /* Stop analysis on branch. */
363 else if (inst
.opcode
->iclass
== compbranch
)
365 /* Stop analysis on branch. */
368 else if (inst
.opcode
->op
== OP_MOVZ
)
370 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
372 /* If this shows up before we set the stack, keep going. Otherwise
373 stop the analysis. */
377 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
379 else if (inst
.opcode
->iclass
== log_shift
380 && strcmp (inst
.opcode
->name
, "orr") == 0)
382 unsigned rd
= inst
.operands
[0].reg
.regno
;
383 unsigned rn
= inst
.operands
[1].reg
.regno
;
384 unsigned rm
= inst
.operands
[2].reg
.regno
;
386 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
387 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn
);
388 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_Rm_SFT
);
390 if (inst
.operands
[2].shifter
.amount
== 0
391 && rn
== AARCH64_SP_REGNUM
)
397 debug_printf ("aarch64: prologue analysis gave up "
398 "addr=%s opcode=0x%x (orr x register)\n",
399 core_addr_to_string_nz (start
), insn
);
404 else if (inst
.opcode
->op
== OP_STUR
)
406 unsigned rt
= inst
.operands
[0].reg
.regno
;
407 unsigned rn
= inst
.operands
[1].addr
.base_regno
;
408 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
410 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
411 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
);
412 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_ADDR_SIMM9
);
413 gdb_assert (!inst
.operands
[1].addr
.offset
.is_reg
);
416 (pv_add_constant (regs
[rn
], inst
.operands
[1].addr
.offset
.imm
),
419 /* Are we storing with SP as a base? */
420 if (rn
== AARCH64_SP_REGNUM
)
421 seen_stack_set
= true;
423 else if ((inst
.opcode
->iclass
== ldstpair_off
424 || (inst
.opcode
->iclass
== ldstpair_indexed
425 && inst
.operands
[2].addr
.preind
))
426 && strcmp ("stp", inst
.opcode
->name
) == 0)
428 /* STP with addressing mode Pre-indexed and Base register. */
431 unsigned rn
= inst
.operands
[2].addr
.base_regno
;
432 int32_t imm
= inst
.operands
[2].addr
.offset
.imm
;
433 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
435 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
436 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
437 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rt2
438 || inst
.operands
[1].type
== AARCH64_OPND_Ft2
);
439 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_ADDR_SIMM7
);
440 gdb_assert (!inst
.operands
[2].addr
.offset
.is_reg
);
442 /* If recording this store would invalidate the store area
443 (perhaps because rn is not known) then we should abandon
444 further prologue analysis. */
445 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
)))
448 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
+ 8)))
451 rt1
= inst
.operands
[0].reg
.regno
;
452 rt2
= inst
.operands
[1].reg
.regno
;
453 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
455 rt1
+= AARCH64_X_REGISTER_COUNT
;
456 rt2
+= AARCH64_X_REGISTER_COUNT
;
459 stack
.store (pv_add_constant (regs
[rn
], imm
), size
, regs
[rt1
]);
460 stack
.store (pv_add_constant (regs
[rn
], imm
+ size
), size
, regs
[rt2
]);
462 if (inst
.operands
[2].addr
.writeback
)
463 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
465 /* Ignore the instruction that allocates stack space and sets
467 if (rn
== AARCH64_SP_REGNUM
&& !inst
.operands
[2].addr
.writeback
)
468 seen_stack_set
= true;
470 else if ((inst
.opcode
->iclass
== ldst_imm9
/* Signed immediate. */
471 || (inst
.opcode
->iclass
== ldst_pos
/* Unsigned immediate. */
472 && (inst
.opcode
->op
== OP_STR_POS
473 || inst
.opcode
->op
== OP_STRF_POS
)))
474 && inst
.operands
[1].addr
.base_regno
== AARCH64_SP_REGNUM
475 && strcmp ("str", inst
.opcode
->name
) == 0)
477 /* STR (immediate) */
478 unsigned int rt
= inst
.operands
[0].reg
.regno
;
479 int32_t imm
= inst
.operands
[1].addr
.offset
.imm
;
480 unsigned int rn
= inst
.operands
[1].addr
.base_regno
;
481 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
482 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
483 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
485 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
486 rt
+= AARCH64_X_REGISTER_COUNT
;
488 stack
.store (pv_add_constant (regs
[rn
], imm
), size
, regs
[rt
]);
489 if (inst
.operands
[1].addr
.writeback
)
490 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
492 /* Are we storing with SP as a base? */
493 if (rn
== AARCH64_SP_REGNUM
)
494 seen_stack_set
= true;
496 else if (inst
.opcode
->iclass
== testbranch
)
498 /* Stop analysis on branch. */
501 else if (inst
.opcode
->iclass
== ic_system
)
503 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
504 int ra_state_val
= 0;
506 if (insn
== 0xd503233f /* paciasp. */
507 || insn
== 0xd503237f /* pacibsp. */)
509 /* Return addresses are mangled. */
512 else if (insn
== 0xd50323bf /* autiasp. */
513 || insn
== 0xd50323ff /* autibsp. */)
515 /* Return addresses are not mangled. */
521 debug_printf ("aarch64: prologue analysis gave up addr=%s"
522 " opcode=0x%x (iclass)\n",
523 core_addr_to_string_nz (start
), insn
);
527 if (tdep
->has_pauth () && cache
!= nullptr)
528 trad_frame_set_value (cache
->saved_regs
,
529 tdep
->pauth_ra_state_regnum
,
536 debug_printf ("aarch64: prologue analysis gave up addr=%s"
538 core_addr_to_string_nz (start
), insn
);
547 if (pv_is_register (regs
[AARCH64_FP_REGNUM
], AARCH64_SP_REGNUM
))
549 /* Frame pointer is fp. Frame size is constant. */
550 cache
->framereg
= AARCH64_FP_REGNUM
;
551 cache
->framesize
= -regs
[AARCH64_FP_REGNUM
].k
;
553 else if (pv_is_register (regs
[AARCH64_SP_REGNUM
], AARCH64_SP_REGNUM
))
555 /* Try the stack pointer. */
556 cache
->framesize
= -regs
[AARCH64_SP_REGNUM
].k
;
557 cache
->framereg
= AARCH64_SP_REGNUM
;
561 /* We're just out of luck. We don't know where the frame is. */
562 cache
->framereg
= -1;
563 cache
->framesize
= 0;
566 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
570 if (stack
.find_reg (gdbarch
, i
, &offset
))
571 cache
->saved_regs
[i
].addr
= offset
;
574 for (i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
576 int regnum
= gdbarch_num_regs (gdbarch
);
579 if (stack
.find_reg (gdbarch
, i
+ AARCH64_X_REGISTER_COUNT
,
581 cache
->saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
= offset
;
588 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
589 CORE_ADDR start
, CORE_ADDR limit
,
590 struct aarch64_prologue_cache
*cache
)
592 instruction_reader reader
;
594 return aarch64_analyze_prologue (gdbarch
, start
, limit
, cache
,
600 namespace selftests
{
602 /* Instruction reader from manually cooked instruction sequences. */
604 class instruction_reader_test
: public abstract_instruction_reader
607 template<size_t SIZE
>
608 explicit instruction_reader_test (const uint32_t (&insns
)[SIZE
])
609 : m_insns (insns
), m_insns_size (SIZE
)
612 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
615 SELF_CHECK (len
== 4);
616 SELF_CHECK (memaddr
% 4 == 0);
617 SELF_CHECK (memaddr
/ 4 < m_insns_size
);
619 return m_insns
[memaddr
/ 4];
623 const uint32_t *m_insns
;
628 aarch64_analyze_prologue_test (void)
630 struct gdbarch_info info
;
632 gdbarch_info_init (&info
);
633 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
635 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
636 SELF_CHECK (gdbarch
!= NULL
);
638 struct aarch64_prologue_cache cache
;
639 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
641 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
643 /* Test the simple prologue in which frame pointer is used. */
645 static const uint32_t insns
[] = {
646 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
647 0x910003fd, /* mov x29, sp */
648 0x97ffffe6, /* bl 0x400580 */
650 instruction_reader_test
reader (insns
);
652 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
653 SELF_CHECK (end
== 4 * 2);
655 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
656 SELF_CHECK (cache
.framesize
== 272);
658 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
660 if (i
== AARCH64_FP_REGNUM
)
661 SELF_CHECK (cache
.saved_regs
[i
].addr
== -272);
662 else if (i
== AARCH64_LR_REGNUM
)
663 SELF_CHECK (cache
.saved_regs
[i
].addr
== -264);
665 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
668 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
670 int regnum
= gdbarch_num_regs (gdbarch
);
672 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
677 /* Test a prologue in which STR is used and frame pointer is not
680 static const uint32_t insns
[] = {
681 0xf81d0ff3, /* str x19, [sp, #-48]! */
682 0xb9002fe0, /* str w0, [sp, #44] */
683 0xf90013e1, /* str x1, [sp, #32]*/
684 0xfd000fe0, /* str d0, [sp, #24] */
685 0xaa0203f3, /* mov x19, x2 */
686 0xf94013e0, /* ldr x0, [sp, #32] */
688 instruction_reader_test
reader (insns
);
690 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
691 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
693 SELF_CHECK (end
== 4 * 5);
695 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
696 SELF_CHECK (cache
.framesize
== 48);
698 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
701 SELF_CHECK (cache
.saved_regs
[i
].addr
== -16);
703 SELF_CHECK (cache
.saved_regs
[i
].addr
== -48);
705 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
708 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
710 int regnum
= gdbarch_num_regs (gdbarch
);
713 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
716 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
721 /* Test handling of movz before setting the frame pointer. */
723 static const uint32_t insns
[] = {
724 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
725 0x52800020, /* mov w0, #0x1 */
726 0x910003fd, /* mov x29, sp */
727 0x528000a2, /* mov w2, #0x5 */
728 0x97fffff8, /* bl 6e4 */
731 instruction_reader_test
reader (insns
);
733 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
734 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
736 /* We should stop at the 4th instruction. */
737 SELF_CHECK (end
== (4 - 1) * 4);
738 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
739 SELF_CHECK (cache
.framesize
== 16);
742 /* Test handling of movz/stp when using the stack pointer as frame
745 static const uint32_t insns
[] = {
746 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
747 0x52800020, /* mov w0, #0x1 */
748 0x290207e0, /* stp w0, w1, [sp, #16] */
749 0xa9018fe2, /* stp x2, x3, [sp, #24] */
750 0x528000a2, /* mov w2, #0x5 */
751 0x97fffff8, /* bl 6e4 */
754 instruction_reader_test
reader (insns
);
756 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
757 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
759 /* We should stop at the 5th instruction. */
760 SELF_CHECK (end
== (5 - 1) * 4);
761 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
762 SELF_CHECK (cache
.framesize
== 64);
765 /* Test handling of movz/str when using the stack pointer as frame
768 static const uint32_t insns
[] = {
769 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
770 0x52800020, /* mov w0, #0x1 */
771 0xb9002be4, /* str w4, [sp, #40] */
772 0xf9001be5, /* str x5, [sp, #48] */
773 0x528000a2, /* mov w2, #0x5 */
774 0x97fffff8, /* bl 6e4 */
777 instruction_reader_test
reader (insns
);
779 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
780 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
782 /* We should stop at the 5th instruction. */
783 SELF_CHECK (end
== (5 - 1) * 4);
784 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
785 SELF_CHECK (cache
.framesize
== 64);
788 /* Test handling of movz/stur when using the stack pointer as frame
791 static const uint32_t insns
[] = {
792 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
793 0x52800020, /* mov w0, #0x1 */
794 0xb80343e6, /* stur w6, [sp, #52] */
795 0xf80383e7, /* stur x7, [sp, #56] */
796 0x528000a2, /* mov w2, #0x5 */
797 0x97fffff8, /* bl 6e4 */
800 instruction_reader_test
reader (insns
);
802 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
803 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
805 /* We should stop at the 5th instruction. */
806 SELF_CHECK (end
== (5 - 1) * 4);
807 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
808 SELF_CHECK (cache
.framesize
== 64);
811 /* Test handling of movz when there is no frame pointer set or no stack
814 static const uint32_t insns
[] = {
815 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
816 0x52800020, /* mov w0, #0x1 */
817 0x528000a2, /* mov w2, #0x5 */
818 0x97fffff8, /* bl 6e4 */
821 instruction_reader_test
reader (insns
);
823 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
824 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
826 /* We should stop at the 4th instruction. */
827 SELF_CHECK (end
== (4 - 1) * 4);
828 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
829 SELF_CHECK (cache
.framesize
== 16);
832 /* Test a prologue in which there is a return address signing instruction. */
833 if (tdep
->has_pauth ())
835 static const uint32_t insns
[] = {
836 0xd503233f, /* paciasp */
837 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
838 0x910003fd, /* mov x29, sp */
839 0xf801c3f3, /* str x19, [sp, #28] */
840 0xb9401fa0, /* ldr x19, [x29, #28] */
842 instruction_reader_test
reader (insns
);
844 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
845 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
,
848 SELF_CHECK (end
== 4 * 4);
849 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
850 SELF_CHECK (cache
.framesize
== 48);
852 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
855 SELF_CHECK (cache
.saved_regs
[i
].addr
== -20);
856 else if (i
== AARCH64_FP_REGNUM
)
857 SELF_CHECK (cache
.saved_regs
[i
].addr
== -48);
858 else if (i
== AARCH64_LR_REGNUM
)
859 SELF_CHECK (cache
.saved_regs
[i
].addr
== -40);
861 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
864 if (tdep
->has_pauth ())
866 SELF_CHECK (trad_frame_value_p (cache
.saved_regs
,
867 tdep
->pauth_ra_state_regnum
));
868 SELF_CHECK (cache
.saved_regs
[tdep
->pauth_ra_state_regnum
].addr
== 1);
872 } // namespace selftests
873 #endif /* GDB_SELF_TEST */
875 /* Implement the "skip_prologue" gdbarch method. */
878 aarch64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
880 CORE_ADDR func_addr
, limit_pc
;
882 /* See if we can determine the end of the prologue via the symbol
883 table. If so, then return either PC, or the PC after the
884 prologue, whichever is greater. */
885 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
887 CORE_ADDR post_prologue_pc
888 = skip_prologue_using_sal (gdbarch
, func_addr
);
890 if (post_prologue_pc
!= 0)
891 return std::max (pc
, post_prologue_pc
);
894 /* Can't determine prologue from the symbol table, need to examine
897 /* Find an upper limit on the function prologue using the debug
898 information. If the debug information could not be used to
899 provide that bound, then use an arbitrary large number as the
901 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
903 limit_pc
= pc
+ 128; /* Magic. */
905 /* Try disassembling prologue. */
906 return aarch64_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
909 /* Scan the function prologue for THIS_FRAME and populate the prologue
913 aarch64_scan_prologue (struct frame_info
*this_frame
,
914 struct aarch64_prologue_cache
*cache
)
916 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
917 CORE_ADDR prologue_start
;
918 CORE_ADDR prologue_end
;
919 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
920 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
922 cache
->prev_pc
= prev_pc
;
924 /* Assume we do not find a frame. */
925 cache
->framereg
= -1;
926 cache
->framesize
= 0;
928 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
931 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
935 /* No line info so use the current PC. */
936 prologue_end
= prev_pc
;
938 else if (sal
.end
< prologue_end
)
940 /* The next line begins after the function end. */
941 prologue_end
= sal
.end
;
944 prologue_end
= std::min (prologue_end
, prev_pc
);
945 aarch64_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
951 frame_loc
= get_frame_register_unsigned (this_frame
, AARCH64_FP_REGNUM
);
955 cache
->framereg
= AARCH64_FP_REGNUM
;
956 cache
->framesize
= 16;
957 cache
->saved_regs
[29].addr
= 0;
958 cache
->saved_regs
[30].addr
= 8;
962 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
963 function may throw an exception if the inferior's registers or memory is
967 aarch64_make_prologue_cache_1 (struct frame_info
*this_frame
,
968 struct aarch64_prologue_cache
*cache
)
970 CORE_ADDR unwound_fp
;
973 aarch64_scan_prologue (this_frame
, cache
);
975 if (cache
->framereg
== -1)
978 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
982 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
984 /* Calculate actual addresses of saved registers using offsets
985 determined by aarch64_analyze_prologue. */
986 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
987 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
988 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
990 cache
->func
= get_frame_func (this_frame
);
992 cache
->available_p
= 1;
995 /* Allocate and fill in *THIS_CACHE with information about the prologue of
996 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
997 Return a pointer to the current aarch64_prologue_cache in
1000 static struct aarch64_prologue_cache
*
1001 aarch64_make_prologue_cache (struct frame_info
*this_frame
, void **this_cache
)
1003 struct aarch64_prologue_cache
*cache
;
1005 if (*this_cache
!= NULL
)
1006 return (struct aarch64_prologue_cache
*) *this_cache
;
1008 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
1009 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1010 *this_cache
= cache
;
1014 aarch64_make_prologue_cache_1 (this_frame
, cache
);
1016 catch (const gdb_exception_error
&ex
)
1018 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
1025 /* Implement the "stop_reason" frame_unwind method. */
1027 static enum unwind_stop_reason
1028 aarch64_prologue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1031 struct aarch64_prologue_cache
*cache
1032 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1034 if (!cache
->available_p
)
1035 return UNWIND_UNAVAILABLE
;
1037 /* Halt the backtrace at "_start". */
1038 if (cache
->prev_pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1039 return UNWIND_OUTERMOST
;
1041 /* We've hit a wall, stop. */
1042 if (cache
->prev_sp
== 0)
1043 return UNWIND_OUTERMOST
;
1045 return UNWIND_NO_REASON
;
1048 /* Our frame ID for a normal frame is the current function's starting
1049 PC and the caller's SP when we were called. */
1052 aarch64_prologue_this_id (struct frame_info
*this_frame
,
1053 void **this_cache
, struct frame_id
*this_id
)
1055 struct aarch64_prologue_cache
*cache
1056 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1058 if (!cache
->available_p
)
1059 *this_id
= frame_id_build_unavailable_stack (cache
->func
);
1061 *this_id
= frame_id_build (cache
->prev_sp
, cache
->func
);
1064 /* Implement the "prev_register" frame_unwind method. */
1066 static struct value
*
1067 aarch64_prologue_prev_register (struct frame_info
*this_frame
,
1068 void **this_cache
, int prev_regnum
)
1070 struct aarch64_prologue_cache
*cache
1071 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1073 /* If we are asked to unwind the PC, then we need to return the LR
1074 instead. The prologue may save PC, but it will point into this
1075 frame's prologue, not the next frame's resume location. */
1076 if (prev_regnum
== AARCH64_PC_REGNUM
)
1079 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1080 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1082 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1084 if (tdep
->has_pauth ()
1085 && trad_frame_value_p (cache
->saved_regs
,
1086 tdep
->pauth_ra_state_regnum
))
1087 lr
= aarch64_frame_unmask_lr (tdep
, this_frame
, lr
);
1089 return frame_unwind_got_constant (this_frame
, prev_regnum
, lr
);
1092 /* SP is generally not saved to the stack, but this frame is
1093 identified by the next frame's stack pointer at the time of the
1094 call. The value was already reconstructed into PREV_SP. */
1100 | | | <- Previous SP
1103 +--| saved fp |<- FP
1107 if (prev_regnum
== AARCH64_SP_REGNUM
)
1108 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1111 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1115 /* AArch64 prologue unwinder. */
1116 struct frame_unwind aarch64_prologue_unwind
=
1119 aarch64_prologue_frame_unwind_stop_reason
,
1120 aarch64_prologue_this_id
,
1121 aarch64_prologue_prev_register
,
1123 default_frame_sniffer
1126 /* Allocate and fill in *THIS_CACHE with information about the prologue of
1127 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
1128 Return a pointer to the current aarch64_prologue_cache in
1131 static struct aarch64_prologue_cache
*
1132 aarch64_make_stub_cache (struct frame_info
*this_frame
, void **this_cache
)
1134 struct aarch64_prologue_cache
*cache
;
1136 if (*this_cache
!= NULL
)
1137 return (struct aarch64_prologue_cache
*) *this_cache
;
1139 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
1140 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1141 *this_cache
= cache
;
1145 cache
->prev_sp
= get_frame_register_unsigned (this_frame
,
1147 cache
->prev_pc
= get_frame_pc (this_frame
);
1148 cache
->available_p
= 1;
1150 catch (const gdb_exception_error
&ex
)
1152 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
1159 /* Implement the "stop_reason" frame_unwind method. */
1161 static enum unwind_stop_reason
1162 aarch64_stub_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1165 struct aarch64_prologue_cache
*cache
1166 = aarch64_make_stub_cache (this_frame
, this_cache
);
1168 if (!cache
->available_p
)
1169 return UNWIND_UNAVAILABLE
;
1171 return UNWIND_NO_REASON
;
1174 /* Our frame ID for a stub frame is the current SP and LR. */
1177 aarch64_stub_this_id (struct frame_info
*this_frame
,
1178 void **this_cache
, struct frame_id
*this_id
)
1180 struct aarch64_prologue_cache
*cache
1181 = aarch64_make_stub_cache (this_frame
, this_cache
);
1183 if (cache
->available_p
)
1184 *this_id
= frame_id_build (cache
->prev_sp
, cache
->prev_pc
);
1186 *this_id
= frame_id_build_unavailable_stack (cache
->prev_pc
);
1189 /* Implement the "sniffer" frame_unwind method. */
1192 aarch64_stub_unwind_sniffer (const struct frame_unwind
*self
,
1193 struct frame_info
*this_frame
,
1194 void **this_prologue_cache
)
1196 CORE_ADDR addr_in_block
;
1199 addr_in_block
= get_frame_address_in_block (this_frame
);
1200 if (in_plt_section (addr_in_block
)
1201 /* We also use the stub winder if the target memory is unreadable
1202 to avoid having the prologue unwinder trying to read it. */
1203 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1209 /* AArch64 stub unwinder. */
1210 struct frame_unwind aarch64_stub_unwind
=
1213 aarch64_stub_frame_unwind_stop_reason
,
1214 aarch64_stub_this_id
,
1215 aarch64_prologue_prev_register
,
1217 aarch64_stub_unwind_sniffer
1220 /* Return the frame base address of *THIS_FRAME. */
1223 aarch64_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1225 struct aarch64_prologue_cache
*cache
1226 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1228 return cache
->prev_sp
- cache
->framesize
;
1231 /* AArch64 default frame base information. */
1232 struct frame_base aarch64_normal_base
=
1234 &aarch64_prologue_unwind
,
1235 aarch64_normal_frame_base
,
1236 aarch64_normal_frame_base
,
1237 aarch64_normal_frame_base
1240 /* Return the value of the REGNUM register in the previous frame of
1243 static struct value
*
1244 aarch64_dwarf2_prev_register (struct frame_info
*this_frame
,
1245 void **this_cache
, int regnum
)
1247 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1252 case AARCH64_PC_REGNUM
:
1253 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1254 lr
= aarch64_frame_unmask_lr (tdep
, this_frame
, lr
);
1255 return frame_unwind_got_constant (this_frame
, regnum
, lr
);
1258 internal_error (__FILE__
, __LINE__
,
1259 _("Unexpected register %d"), regnum
);
1263 static const unsigned char op_lit0
= DW_OP_lit0
;
1264 static const unsigned char op_lit1
= DW_OP_lit1
;
1266 /* Implement the "init_reg" dwarf2_frame_ops method. */
1269 aarch64_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1270 struct dwarf2_frame_state_reg
*reg
,
1271 struct frame_info
*this_frame
)
1273 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1277 case AARCH64_PC_REGNUM
:
1278 reg
->how
= DWARF2_FRAME_REG_FN
;
1279 reg
->loc
.fn
= aarch64_dwarf2_prev_register
;
1282 case AARCH64_SP_REGNUM
:
1283 reg
->how
= DWARF2_FRAME_REG_CFA
;
1287 /* Init pauth registers. */
1288 if (tdep
->has_pauth ())
1290 if (regnum
== tdep
->pauth_ra_state_regnum
)
1292 /* Initialize RA_STATE to zero. */
1293 reg
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1294 reg
->loc
.exp
.start
= &op_lit0
;
1295 reg
->loc
.exp
.len
= 1;
1298 else if (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
1299 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
))
1301 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1307 /* Implement the execute_dwarf_cfa_vendor_op method. */
1310 aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch
*gdbarch
, gdb_byte op
,
1311 struct dwarf2_frame_state
*fs
)
1313 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1314 struct dwarf2_frame_state_reg
*ra_state
;
1316 if (op
== DW_CFA_AARCH64_negate_ra_state
)
1318 /* On systems without pauth, treat as a nop. */
1319 if (!tdep
->has_pauth ())
1322 /* Allocate RA_STATE column if it's not allocated yet. */
1323 fs
->regs
.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE
+ 1);
1325 /* Toggle the status of RA_STATE between 0 and 1. */
1326 ra_state
= &(fs
->regs
.reg
[AARCH64_DWARF_PAUTH_RA_STATE
]);
1327 ra_state
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1329 if (ra_state
->loc
.exp
.start
== nullptr
1330 || ra_state
->loc
.exp
.start
== &op_lit0
)
1331 ra_state
->loc
.exp
.start
= &op_lit1
;
1333 ra_state
->loc
.exp
.start
= &op_lit0
;
1335 ra_state
->loc
.exp
.len
= 1;
1343 /* Used for matching BRK instructions for AArch64. */
1344 static constexpr uint32_t BRK_INSN_MASK
= 0xffe0001f;
1345 static constexpr uint32_t BRK_INSN_BASE
= 0xd4200000;
1347 /* Implementation of gdbarch_program_breakpoint_here_p for aarch64. */
1350 aarch64_program_breakpoint_here_p (gdbarch
*gdbarch
, CORE_ADDR address
)
1352 const uint32_t insn_len
= 4;
1353 gdb_byte target_mem
[4];
1355 /* Enable the automatic memory restoration from breakpoints while
1356 we read the memory. Otherwise we may find temporary breakpoints, ones
1357 inserted by GDB, and flag them as permanent breakpoints. */
1358 scoped_restore restore_memory
1359 = make_scoped_restore_show_memory_breakpoints (0);
1361 if (target_read_memory (address
, target_mem
, insn_len
) == 0)
1364 (uint32_t) extract_unsigned_integer (target_mem
, insn_len
,
1365 gdbarch_byte_order_for_code (gdbarch
));
1367 /* Check if INSN is a BRK instruction pattern. There are multiple choices
1368 of such instructions with different immediate values. Different OS'
1369 may use a different variation, but they have the same outcome. */
1370 return ((insn
& BRK_INSN_MASK
) == BRK_INSN_BASE
);
1376 /* When arguments must be pushed onto the stack, they go on in reverse
1377 order. The code below implements a FILO (stack) to do this. */
1381 /* Value to pass on stack. It can be NULL if this item is for stack
1383 const gdb_byte
*data
;
1385 /* Size in bytes of value to pass on stack. */
1389 /* Implement the gdbarch type alignment method, overrides the generic
1390 alignment algorithm for anything that is aarch64 specific. */
1393 aarch64_type_align (gdbarch
*gdbarch
, struct type
*t
)
1395 t
= check_typedef (t
);
1396 if (t
->code () == TYPE_CODE_ARRAY
&& t
->is_vector ())
1398 /* Use the natural alignment for vector types (the same for
1399 scalar type), but the maximum alignment is 128-bit. */
1400 if (TYPE_LENGTH (t
) > 16)
1403 return TYPE_LENGTH (t
);
1406 /* Allow the common code to calculate the alignment. */
1410 /* Worker function for aapcs_is_vfp_call_or_return_candidate.
1412 Return the number of register required, or -1 on failure.
1414 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1415 to the element, else fail if the type of this element does not match the
1419 aapcs_is_vfp_call_or_return_candidate_1 (struct type
*type
,
1420 struct type
**fundamental_type
)
1422 if (type
== nullptr)
1425 switch (type
->code ())
1428 if (TYPE_LENGTH (type
) > 16)
1431 if (*fundamental_type
== nullptr)
1432 *fundamental_type
= type
;
1433 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1434 || type
->code () != (*fundamental_type
)->code ())
1439 case TYPE_CODE_COMPLEX
:
1441 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
1442 if (TYPE_LENGTH (target_type
) > 16)
1445 if (*fundamental_type
== nullptr)
1446 *fundamental_type
= target_type
;
1447 else if (TYPE_LENGTH (target_type
) != TYPE_LENGTH (*fundamental_type
)
1448 || target_type
->code () != (*fundamental_type
)->code ())
1454 case TYPE_CODE_ARRAY
:
1456 if (type
->is_vector ())
1458 if (TYPE_LENGTH (type
) != 8 && TYPE_LENGTH (type
) != 16)
1461 if (*fundamental_type
== nullptr)
1462 *fundamental_type
= type
;
1463 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1464 || type
->code () != (*fundamental_type
)->code ())
1471 struct type
*target_type
= TYPE_TARGET_TYPE (type
);
1472 int count
= aapcs_is_vfp_call_or_return_candidate_1
1473 (target_type
, fundamental_type
);
1478 count
*= (TYPE_LENGTH (type
) / TYPE_LENGTH (target_type
));
1483 case TYPE_CODE_STRUCT
:
1484 case TYPE_CODE_UNION
:
1488 for (int i
= 0; i
< type
->num_fields (); i
++)
1490 /* Ignore any static fields. */
1491 if (field_is_static (&type
->field (i
)))
1494 struct type
*member
= check_typedef (type
->field (i
).type ());
1496 int sub_count
= aapcs_is_vfp_call_or_return_candidate_1
1497 (member
, fundamental_type
);
1498 if (sub_count
== -1)
1503 /* Ensure there is no padding between the fields (allowing for empty
1504 zero length structs) */
1505 int ftype_length
= (*fundamental_type
== nullptr)
1506 ? 0 : TYPE_LENGTH (*fundamental_type
);
1507 if (count
* ftype_length
!= TYPE_LENGTH (type
))
1520 /* Return true if an argument, whose type is described by TYPE, can be passed or
1521 returned in simd/fp registers, providing enough parameter passing registers
1522 are available. This is as described in the AAPCS64.
1524 Upon successful return, *COUNT returns the number of needed registers,
1525 *FUNDAMENTAL_TYPE contains the type of those registers.
1527 Candidate as per the AAPCS64 5.4.2.C is either a:
1530 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1531 all the members are floats and has at most 4 members.
1532 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1533 all the members are short vectors and has at most 4 members.
1536 Note that HFAs and HVAs can include nested structures and arrays. */
1539 aapcs_is_vfp_call_or_return_candidate (struct type
*type
, int *count
,
1540 struct type
**fundamental_type
)
1542 if (type
== nullptr)
1545 *fundamental_type
= nullptr;
1547 int ag_count
= aapcs_is_vfp_call_or_return_candidate_1 (type
,
1550 if (ag_count
> 0 && ag_count
<= HA_MAX_NUM_FLDS
)
1559 /* AArch64 function call information structure. */
1560 struct aarch64_call_info
1562 /* the current argument number. */
1563 unsigned argnum
= 0;
1565 /* The next general purpose register number, equivalent to NGRN as
1566 described in the AArch64 Procedure Call Standard. */
1569 /* The next SIMD and floating point register number, equivalent to
1570 NSRN as described in the AArch64 Procedure Call Standard. */
1573 /* The next stacked argument address, equivalent to NSAA as
1574 described in the AArch64 Procedure Call Standard. */
1577 /* Stack item vector. */
1578 std::vector
<stack_item_t
> si
;
1581 /* Pass a value in a sequence of consecutive X registers. The caller
1582 is responsible for ensuring sufficient registers are available. */
1585 pass_in_x (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1586 struct aarch64_call_info
*info
, struct type
*type
,
1589 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1590 int len
= TYPE_LENGTH (type
);
1591 enum type_code typecode
= type
->code ();
1592 int regnum
= AARCH64_X0_REGNUM
+ info
->ngrn
;
1593 const bfd_byte
*buf
= value_contents (arg
);
1599 int partial_len
= len
< X_REGISTER_SIZE
? len
: X_REGISTER_SIZE
;
1600 CORE_ADDR regval
= extract_unsigned_integer (buf
, partial_len
,
1604 /* Adjust sub-word struct/union args when big-endian. */
1605 if (byte_order
== BFD_ENDIAN_BIG
1606 && partial_len
< X_REGISTER_SIZE
1607 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1608 regval
<<= ((X_REGISTER_SIZE
- partial_len
) * TARGET_CHAR_BIT
);
1612 debug_printf ("arg %d in %s = 0x%s\n", info
->argnum
,
1613 gdbarch_register_name (gdbarch
, regnum
),
1614 phex (regval
, X_REGISTER_SIZE
));
1616 regcache_cooked_write_unsigned (regcache
, regnum
, regval
);
1623 /* Attempt to marshall a value in a V register. Return 1 if
1624 successful, or 0 if insufficient registers are available. This
1625 function, unlike the equivalent pass_in_x() function does not
1626 handle arguments spread across multiple registers. */
1629 pass_in_v (struct gdbarch
*gdbarch
,
1630 struct regcache
*regcache
,
1631 struct aarch64_call_info
*info
,
1632 int len
, const bfd_byte
*buf
)
1636 int regnum
= AARCH64_V0_REGNUM
+ info
->nsrn
;
1637 /* Enough space for a full vector register. */
1638 gdb_byte reg
[register_size (gdbarch
, regnum
)];
1639 gdb_assert (len
<= sizeof (reg
));
1644 memset (reg
, 0, sizeof (reg
));
1645 /* PCS C.1, the argument is allocated to the least significant
1646 bits of V register. */
1647 memcpy (reg
, buf
, len
);
1648 regcache
->cooked_write (regnum
, reg
);
1652 debug_printf ("arg %d in %s\n", info
->argnum
,
1653 gdbarch_register_name (gdbarch
, regnum
));
1661 /* Marshall an argument onto the stack. */
1664 pass_on_stack (struct aarch64_call_info
*info
, struct type
*type
,
1667 const bfd_byte
*buf
= value_contents (arg
);
1668 int len
= TYPE_LENGTH (type
);
1674 align
= type_align (type
);
1676 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1677 Natural alignment of the argument's type. */
1678 align
= align_up (align
, 8);
1680 /* The AArch64 PCS requires at most doubleword alignment. */
1686 debug_printf ("arg %d len=%d @ sp + %d\n", info
->argnum
, len
,
1692 info
->si
.push_back (item
);
1695 if (info
->nsaa
& (align
- 1))
1697 /* Push stack alignment padding. */
1698 int pad
= align
- (info
->nsaa
& (align
- 1));
1703 info
->si
.push_back (item
);
1708 /* Marshall an argument into a sequence of one or more consecutive X
1709 registers or, if insufficient X registers are available then onto
1713 pass_in_x_or_stack (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1714 struct aarch64_call_info
*info
, struct type
*type
,
1717 int len
= TYPE_LENGTH (type
);
1718 int nregs
= (len
+ X_REGISTER_SIZE
- 1) / X_REGISTER_SIZE
;
1720 /* PCS C.13 - Pass in registers if we have enough spare */
1721 if (info
->ngrn
+ nregs
<= 8)
1723 pass_in_x (gdbarch
, regcache
, info
, type
, arg
);
1724 info
->ngrn
+= nregs
;
1729 pass_on_stack (info
, type
, arg
);
1733 /* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1734 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1735 registers. A return value of false is an error state as the value will have
1736 been partially passed to the stack. */
1738 pass_in_v_vfp_candidate (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1739 struct aarch64_call_info
*info
, struct type
*arg_type
,
1742 switch (arg_type
->code ())
1745 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1746 value_contents (arg
));
1749 case TYPE_CODE_COMPLEX
:
1751 const bfd_byte
*buf
= value_contents (arg
);
1752 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (arg_type
));
1754 if (!pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1758 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1759 buf
+ TYPE_LENGTH (target_type
));
1762 case TYPE_CODE_ARRAY
:
1763 if (arg_type
->is_vector ())
1764 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1765 value_contents (arg
));
1768 case TYPE_CODE_STRUCT
:
1769 case TYPE_CODE_UNION
:
1770 for (int i
= 0; i
< arg_type
->num_fields (); i
++)
1772 /* Don't include static fields. */
1773 if (field_is_static (&arg_type
->field (i
)))
1776 struct value
*field
= value_primitive_field (arg
, 0, i
, arg_type
);
1777 struct type
*field_type
= check_typedef (value_type (field
));
1779 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, info
, field_type
,
1790 /* Implement the "push_dummy_call" gdbarch method. */
1793 aarch64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1794 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1796 struct value
**args
, CORE_ADDR sp
,
1797 function_call_return_method return_method
,
1798 CORE_ADDR struct_addr
)
1801 struct aarch64_call_info info
;
1803 /* We need to know what the type of the called function is in order
1804 to determine the number of named/anonymous arguments for the
1805 actual argument placement, and the return type in order to handle
1806 return value correctly.
1808 The generic code above us views the decision of return in memory
1809 or return in registers as a two stage processes. The language
1810 handler is consulted first and may decide to return in memory (eg
1811 class with copy constructor returned by value), this will cause
1812 the generic code to allocate space AND insert an initial leading
1815 If the language code does not decide to pass in memory then the
1816 target code is consulted.
1818 If the language code decides to pass in memory we want to move
1819 the pointer inserted as the initial argument from the argument
1820 list and into X8, the conventional AArch64 struct return pointer
1823 /* Set the return address. For the AArch64, the return breakpoint
1824 is always at BP_ADDR. */
1825 regcache_cooked_write_unsigned (regcache
, AARCH64_LR_REGNUM
, bp_addr
);
1827 /* If we were given an initial argument for the return slot, lose it. */
1828 if (return_method
== return_method_hidden_param
)
1834 /* The struct_return pointer occupies X8. */
1835 if (return_method
!= return_method_normal
)
1839 debug_printf ("struct return in %s = 0x%s\n",
1840 gdbarch_register_name (gdbarch
,
1841 AARCH64_STRUCT_RETURN_REGNUM
),
1842 paddress (gdbarch
, struct_addr
));
1844 regcache_cooked_write_unsigned (regcache
, AARCH64_STRUCT_RETURN_REGNUM
,
1848 for (argnum
= 0; argnum
< nargs
; argnum
++)
1850 struct value
*arg
= args
[argnum
];
1851 struct type
*arg_type
, *fundamental_type
;
1854 arg_type
= check_typedef (value_type (arg
));
1855 len
= TYPE_LENGTH (arg_type
);
1857 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1858 if there are enough spare registers. */
1859 if (aapcs_is_vfp_call_or_return_candidate (arg_type
, &elements
,
1862 if (info
.nsrn
+ elements
<= 8)
1864 /* We know that we have sufficient registers available therefore
1865 this will never need to fallback to the stack. */
1866 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, &info
, arg_type
,
1868 gdb_assert_not_reached ("Failed to push args");
1873 pass_on_stack (&info
, arg_type
, arg
);
1878 switch (arg_type
->code ())
1881 case TYPE_CODE_BOOL
:
1882 case TYPE_CODE_CHAR
:
1883 case TYPE_CODE_RANGE
:
1884 case TYPE_CODE_ENUM
:
1887 /* Promote to 32 bit integer. */
1888 if (arg_type
->is_unsigned ())
1889 arg_type
= builtin_type (gdbarch
)->builtin_uint32
;
1891 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
1892 arg
= value_cast (arg_type
, arg
);
1894 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1897 case TYPE_CODE_STRUCT
:
1898 case TYPE_CODE_ARRAY
:
1899 case TYPE_CODE_UNION
:
1902 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1903 invisible reference. */
1905 /* Allocate aligned storage. */
1906 sp
= align_down (sp
- len
, 16);
1908 /* Write the real data into the stack. */
1909 write_memory (sp
, value_contents (arg
), len
);
1911 /* Construct the indirection. */
1912 arg_type
= lookup_pointer_type (arg_type
);
1913 arg
= value_from_pointer (arg_type
, sp
);
1914 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1917 /* PCS C.15 / C.18 multiple values pass. */
1918 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1922 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1927 /* Make sure stack retains 16 byte alignment. */
1929 sp
-= 16 - (info
.nsaa
& 15);
1931 while (!info
.si
.empty ())
1933 const stack_item_t
&si
= info
.si
.back ();
1936 if (si
.data
!= NULL
)
1937 write_memory (sp
, si
.data
, si
.len
);
1938 info
.si
.pop_back ();
1941 /* Finally, update the SP register. */
1942 regcache_cooked_write_unsigned (regcache
, AARCH64_SP_REGNUM
, sp
);
1947 /* Implement the "frame_align" gdbarch method. */
1950 aarch64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1952 /* Align the stack to sixteen bytes. */
1953 return sp
& ~(CORE_ADDR
) 15;
1956 /* Return the type for an AdvSISD Q register. */
1958 static struct type
*
1959 aarch64_vnq_type (struct gdbarch
*gdbarch
)
1961 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1963 if (tdep
->vnq_type
== NULL
)
1968 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1971 elem
= builtin_type (gdbarch
)->builtin_uint128
;
1972 append_composite_type_field (t
, "u", elem
);
1974 elem
= builtin_type (gdbarch
)->builtin_int128
;
1975 append_composite_type_field (t
, "s", elem
);
1980 return tdep
->vnq_type
;
1983 /* Return the type for an AdvSISD D register. */
1985 static struct type
*
1986 aarch64_vnd_type (struct gdbarch
*gdbarch
)
1988 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1990 if (tdep
->vnd_type
== NULL
)
1995 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1998 elem
= builtin_type (gdbarch
)->builtin_double
;
1999 append_composite_type_field (t
, "f", elem
);
2001 elem
= builtin_type (gdbarch
)->builtin_uint64
;
2002 append_composite_type_field (t
, "u", elem
);
2004 elem
= builtin_type (gdbarch
)->builtin_int64
;
2005 append_composite_type_field (t
, "s", elem
);
2010 return tdep
->vnd_type
;
2013 /* Return the type for an AdvSISD S register. */
2015 static struct type
*
2016 aarch64_vns_type (struct gdbarch
*gdbarch
)
2018 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2020 if (tdep
->vns_type
== NULL
)
2025 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
2028 elem
= builtin_type (gdbarch
)->builtin_float
;
2029 append_composite_type_field (t
, "f", elem
);
2031 elem
= builtin_type (gdbarch
)->builtin_uint32
;
2032 append_composite_type_field (t
, "u", elem
);
2034 elem
= builtin_type (gdbarch
)->builtin_int32
;
2035 append_composite_type_field (t
, "s", elem
);
2040 return tdep
->vns_type
;
2043 /* Return the type for an AdvSISD H register. */
2045 static struct type
*
2046 aarch64_vnh_type (struct gdbarch
*gdbarch
)
2048 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2050 if (tdep
->vnh_type
== NULL
)
2055 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
2058 elem
= builtin_type (gdbarch
)->builtin_half
;
2059 append_composite_type_field (t
, "f", elem
);
2061 elem
= builtin_type (gdbarch
)->builtin_uint16
;
2062 append_composite_type_field (t
, "u", elem
);
2064 elem
= builtin_type (gdbarch
)->builtin_int16
;
2065 append_composite_type_field (t
, "s", elem
);
2070 return tdep
->vnh_type
;
2073 /* Return the type for an AdvSISD B register. */
2075 static struct type
*
2076 aarch64_vnb_type (struct gdbarch
*gdbarch
)
2078 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2080 if (tdep
->vnb_type
== NULL
)
2085 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
2088 elem
= builtin_type (gdbarch
)->builtin_uint8
;
2089 append_composite_type_field (t
, "u", elem
);
2091 elem
= builtin_type (gdbarch
)->builtin_int8
;
2092 append_composite_type_field (t
, "s", elem
);
2097 return tdep
->vnb_type
;
2100 /* Return the type for an AdvSISD V register. */
2102 static struct type
*
2103 aarch64_vnv_type (struct gdbarch
*gdbarch
)
2105 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2107 if (tdep
->vnv_type
== NULL
)
2109 /* The other AArch64 pseudo registers (Q,D,H,S,B) refer to a single value
2110 slice from the non-pseudo vector registers. However NEON V registers
2111 are always vector registers, and need constructing as such. */
2112 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2114 struct type
*t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnv",
2117 struct type
*sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
2119 append_composite_type_field (sub
, "f",
2120 init_vector_type (bt
->builtin_double
, 2));
2121 append_composite_type_field (sub
, "u",
2122 init_vector_type (bt
->builtin_uint64
, 2));
2123 append_composite_type_field (sub
, "s",
2124 init_vector_type (bt
->builtin_int64
, 2));
2125 append_composite_type_field (t
, "d", sub
);
2127 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
2129 append_composite_type_field (sub
, "f",
2130 init_vector_type (bt
->builtin_float
, 4));
2131 append_composite_type_field (sub
, "u",
2132 init_vector_type (bt
->builtin_uint32
, 4));
2133 append_composite_type_field (sub
, "s",
2134 init_vector_type (bt
->builtin_int32
, 4));
2135 append_composite_type_field (t
, "s", sub
);
2137 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
2139 append_composite_type_field (sub
, "f",
2140 init_vector_type (bt
->builtin_half
, 8));
2141 append_composite_type_field (sub
, "u",
2142 init_vector_type (bt
->builtin_uint16
, 8));
2143 append_composite_type_field (sub
, "s",
2144 init_vector_type (bt
->builtin_int16
, 8));
2145 append_composite_type_field (t
, "h", sub
);
2147 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
2149 append_composite_type_field (sub
, "u",
2150 init_vector_type (bt
->builtin_uint8
, 16));
2151 append_composite_type_field (sub
, "s",
2152 init_vector_type (bt
->builtin_int8
, 16));
2153 append_composite_type_field (t
, "b", sub
);
2155 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
2157 append_composite_type_field (sub
, "u",
2158 init_vector_type (bt
->builtin_uint128
, 1));
2159 append_composite_type_field (sub
, "s",
2160 init_vector_type (bt
->builtin_int128
, 1));
2161 append_composite_type_field (t
, "q", sub
);
2166 return tdep
->vnv_type
;
2169 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
2172 aarch64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
2174 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2176 if (reg
>= AARCH64_DWARF_X0
&& reg
<= AARCH64_DWARF_X0
+ 30)
2177 return AARCH64_X0_REGNUM
+ reg
- AARCH64_DWARF_X0
;
2179 if (reg
== AARCH64_DWARF_SP
)
2180 return AARCH64_SP_REGNUM
;
2182 if (reg
>= AARCH64_DWARF_V0
&& reg
<= AARCH64_DWARF_V0
+ 31)
2183 return AARCH64_V0_REGNUM
+ reg
- AARCH64_DWARF_V0
;
2185 if (reg
== AARCH64_DWARF_SVE_VG
)
2186 return AARCH64_SVE_VG_REGNUM
;
2188 if (reg
== AARCH64_DWARF_SVE_FFR
)
2189 return AARCH64_SVE_FFR_REGNUM
;
2191 if (reg
>= AARCH64_DWARF_SVE_P0
&& reg
<= AARCH64_DWARF_SVE_P0
+ 15)
2192 return AARCH64_SVE_P0_REGNUM
+ reg
- AARCH64_DWARF_SVE_P0
;
2194 if (reg
>= AARCH64_DWARF_SVE_Z0
&& reg
<= AARCH64_DWARF_SVE_Z0
+ 15)
2195 return AARCH64_SVE_Z0_REGNUM
+ reg
- AARCH64_DWARF_SVE_Z0
;
2197 if (tdep
->has_pauth ())
2199 if (reg
>= AARCH64_DWARF_PAUTH_DMASK
&& reg
<= AARCH64_DWARF_PAUTH_CMASK
)
2200 return tdep
->pauth_reg_base
+ reg
- AARCH64_DWARF_PAUTH_DMASK
;
2202 if (reg
== AARCH64_DWARF_PAUTH_RA_STATE
)
2203 return tdep
->pauth_ra_state_regnum
;
2209 /* Implement the "print_insn" gdbarch method. */
2212 aarch64_gdb_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
2214 info
->symbols
= NULL
;
2215 return default_print_insn (memaddr
, info
);
2218 /* AArch64 BRK software debug mode instruction.
2219 Note that AArch64 code is always little-endian.
2220 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
2221 constexpr gdb_byte aarch64_default_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
2223 typedef BP_MANIPULATION (aarch64_default_breakpoint
) aarch64_breakpoint
;
2225 /* Extract from an array REGS containing the (raw) register state a
2226 function return value of type TYPE, and copy that, in virtual
2227 format, into VALBUF. */
2230 aarch64_extract_return_value (struct type
*type
, struct regcache
*regs
,
2233 struct gdbarch
*gdbarch
= regs
->arch ();
2234 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2236 struct type
*fundamental_type
;
2238 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2241 int len
= TYPE_LENGTH (fundamental_type
);
2243 for (int i
= 0; i
< elements
; i
++)
2245 int regno
= AARCH64_V0_REGNUM
+ i
;
2246 /* Enough space for a full vector register. */
2247 gdb_byte buf
[register_size (gdbarch
, regno
)];
2248 gdb_assert (len
<= sizeof (buf
));
2252 debug_printf ("read HFA or HVA return value element %d from %s\n",
2254 gdbarch_register_name (gdbarch
, regno
));
2256 regs
->cooked_read (regno
, buf
);
2258 memcpy (valbuf
, buf
, len
);
2262 else if (type
->code () == TYPE_CODE_INT
2263 || type
->code () == TYPE_CODE_CHAR
2264 || type
->code () == TYPE_CODE_BOOL
2265 || type
->code () == TYPE_CODE_PTR
2266 || TYPE_IS_REFERENCE (type
)
2267 || type
->code () == TYPE_CODE_ENUM
)
2269 /* If the type is a plain integer, then the access is
2270 straight-forward. Otherwise we have to play around a bit
2272 int len
= TYPE_LENGTH (type
);
2273 int regno
= AARCH64_X0_REGNUM
;
2278 /* By using store_unsigned_integer we avoid having to do
2279 anything special for small big-endian values. */
2280 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2281 store_unsigned_integer (valbuf
,
2282 (len
> X_REGISTER_SIZE
2283 ? X_REGISTER_SIZE
: len
), byte_order
, tmp
);
2284 len
-= X_REGISTER_SIZE
;
2285 valbuf
+= X_REGISTER_SIZE
;
2290 /* For a structure or union the behaviour is as if the value had
2291 been stored to word-aligned memory and then loaded into
2292 registers with 64-bit load instruction(s). */
2293 int len
= TYPE_LENGTH (type
);
2294 int regno
= AARCH64_X0_REGNUM
;
2295 bfd_byte buf
[X_REGISTER_SIZE
];
2299 regs
->cooked_read (regno
++, buf
);
2300 memcpy (valbuf
, buf
, len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2301 len
-= X_REGISTER_SIZE
;
2302 valbuf
+= X_REGISTER_SIZE
;
2308 /* Will a function return an aggregate type in memory or in a
2309 register? Return 0 if an aggregate type can be returned in a
2310 register, 1 if it must be returned in memory. */
2313 aarch64_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2315 type
= check_typedef (type
);
2317 struct type
*fundamental_type
;
2319 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2322 /* v0-v7 are used to return values and one register is allocated
2323 for one member. However, HFA or HVA has at most four members. */
2327 if (TYPE_LENGTH (type
) > 16)
2329 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2330 invisible reference. */
2338 /* Write into appropriate registers a function return value of type
2339 TYPE, given in virtual format. */
2342 aarch64_store_return_value (struct type
*type
, struct regcache
*regs
,
2343 const gdb_byte
*valbuf
)
2345 struct gdbarch
*gdbarch
= regs
->arch ();
2346 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2348 struct type
*fundamental_type
;
2350 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2353 int len
= TYPE_LENGTH (fundamental_type
);
2355 for (int i
= 0; i
< elements
; i
++)
2357 int regno
= AARCH64_V0_REGNUM
+ i
;
2358 /* Enough space for a full vector register. */
2359 gdb_byte tmpbuf
[register_size (gdbarch
, regno
)];
2360 gdb_assert (len
<= sizeof (tmpbuf
));
2364 debug_printf ("write HFA or HVA return value element %d to %s\n",
2366 gdbarch_register_name (gdbarch
, regno
));
2369 memcpy (tmpbuf
, valbuf
,
2370 len
> V_REGISTER_SIZE
? V_REGISTER_SIZE
: len
);
2371 regs
->cooked_write (regno
, tmpbuf
);
2375 else if (type
->code () == TYPE_CODE_INT
2376 || type
->code () == TYPE_CODE_CHAR
2377 || type
->code () == TYPE_CODE_BOOL
2378 || type
->code () == TYPE_CODE_PTR
2379 || TYPE_IS_REFERENCE (type
)
2380 || type
->code () == TYPE_CODE_ENUM
)
2382 if (TYPE_LENGTH (type
) <= X_REGISTER_SIZE
)
2384 /* Values of one word or less are zero/sign-extended and
2386 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2387 LONGEST val
= unpack_long (type
, valbuf
);
2389 store_signed_integer (tmpbuf
, X_REGISTER_SIZE
, byte_order
, val
);
2390 regs
->cooked_write (AARCH64_X0_REGNUM
, tmpbuf
);
2394 /* Integral values greater than one word are stored in
2395 consecutive registers starting with r0. This will always
2396 be a multiple of the regiser size. */
2397 int len
= TYPE_LENGTH (type
);
2398 int regno
= AARCH64_X0_REGNUM
;
2402 regs
->cooked_write (regno
++, valbuf
);
2403 len
-= X_REGISTER_SIZE
;
2404 valbuf
+= X_REGISTER_SIZE
;
2410 /* For a structure or union the behaviour is as if the value had
2411 been stored to word-aligned memory and then loaded into
2412 registers with 64-bit load instruction(s). */
2413 int len
= TYPE_LENGTH (type
);
2414 int regno
= AARCH64_X0_REGNUM
;
2415 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2419 memcpy (tmpbuf
, valbuf
,
2420 len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2421 regs
->cooked_write (regno
++, tmpbuf
);
2422 len
-= X_REGISTER_SIZE
;
2423 valbuf
+= X_REGISTER_SIZE
;
2428 /* Implement the "return_value" gdbarch method. */
2430 static enum return_value_convention
2431 aarch64_return_value (struct gdbarch
*gdbarch
, struct value
*func_value
,
2432 struct type
*valtype
, struct regcache
*regcache
,
2433 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2436 if (valtype
->code () == TYPE_CODE_STRUCT
2437 || valtype
->code () == TYPE_CODE_UNION
2438 || valtype
->code () == TYPE_CODE_ARRAY
)
2440 if (aarch64_return_in_memory (gdbarch
, valtype
))
2443 debug_printf ("return value in memory\n");
2444 return RETURN_VALUE_STRUCT_CONVENTION
;
2449 aarch64_store_return_value (valtype
, regcache
, writebuf
);
2452 aarch64_extract_return_value (valtype
, regcache
, readbuf
);
2455 debug_printf ("return value in registers\n");
2457 return RETURN_VALUE_REGISTER_CONVENTION
;
2460 /* Implement the "get_longjmp_target" gdbarch method. */
2463 aarch64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2466 gdb_byte buf
[X_REGISTER_SIZE
];
2467 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2468 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2469 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2471 jb_addr
= get_frame_register_unsigned (frame
, AARCH64_X0_REGNUM
);
2473 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2477 *pc
= extract_unsigned_integer (buf
, X_REGISTER_SIZE
, byte_order
);
2481 /* Implement the "gen_return_address" gdbarch method. */
2484 aarch64_gen_return_address (struct gdbarch
*gdbarch
,
2485 struct agent_expr
*ax
, struct axs_value
*value
,
2488 value
->type
= register_type (gdbarch
, AARCH64_LR_REGNUM
);
2489 value
->kind
= axs_lvalue_register
;
2490 value
->u
.reg
= AARCH64_LR_REGNUM
;
2494 /* Return the pseudo register name corresponding to register regnum. */
2497 aarch64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
2499 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2501 static const char *const q_name
[] =
2503 "q0", "q1", "q2", "q3",
2504 "q4", "q5", "q6", "q7",
2505 "q8", "q9", "q10", "q11",
2506 "q12", "q13", "q14", "q15",
2507 "q16", "q17", "q18", "q19",
2508 "q20", "q21", "q22", "q23",
2509 "q24", "q25", "q26", "q27",
2510 "q28", "q29", "q30", "q31",
2513 static const char *const d_name
[] =
2515 "d0", "d1", "d2", "d3",
2516 "d4", "d5", "d6", "d7",
2517 "d8", "d9", "d10", "d11",
2518 "d12", "d13", "d14", "d15",
2519 "d16", "d17", "d18", "d19",
2520 "d20", "d21", "d22", "d23",
2521 "d24", "d25", "d26", "d27",
2522 "d28", "d29", "d30", "d31",
2525 static const char *const s_name
[] =
2527 "s0", "s1", "s2", "s3",
2528 "s4", "s5", "s6", "s7",
2529 "s8", "s9", "s10", "s11",
2530 "s12", "s13", "s14", "s15",
2531 "s16", "s17", "s18", "s19",
2532 "s20", "s21", "s22", "s23",
2533 "s24", "s25", "s26", "s27",
2534 "s28", "s29", "s30", "s31",
2537 static const char *const h_name
[] =
2539 "h0", "h1", "h2", "h3",
2540 "h4", "h5", "h6", "h7",
2541 "h8", "h9", "h10", "h11",
2542 "h12", "h13", "h14", "h15",
2543 "h16", "h17", "h18", "h19",
2544 "h20", "h21", "h22", "h23",
2545 "h24", "h25", "h26", "h27",
2546 "h28", "h29", "h30", "h31",
2549 static const char *const b_name
[] =
2551 "b0", "b1", "b2", "b3",
2552 "b4", "b5", "b6", "b7",
2553 "b8", "b9", "b10", "b11",
2554 "b12", "b13", "b14", "b15",
2555 "b16", "b17", "b18", "b19",
2556 "b20", "b21", "b22", "b23",
2557 "b24", "b25", "b26", "b27",
2558 "b28", "b29", "b30", "b31",
2561 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2563 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2564 return q_name
[p_regnum
- AARCH64_Q0_REGNUM
];
2566 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2567 return d_name
[p_regnum
- AARCH64_D0_REGNUM
];
2569 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2570 return s_name
[p_regnum
- AARCH64_S0_REGNUM
];
2572 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2573 return h_name
[p_regnum
- AARCH64_H0_REGNUM
];
2575 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2576 return b_name
[p_regnum
- AARCH64_B0_REGNUM
];
2578 if (tdep
->has_sve ())
2580 static const char *const sve_v_name
[] =
2582 "v0", "v1", "v2", "v3",
2583 "v4", "v5", "v6", "v7",
2584 "v8", "v9", "v10", "v11",
2585 "v12", "v13", "v14", "v15",
2586 "v16", "v17", "v18", "v19",
2587 "v20", "v21", "v22", "v23",
2588 "v24", "v25", "v26", "v27",
2589 "v28", "v29", "v30", "v31",
2592 if (p_regnum
>= AARCH64_SVE_V0_REGNUM
2593 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2594 return sve_v_name
[p_regnum
- AARCH64_SVE_V0_REGNUM
];
2597 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2598 prevents it from being read by methods such as
2599 mi_cmd_trace_frame_collected. */
2600 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2603 internal_error (__FILE__
, __LINE__
,
2604 _("aarch64_pseudo_register_name: bad register number %d"),
2608 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2610 static struct type
*
2611 aarch64_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2613 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2615 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2617 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2618 return aarch64_vnq_type (gdbarch
);
2620 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2621 return aarch64_vnd_type (gdbarch
);
2623 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2624 return aarch64_vns_type (gdbarch
);
2626 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2627 return aarch64_vnh_type (gdbarch
);
2629 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2630 return aarch64_vnb_type (gdbarch
);
2632 if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2633 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2634 return aarch64_vnv_type (gdbarch
);
2636 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2637 return builtin_type (gdbarch
)->builtin_uint64
;
2639 internal_error (__FILE__
, __LINE__
,
2640 _("aarch64_pseudo_register_type: bad register number %d"),
2644 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2647 aarch64_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2648 struct reggroup
*group
)
2650 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2652 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2654 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2655 return group
== all_reggroup
|| group
== vector_reggroup
;
2656 else if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2657 return (group
== all_reggroup
|| group
== vector_reggroup
2658 || group
== float_reggroup
);
2659 else if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2660 return (group
== all_reggroup
|| group
== vector_reggroup
2661 || group
== float_reggroup
);
2662 else if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2663 return group
== all_reggroup
|| group
== vector_reggroup
;
2664 else if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2665 return group
== all_reggroup
|| group
== vector_reggroup
;
2666 else if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2667 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2668 return group
== all_reggroup
|| group
== vector_reggroup
;
2669 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2670 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2673 return group
== all_reggroup
;
2676 /* Helper for aarch64_pseudo_read_value. */
2678 static struct value
*
2679 aarch64_pseudo_read_value_1 (struct gdbarch
*gdbarch
,
2680 readable_regcache
*regcache
, int regnum_offset
,
2681 int regsize
, struct value
*result_value
)
2683 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2685 /* Enough space for a full vector register. */
2686 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2687 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2689 if (regcache
->raw_read (v_regnum
, reg_buf
) != REG_VALID
)
2690 mark_value_bytes_unavailable (result_value
, 0,
2691 TYPE_LENGTH (value_type (result_value
)));
2693 memcpy (value_contents_raw (result_value
), reg_buf
, regsize
);
2695 return result_value
;
2698 /* Implement the "pseudo_register_read_value" gdbarch method. */
2700 static struct value
*
2701 aarch64_pseudo_read_value (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2704 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2705 struct value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
2707 VALUE_LVAL (result_value
) = lval_register
;
2708 VALUE_REGNUM (result_value
) = regnum
;
2710 regnum
-= gdbarch_num_regs (gdbarch
);
2712 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2713 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2714 regnum
- AARCH64_Q0_REGNUM
,
2715 Q_REGISTER_SIZE
, result_value
);
2717 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2718 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2719 regnum
- AARCH64_D0_REGNUM
,
2720 D_REGISTER_SIZE
, result_value
);
2722 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2723 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2724 regnum
- AARCH64_S0_REGNUM
,
2725 S_REGISTER_SIZE
, result_value
);
2727 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2728 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2729 regnum
- AARCH64_H0_REGNUM
,
2730 H_REGISTER_SIZE
, result_value
);
2732 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2733 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2734 regnum
- AARCH64_B0_REGNUM
,
2735 B_REGISTER_SIZE
, result_value
);
2737 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2738 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2739 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2740 regnum
- AARCH64_SVE_V0_REGNUM
,
2741 V_REGISTER_SIZE
, result_value
);
2743 gdb_assert_not_reached ("regnum out of bound");
2746 /* Helper for aarch64_pseudo_write. */
2749 aarch64_pseudo_write_1 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2750 int regnum_offset
, int regsize
, const gdb_byte
*buf
)
2752 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2754 /* Enough space for a full vector register. */
2755 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2756 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2758 /* Ensure the register buffer is zero, we want gdb writes of the
2759 various 'scalar' pseudo registers to behavior like architectural
2760 writes, register width bytes are written the remainder are set to
2762 memset (reg_buf
, 0, register_size (gdbarch
, AARCH64_V0_REGNUM
));
2764 memcpy (reg_buf
, buf
, regsize
);
2765 regcache
->raw_write (v_regnum
, reg_buf
);
2768 /* Implement the "pseudo_register_write" gdbarch method. */
2771 aarch64_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2772 int regnum
, const gdb_byte
*buf
)
2774 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2775 regnum
-= gdbarch_num_regs (gdbarch
);
2777 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2778 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2779 regnum
- AARCH64_Q0_REGNUM
, Q_REGISTER_SIZE
,
2782 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2783 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2784 regnum
- AARCH64_D0_REGNUM
, D_REGISTER_SIZE
,
2787 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2788 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2789 regnum
- AARCH64_S0_REGNUM
, S_REGISTER_SIZE
,
2792 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2793 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2794 regnum
- AARCH64_H0_REGNUM
, H_REGISTER_SIZE
,
2797 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2798 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2799 regnum
- AARCH64_B0_REGNUM
, B_REGISTER_SIZE
,
2802 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2803 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2804 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2805 regnum
- AARCH64_SVE_V0_REGNUM
,
2806 V_REGISTER_SIZE
, buf
);
2808 gdb_assert_not_reached ("regnum out of bound");
2811 /* Callback function for user_reg_add. */
2813 static struct value
*
2814 value_of_aarch64_user_reg (struct frame_info
*frame
, const void *baton
)
2816 const int *reg_p
= (const int *) baton
;
2818 return value_of_register (*reg_p
, frame
);
2822 /* Implement the "software_single_step" gdbarch method, needed to
2823 single step through atomic sequences on AArch64. */
2825 static std::vector
<CORE_ADDR
>
2826 aarch64_software_single_step (struct regcache
*regcache
)
2828 struct gdbarch
*gdbarch
= regcache
->arch ();
2829 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2830 const int insn_size
= 4;
2831 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2832 CORE_ADDR pc
= regcache_read_pc (regcache
);
2833 CORE_ADDR breaks
[2] = { CORE_ADDR_MAX
, CORE_ADDR_MAX
};
2835 CORE_ADDR closing_insn
= 0;
2836 uint32_t insn
= read_memory_unsigned_integer (loc
, insn_size
,
2837 byte_order_for_code
);
2840 int bc_insn_count
= 0; /* Conditional branch instruction count. */
2841 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2844 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2847 /* Look for a Load Exclusive instruction which begins the sequence. */
2848 if (inst
.opcode
->iclass
!= ldstexcl
|| bit (insn
, 22) == 0)
2851 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2854 insn
= read_memory_unsigned_integer (loc
, insn_size
,
2855 byte_order_for_code
);
2857 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2859 /* Check if the instruction is a conditional branch. */
2860 if (inst
.opcode
->iclass
== condbranch
)
2862 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_ADDR_PCREL19
);
2864 if (bc_insn_count
>= 1)
2867 /* It is, so we'll try to set a breakpoint at the destination. */
2868 breaks
[1] = loc
+ inst
.operands
[0].imm
.value
;
2874 /* Look for the Store Exclusive which closes the atomic sequence. */
2875 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22) == 0)
2882 /* We didn't find a closing Store Exclusive instruction, fall back. */
2886 /* Insert breakpoint after the end of the atomic sequence. */
2887 breaks
[0] = loc
+ insn_size
;
2889 /* Check for duplicated breakpoints, and also check that the second
2890 breakpoint is not within the atomic sequence. */
2892 && (breaks
[1] == breaks
[0]
2893 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
2894 last_breakpoint
= 0;
2896 std::vector
<CORE_ADDR
> next_pcs
;
2898 /* Insert the breakpoint at the end of the sequence, and one at the
2899 destination of the conditional branch, if it exists. */
2900 for (index
= 0; index
<= last_breakpoint
; index
++)
2901 next_pcs
.push_back (breaks
[index
]);
2906 struct aarch64_displaced_step_closure
: public displaced_step_closure
2908 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2909 is being displaced stepping. */
2912 /* PC adjustment offset after displaced stepping. If 0, then we don't
2913 write the PC back, assuming the PC is already the right address. */
2914 int32_t pc_adjust
= 0;
2917 /* Data when visiting instructions for displaced stepping. */
2919 struct aarch64_displaced_step_data
2921 struct aarch64_insn_data base
;
2923 /* The address where the instruction will be executed at. */
2925 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2926 uint32_t insn_buf
[AARCH64_DISPLACED_MODIFIED_INSNS
];
2927 /* Number of instructions in INSN_BUF. */
2928 unsigned insn_count
;
2929 /* Registers when doing displaced stepping. */
2930 struct regcache
*regs
;
2932 aarch64_displaced_step_closure
*dsc
;
2935 /* Implementation of aarch64_insn_visitor method "b". */
2938 aarch64_displaced_step_b (const int is_bl
, const int32_t offset
,
2939 struct aarch64_insn_data
*data
)
2941 struct aarch64_displaced_step_data
*dsd
2942 = (struct aarch64_displaced_step_data
*) data
;
2943 int64_t new_offset
= data
->insn_addr
- dsd
->new_addr
+ offset
;
2945 if (can_encode_int32 (new_offset
, 28))
2947 /* Emit B rather than BL, because executing BL on a new address
2948 will get the wrong address into LR. In order to avoid this,
2949 we emit B, and update LR if the instruction is BL. */
2950 emit_b (dsd
->insn_buf
, 0, new_offset
);
2956 emit_nop (dsd
->insn_buf
);
2958 dsd
->dsc
->pc_adjust
= offset
;
2964 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
2965 data
->insn_addr
+ 4);
2969 /* Implementation of aarch64_insn_visitor method "b_cond". */
2972 aarch64_displaced_step_b_cond (const unsigned cond
, const int32_t offset
,
2973 struct aarch64_insn_data
*data
)
2975 struct aarch64_displaced_step_data
*dsd
2976 = (struct aarch64_displaced_step_data
*) data
;
2978 /* GDB has to fix up PC after displaced step this instruction
2979 differently according to the condition is true or false. Instead
2980 of checking COND against conditional flags, we can use
2981 the following instructions, and GDB can tell how to fix up PC
2982 according to the PC value.
2984 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2990 emit_bcond (dsd
->insn_buf
, cond
, 8);
2991 dsd
->dsc
->cond
= true;
2992 dsd
->dsc
->pc_adjust
= offset
;
2993 dsd
->insn_count
= 1;
2996 /* Dynamically allocate a new register. If we know the register
2997 statically, we should make it a global as above instead of using this
3000 static struct aarch64_register
3001 aarch64_register (unsigned num
, int is64
)
3003 return (struct aarch64_register
) { num
, is64
};
3006 /* Implementation of aarch64_insn_visitor method "cb". */
3009 aarch64_displaced_step_cb (const int32_t offset
, const int is_cbnz
,
3010 const unsigned rn
, int is64
,
3011 struct aarch64_insn_data
*data
)
3013 struct aarch64_displaced_step_data
*dsd
3014 = (struct aarch64_displaced_step_data
*) data
;
3016 /* The offset is out of range for a compare and branch
3017 instruction. We can use the following instructions instead:
3019 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
3024 emit_cb (dsd
->insn_buf
, is_cbnz
, aarch64_register (rn
, is64
), 8);
3025 dsd
->insn_count
= 1;
3026 dsd
->dsc
->cond
= true;
3027 dsd
->dsc
->pc_adjust
= offset
;
3030 /* Implementation of aarch64_insn_visitor method "tb". */
3033 aarch64_displaced_step_tb (const int32_t offset
, int is_tbnz
,
3034 const unsigned rt
, unsigned bit
,
3035 struct aarch64_insn_data
*data
)
3037 struct aarch64_displaced_step_data
*dsd
3038 = (struct aarch64_displaced_step_data
*) data
;
3040 /* The offset is out of range for a test bit and branch
3041 instruction We can use the following instructions instead:
3043 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
3049 emit_tb (dsd
->insn_buf
, is_tbnz
, bit
, aarch64_register (rt
, 1), 8);
3050 dsd
->insn_count
= 1;
3051 dsd
->dsc
->cond
= true;
3052 dsd
->dsc
->pc_adjust
= offset
;
3055 /* Implementation of aarch64_insn_visitor method "adr". */
3058 aarch64_displaced_step_adr (const int32_t offset
, const unsigned rd
,
3059 const int is_adrp
, struct aarch64_insn_data
*data
)
3061 struct aarch64_displaced_step_data
*dsd
3062 = (struct aarch64_displaced_step_data
*) data
;
3063 /* We know exactly the address the ADR{P,} instruction will compute.
3064 We can just write it to the destination register. */
3065 CORE_ADDR address
= data
->insn_addr
+ offset
;
3069 /* Clear the lower 12 bits of the offset to get the 4K page. */
3070 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
3074 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
3077 dsd
->dsc
->pc_adjust
= 4;
3078 emit_nop (dsd
->insn_buf
);
3079 dsd
->insn_count
= 1;
3082 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
3085 aarch64_displaced_step_ldr_literal (const int32_t offset
, const int is_sw
,
3086 const unsigned rt
, const int is64
,
3087 struct aarch64_insn_data
*data
)
3089 struct aarch64_displaced_step_data
*dsd
3090 = (struct aarch64_displaced_step_data
*) data
;
3091 CORE_ADDR address
= data
->insn_addr
+ offset
;
3092 struct aarch64_memory_operand zero
= { MEMORY_OPERAND_OFFSET
, 0 };
3094 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rt
,
3098 dsd
->insn_count
= emit_ldrsw (dsd
->insn_buf
, aarch64_register (rt
, 1),
3099 aarch64_register (rt
, 1), zero
);
3101 dsd
->insn_count
= emit_ldr (dsd
->insn_buf
, aarch64_register (rt
, is64
),
3102 aarch64_register (rt
, 1), zero
);
3104 dsd
->dsc
->pc_adjust
= 4;
3107 /* Implementation of aarch64_insn_visitor method "others". */
3110 aarch64_displaced_step_others (const uint32_t insn
,
3111 struct aarch64_insn_data
*data
)
3113 struct aarch64_displaced_step_data
*dsd
3114 = (struct aarch64_displaced_step_data
*) data
;
3116 aarch64_emit_insn (dsd
->insn_buf
, insn
);
3117 dsd
->insn_count
= 1;
3119 if ((insn
& 0xfffffc1f) == 0xd65f0000)
3122 dsd
->dsc
->pc_adjust
= 0;
3125 dsd
->dsc
->pc_adjust
= 4;
3128 static const struct aarch64_insn_visitor visitor
=
3130 aarch64_displaced_step_b
,
3131 aarch64_displaced_step_b_cond
,
3132 aarch64_displaced_step_cb
,
3133 aarch64_displaced_step_tb
,
3134 aarch64_displaced_step_adr
,
3135 aarch64_displaced_step_ldr_literal
,
3136 aarch64_displaced_step_others
,
3139 /* Implement the "displaced_step_copy_insn" gdbarch method. */
3141 displaced_step_closure_up
3142 aarch64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
3143 CORE_ADDR from
, CORE_ADDR to
,
3144 struct regcache
*regs
)
3146 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3147 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
3148 struct aarch64_displaced_step_data dsd
;
3151 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
3154 /* Look for a Load Exclusive instruction which begins the sequence. */
3155 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22))
3157 /* We can't displaced step atomic sequences. */
3161 std::unique_ptr
<aarch64_displaced_step_closure
> dsc
3162 (new aarch64_displaced_step_closure
);
3163 dsd
.base
.insn_addr
= from
;
3166 dsd
.dsc
= dsc
.get ();
3168 aarch64_relocate_instruction (insn
, &visitor
,
3169 (struct aarch64_insn_data
*) &dsd
);
3170 gdb_assert (dsd
.insn_count
<= AARCH64_DISPLACED_MODIFIED_INSNS
);
3172 if (dsd
.insn_count
!= 0)
3176 /* Instruction can be relocated to scratch pad. Copy
3177 relocated instruction(s) there. */
3178 for (i
= 0; i
< dsd
.insn_count
; i
++)
3180 if (debug_displaced
)
3182 debug_printf ("displaced: writing insn ");
3183 debug_printf ("%.8x", dsd
.insn_buf
[i
]);
3184 debug_printf (" at %s\n", paddress (gdbarch
, to
+ i
* 4));
3186 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
3187 (ULONGEST
) dsd
.insn_buf
[i
]);
3195 /* This is a work around for a problem with g++ 4.8. */
3196 return displaced_step_closure_up (dsc
.release ());
3199 /* Implement the "displaced_step_fixup" gdbarch method. */
3202 aarch64_displaced_step_fixup (struct gdbarch
*gdbarch
,
3203 struct displaced_step_closure
*dsc_
,
3204 CORE_ADDR from
, CORE_ADDR to
,
3205 struct regcache
*regs
)
3207 aarch64_displaced_step_closure
*dsc
= (aarch64_displaced_step_closure
*) dsc_
;
3211 regcache_cooked_read_unsigned (regs
, AARCH64_PC_REGNUM
, &pc
);
3213 if (debug_displaced
)
3214 debug_printf ("Displaced: PC after stepping: %s (was %s).\n",
3215 paddress (gdbarch
, pc
), paddress (gdbarch
, to
));
3219 if (debug_displaced
)
3220 debug_printf ("Displaced: [Conditional] pc_adjust before: %d\n",
3225 /* Condition is true. */
3227 else if (pc
- to
== 4)
3229 /* Condition is false. */
3233 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
3235 if (debug_displaced
)
3236 debug_printf ("Displaced: [Conditional] pc_adjust after: %d\n",
3240 if (debug_displaced
)
3241 debug_printf ("Displaced: %s PC by %d\n",
3242 dsc
->pc_adjust
? "adjusting" : "not adjusting",
3246 if (dsc
->pc_adjust
!= 0)
3248 /* Make sure the previous instruction was executed (that is, the PC
3249 has changed). If the PC didn't change, then discard the adjustment
3250 offset. Otherwise we may skip an instruction before its execution
3254 if (debug_displaced
)
3255 debug_printf ("Displaced: PC did not move. Discarding PC "
3260 if (debug_displaced
)
3262 debug_printf ("Displaced: fixup: set PC to %s:%d\n",
3263 paddress (gdbarch
, from
), dsc
->pc_adjust
);
3265 regcache_cooked_write_unsigned (regs
, AARCH64_PC_REGNUM
,
3266 from
+ dsc
->pc_adjust
);
3270 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3273 aarch64_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
)
3278 /* Get the correct target description for the given VQ value.
3279 If VQ is zero then it is assumed SVE is not supported.
3280 (It is not possible to set VQ to zero on an SVE system). */
3283 aarch64_read_description (uint64_t vq
, bool pauth_p
)
3285 if (vq
> AARCH64_MAX_SVE_VQ
)
3286 error (_("VQ is %" PRIu64
", maximum supported value is %d"), vq
,
3287 AARCH64_MAX_SVE_VQ
);
3289 struct target_desc
*tdesc
= tdesc_aarch64_list
[vq
][pauth_p
];
3293 tdesc
= aarch64_create_target_description (vq
, pauth_p
);
3294 tdesc_aarch64_list
[vq
][pauth_p
] = tdesc
;
3300 /* Return the VQ used when creating the target description TDESC. */
3303 aarch64_get_tdesc_vq (const struct target_desc
*tdesc
)
3305 const struct tdesc_feature
*feature_sve
;
3307 if (!tdesc_has_registers (tdesc
))
3310 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3312 if (feature_sve
== nullptr)
3315 uint64_t vl
= tdesc_register_bitsize (feature_sve
,
3316 aarch64_sve_register_names
[0]) / 8;
3317 return sve_vq_from_vl (vl
);
3320 /* Add all the expected register sets into GDBARCH. */
3323 aarch64_add_reggroups (struct gdbarch
*gdbarch
)
3325 reggroup_add (gdbarch
, general_reggroup
);
3326 reggroup_add (gdbarch
, float_reggroup
);
3327 reggroup_add (gdbarch
, system_reggroup
);
3328 reggroup_add (gdbarch
, vector_reggroup
);
3329 reggroup_add (gdbarch
, all_reggroup
);
3330 reggroup_add (gdbarch
, save_reggroup
);
3331 reggroup_add (gdbarch
, restore_reggroup
);
3334 /* Implement the "cannot_store_register" gdbarch method. */
3337 aarch64_cannot_store_register (struct gdbarch
*gdbarch
, int regnum
)
3339 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3341 if (!tdep
->has_pauth ())
3344 /* Pointer authentication registers are read-only. */
3345 return (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
3346 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
));
3349 /* Initialize the current architecture based on INFO. If possible,
3350 re-use an architecture from ARCHES, which is a list of
3351 architectures already created during this debugging session.
3353 Called e.g. at program startup, when reading a core file, and when
3354 reading a binary file. */
3356 static struct gdbarch
*
3357 aarch64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3359 const struct tdesc_feature
*feature_core
, *feature_fpu
, *feature_sve
;
3360 const struct tdesc_feature
*feature_pauth
;
3361 bool valid_p
= true;
3362 int i
, num_regs
= 0, num_pseudo_regs
= 0;
3363 int first_pauth_regnum
= -1, pauth_ra_state_offset
= -1;
3365 /* Use the vector length passed via the target info. Here -1 is used for no
3366 SVE, and 0 is unset. If unset then use the vector length from the existing
3369 if (info
.id
== (int *) -1)
3371 else if (info
.id
!= 0)
3372 vq
= (uint64_t) info
.id
;
3374 vq
= aarch64_get_tdesc_vq (info
.target_desc
);
3376 if (vq
> AARCH64_MAX_SVE_VQ
)
3377 internal_error (__FILE__
, __LINE__
, _("VQ out of bounds: %s (max %d)"),
3378 pulongest (vq
), AARCH64_MAX_SVE_VQ
);
3380 /* If there is already a candidate, use it. */
3381 for (gdbarch_list
*best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3382 best_arch
!= nullptr;
3383 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3385 struct gdbarch_tdep
*tdep
= gdbarch_tdep (best_arch
->gdbarch
);
3386 if (tdep
&& tdep
->vq
== vq
)
3387 return best_arch
->gdbarch
;
3390 /* Ensure we always have a target descriptor, and that it is for the given VQ
3392 const struct target_desc
*tdesc
= info
.target_desc
;
3393 if (!tdesc_has_registers (tdesc
) || vq
!= aarch64_get_tdesc_vq (tdesc
))
3394 tdesc
= aarch64_read_description (vq
, false);
3397 feature_core
= tdesc_find_feature (tdesc
,"org.gnu.gdb.aarch64.core");
3398 feature_fpu
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.fpu");
3399 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3400 feature_pauth
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.pauth");
3402 if (feature_core
== nullptr)
3405 tdesc_arch_data_up tdesc_data
= tdesc_data_alloc ();
3407 /* Validate the description provides the mandatory core R registers
3408 and allocate their numbers. */
3409 for (i
= 0; i
< ARRAY_SIZE (aarch64_r_register_names
); i
++)
3410 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
.get (),
3411 AARCH64_X0_REGNUM
+ i
,
3412 aarch64_r_register_names
[i
]);
3414 num_regs
= AARCH64_X0_REGNUM
+ i
;
3416 /* Add the V registers. */
3417 if (feature_fpu
!= nullptr)
3419 if (feature_sve
!= nullptr)
3420 error (_("Program contains both fpu and SVE features."));
3422 /* Validate the description provides the mandatory V registers
3423 and allocate their numbers. */
3424 for (i
= 0; i
< ARRAY_SIZE (aarch64_v_register_names
); i
++)
3425 valid_p
&= tdesc_numbered_register (feature_fpu
, tdesc_data
.get (),
3426 AARCH64_V0_REGNUM
+ i
,
3427 aarch64_v_register_names
[i
]);
3429 num_regs
= AARCH64_V0_REGNUM
+ i
;
3432 /* Add the SVE registers. */
3433 if (feature_sve
!= nullptr)
3435 /* Validate the description provides the mandatory SVE registers
3436 and allocate their numbers. */
3437 for (i
= 0; i
< ARRAY_SIZE (aarch64_sve_register_names
); i
++)
3438 valid_p
&= tdesc_numbered_register (feature_sve
, tdesc_data
.get (),
3439 AARCH64_SVE_Z0_REGNUM
+ i
,
3440 aarch64_sve_register_names
[i
]);
3442 num_regs
= AARCH64_SVE_Z0_REGNUM
+ i
;
3443 num_pseudo_regs
+= 32; /* add the Vn register pseudos. */
3446 if (feature_fpu
!= nullptr || feature_sve
!= nullptr)
3448 num_pseudo_regs
+= 32; /* add the Qn scalar register pseudos */
3449 num_pseudo_regs
+= 32; /* add the Dn scalar register pseudos */
3450 num_pseudo_regs
+= 32; /* add the Sn scalar register pseudos */
3451 num_pseudo_regs
+= 32; /* add the Hn scalar register pseudos */
3452 num_pseudo_regs
+= 32; /* add the Bn scalar register pseudos */
3455 /* Add the pauth registers. */
3456 if (feature_pauth
!= NULL
)
3458 first_pauth_regnum
= num_regs
;
3459 pauth_ra_state_offset
= num_pseudo_regs
;
3460 /* Validate the descriptor provides the mandatory PAUTH registers and
3461 allocate their numbers. */
3462 for (i
= 0; i
< ARRAY_SIZE (aarch64_pauth_register_names
); i
++)
3463 valid_p
&= tdesc_numbered_register (feature_pauth
, tdesc_data
.get (),
3464 first_pauth_regnum
+ i
,
3465 aarch64_pauth_register_names
[i
]);
3468 num_pseudo_regs
+= 1; /* Count RA_STATE pseudo register. */
3474 /* AArch64 code is always little-endian. */
3475 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
3477 struct gdbarch_tdep
*tdep
= XCNEW (struct gdbarch_tdep
);
3478 struct gdbarch
*gdbarch
= gdbarch_alloc (&info
, tdep
);
3480 /* This should be low enough for everything. */
3481 tdep
->lowest_pc
= 0x20;
3482 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3483 tdep
->jb_elt_size
= 8;
3485 tdep
->pauth_reg_base
= first_pauth_regnum
;
3486 tdep
->pauth_ra_state_regnum
= (feature_pauth
== NULL
) ? -1
3487 : pauth_ra_state_offset
+ num_regs
;
3489 set_gdbarch_push_dummy_call (gdbarch
, aarch64_push_dummy_call
);
3490 set_gdbarch_frame_align (gdbarch
, aarch64_frame_align
);
3492 /* Advance PC across function entry code. */
3493 set_gdbarch_skip_prologue (gdbarch
, aarch64_skip_prologue
);
3495 /* The stack grows downward. */
3496 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3498 /* Breakpoint manipulation. */
3499 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3500 aarch64_breakpoint::kind_from_pc
);
3501 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3502 aarch64_breakpoint::bp_from_kind
);
3503 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3504 set_gdbarch_software_single_step (gdbarch
, aarch64_software_single_step
);
3506 /* Information about registers, etc. */
3507 set_gdbarch_sp_regnum (gdbarch
, AARCH64_SP_REGNUM
);
3508 set_gdbarch_pc_regnum (gdbarch
, AARCH64_PC_REGNUM
);
3509 set_gdbarch_num_regs (gdbarch
, num_regs
);
3511 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3512 set_gdbarch_pseudo_register_read_value (gdbarch
, aarch64_pseudo_read_value
);
3513 set_gdbarch_pseudo_register_write (gdbarch
, aarch64_pseudo_write
);
3514 set_tdesc_pseudo_register_name (gdbarch
, aarch64_pseudo_register_name
);
3515 set_tdesc_pseudo_register_type (gdbarch
, aarch64_pseudo_register_type
);
3516 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3517 aarch64_pseudo_register_reggroup_p
);
3518 set_gdbarch_cannot_store_register (gdbarch
, aarch64_cannot_store_register
);
3521 set_gdbarch_short_bit (gdbarch
, 16);
3522 set_gdbarch_int_bit (gdbarch
, 32);
3523 set_gdbarch_float_bit (gdbarch
, 32);
3524 set_gdbarch_double_bit (gdbarch
, 64);
3525 set_gdbarch_long_double_bit (gdbarch
, 128);
3526 set_gdbarch_long_bit (gdbarch
, 64);
3527 set_gdbarch_long_long_bit (gdbarch
, 64);
3528 set_gdbarch_ptr_bit (gdbarch
, 64);
3529 set_gdbarch_char_signed (gdbarch
, 0);
3530 set_gdbarch_wchar_signed (gdbarch
, 0);
3531 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3532 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3533 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3534 set_gdbarch_type_align (gdbarch
, aarch64_type_align
);
3536 /* Internal <-> external register number maps. */
3537 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, aarch64_dwarf_reg_to_regnum
);
3539 /* Returning results. */
3540 set_gdbarch_return_value (gdbarch
, aarch64_return_value
);
3543 set_gdbarch_print_insn (gdbarch
, aarch64_gdb_print_insn
);
3545 /* Virtual tables. */
3546 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3548 /* Register architecture. */
3549 aarch64_add_reggroups (gdbarch
);
3551 /* Hook in the ABI-specific overrides, if they have been registered. */
3552 info
.target_desc
= tdesc
;
3553 info
.tdesc_data
= tdesc_data
.get ();
3554 gdbarch_init_osabi (info
, gdbarch
);
3556 dwarf2_frame_set_init_reg (gdbarch
, aarch64_dwarf2_frame_init_reg
);
3557 /* Register DWARF CFA vendor handler. */
3558 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch
,
3559 aarch64_execute_dwarf_cfa_vendor_op
);
3561 /* Permanent/Program breakpoint handling. */
3562 set_gdbarch_program_breakpoint_here_p (gdbarch
,
3563 aarch64_program_breakpoint_here_p
);
3565 /* Add some default predicates. */
3566 frame_unwind_append_unwinder (gdbarch
, &aarch64_stub_unwind
);
3567 dwarf2_append_unwinders (gdbarch
);
3568 frame_unwind_append_unwinder (gdbarch
, &aarch64_prologue_unwind
);
3570 frame_base_set_default (gdbarch
, &aarch64_normal_base
);
3572 /* Now we have tuned the configuration, set a few final things,
3573 based on what the OS ABI has told us. */
3575 if (tdep
->jb_pc
>= 0)
3576 set_gdbarch_get_longjmp_target (gdbarch
, aarch64_get_longjmp_target
);
3578 set_gdbarch_gen_return_address (gdbarch
, aarch64_gen_return_address
);
3580 set_gdbarch_get_pc_address_flags (gdbarch
, aarch64_get_pc_address_flags
);
3582 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
3584 /* Add standard register aliases. */
3585 for (i
= 0; i
< ARRAY_SIZE (aarch64_register_aliases
); i
++)
3586 user_reg_add (gdbarch
, aarch64_register_aliases
[i
].name
,
3587 value_of_aarch64_user_reg
,
3588 &aarch64_register_aliases
[i
].regnum
);
3590 register_aarch64_ravenscar_ops (gdbarch
);
3596 aarch64_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3598 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3603 fprintf_unfiltered (file
, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3604 paddress (gdbarch
, tdep
->lowest_pc
));
3610 static void aarch64_process_record_test (void);
3614 void _initialize_aarch64_tdep ();
3616 _initialize_aarch64_tdep ()
3618 gdbarch_register (bfd_arch_aarch64
, aarch64_gdbarch_init
,
3621 /* Debug this file's internals. */
3622 add_setshow_boolean_cmd ("aarch64", class_maintenance
, &aarch64_debug
, _("\
3623 Set AArch64 debugging."), _("\
3624 Show AArch64 debugging."), _("\
3625 When on, AArch64 specific debugging is enabled."),
3628 &setdebuglist
, &showdebuglist
);
3631 selftests::register_test ("aarch64-analyze-prologue",
3632 selftests::aarch64_analyze_prologue_test
);
3633 selftests::register_test ("aarch64-process-record",
3634 selftests::aarch64_process_record_test
);
3638 /* AArch64 process record-replay related structures, defines etc. */
3640 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3643 unsigned int reg_len = LENGTH; \
3646 REGS = XNEWVEC (uint32_t, reg_len); \
3647 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3652 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3655 unsigned int mem_len = LENGTH; \
3658 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3659 memcpy(&MEMS->len, &RECORD_BUF[0], \
3660 sizeof(struct aarch64_mem_r) * LENGTH); \
3665 /* AArch64 record/replay structures and enumerations. */
3667 struct aarch64_mem_r
3669 uint64_t len
; /* Record length. */
3670 uint64_t addr
; /* Memory address. */
3673 enum aarch64_record_result
3675 AARCH64_RECORD_SUCCESS
,
3676 AARCH64_RECORD_UNSUPPORTED
,
3677 AARCH64_RECORD_UNKNOWN
3680 typedef struct insn_decode_record_t
3682 struct gdbarch
*gdbarch
;
3683 struct regcache
*regcache
;
3684 CORE_ADDR this_addr
; /* Address of insn to be recorded. */
3685 uint32_t aarch64_insn
; /* Insn to be recorded. */
3686 uint32_t mem_rec_count
; /* Count of memory records. */
3687 uint32_t reg_rec_count
; /* Count of register records. */
3688 uint32_t *aarch64_regs
; /* Registers to be recorded. */
3689 struct aarch64_mem_r
*aarch64_mems
; /* Memory locations to be recorded. */
3690 } insn_decode_record
;
3692 /* Record handler for data processing - register instructions. */
3695 aarch64_record_data_proc_reg (insn_decode_record
*aarch64_insn_r
)
3697 uint8_t reg_rd
, insn_bits24_27
, insn_bits21_23
;
3698 uint32_t record_buf
[4];
3700 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3701 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3702 insn_bits21_23
= bits (aarch64_insn_r
->aarch64_insn
, 21, 23);
3704 if (!bit (aarch64_insn_r
->aarch64_insn
, 28))
3708 /* Logical (shifted register). */
3709 if (insn_bits24_27
== 0x0a)
3710 setflags
= (bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03);
3712 else if (insn_bits24_27
== 0x0b)
3713 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3715 return AARCH64_RECORD_UNKNOWN
;
3717 record_buf
[0] = reg_rd
;
3718 aarch64_insn_r
->reg_rec_count
= 1;
3720 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3724 if (insn_bits24_27
== 0x0b)
3726 /* Data-processing (3 source). */
3727 record_buf
[0] = reg_rd
;
3728 aarch64_insn_r
->reg_rec_count
= 1;
3730 else if (insn_bits24_27
== 0x0a)
3732 if (insn_bits21_23
== 0x00)
3734 /* Add/subtract (with carry). */
3735 record_buf
[0] = reg_rd
;
3736 aarch64_insn_r
->reg_rec_count
= 1;
3737 if (bit (aarch64_insn_r
->aarch64_insn
, 29))
3739 record_buf
[1] = AARCH64_CPSR_REGNUM
;
3740 aarch64_insn_r
->reg_rec_count
= 2;
3743 else if (insn_bits21_23
== 0x02)
3745 /* Conditional compare (register) and conditional compare
3746 (immediate) instructions. */
3747 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3748 aarch64_insn_r
->reg_rec_count
= 1;
3750 else if (insn_bits21_23
== 0x04 || insn_bits21_23
== 0x06)
3752 /* Conditional select. */
3753 /* Data-processing (2 source). */
3754 /* Data-processing (1 source). */
3755 record_buf
[0] = reg_rd
;
3756 aarch64_insn_r
->reg_rec_count
= 1;
3759 return AARCH64_RECORD_UNKNOWN
;
3763 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3765 return AARCH64_RECORD_SUCCESS
;
3768 /* Record handler for data processing - immediate instructions. */
3771 aarch64_record_data_proc_imm (insn_decode_record
*aarch64_insn_r
)
3773 uint8_t reg_rd
, insn_bit23
, insn_bits24_27
, setflags
;
3774 uint32_t record_buf
[4];
3776 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3777 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3778 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3780 if (insn_bits24_27
== 0x00 /* PC rel addressing. */
3781 || insn_bits24_27
== 0x03 /* Bitfield and Extract. */
3782 || (insn_bits24_27
== 0x02 && insn_bit23
)) /* Move wide (immediate). */
3784 record_buf
[0] = reg_rd
;
3785 aarch64_insn_r
->reg_rec_count
= 1;
3787 else if (insn_bits24_27
== 0x01)
3789 /* Add/Subtract (immediate). */
3790 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3791 record_buf
[0] = reg_rd
;
3792 aarch64_insn_r
->reg_rec_count
= 1;
3794 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3796 else if (insn_bits24_27
== 0x02 && !insn_bit23
)
3798 /* Logical (immediate). */
3799 setflags
= bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03;
3800 record_buf
[0] = reg_rd
;
3801 aarch64_insn_r
->reg_rec_count
= 1;
3803 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3806 return AARCH64_RECORD_UNKNOWN
;
3808 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3810 return AARCH64_RECORD_SUCCESS
;
3813 /* Record handler for branch, exception generation and system instructions. */
3816 aarch64_record_branch_except_sys (insn_decode_record
*aarch64_insn_r
)
3818 struct gdbarch_tdep
*tdep
= gdbarch_tdep (aarch64_insn_r
->gdbarch
);
3819 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits22_23
;
3820 uint32_t record_buf
[4];
3822 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3823 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
3824 insn_bits22_23
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3826 if (insn_bits28_31
== 0x0d)
3828 /* Exception generation instructions. */
3829 if (insn_bits24_27
== 0x04)
3831 if (!bits (aarch64_insn_r
->aarch64_insn
, 2, 4)
3832 && !bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
3833 && bits (aarch64_insn_r
->aarch64_insn
, 0, 1) == 0x01)
3835 ULONGEST svc_number
;
3837 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, 8,
3839 return tdep
->aarch64_syscall_record (aarch64_insn_r
->regcache
,
3843 return AARCH64_RECORD_UNSUPPORTED
;
3845 /* System instructions. */
3846 else if (insn_bits24_27
== 0x05 && insn_bits22_23
== 0x00)
3848 uint32_t reg_rt
, reg_crn
;
3850 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3851 reg_crn
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3853 /* Record rt in case of sysl and mrs instructions. */
3854 if (bit (aarch64_insn_r
->aarch64_insn
, 21))
3856 record_buf
[0] = reg_rt
;
3857 aarch64_insn_r
->reg_rec_count
= 1;
3859 /* Record cpsr for hint and msr(immediate) instructions. */
3860 else if (reg_crn
== 0x02 || reg_crn
== 0x04)
3862 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3863 aarch64_insn_r
->reg_rec_count
= 1;
3866 /* Unconditional branch (register). */
3867 else if((insn_bits24_27
& 0x0e) == 0x06)
3869 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3870 if (bits (aarch64_insn_r
->aarch64_insn
, 21, 22) == 0x01)
3871 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3874 return AARCH64_RECORD_UNKNOWN
;
3876 /* Unconditional branch (immediate). */
3877 else if ((insn_bits28_31
& 0x07) == 0x01 && (insn_bits24_27
& 0x0c) == 0x04)
3879 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3880 if (bit (aarch64_insn_r
->aarch64_insn
, 31))
3881 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3884 /* Compare & branch (immediate), Test & branch (immediate) and
3885 Conditional branch (immediate). */
3886 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3888 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3890 return AARCH64_RECORD_SUCCESS
;
3893 /* Record handler for advanced SIMD load and store instructions. */
3896 aarch64_record_asimd_load_store (insn_decode_record
*aarch64_insn_r
)
3899 uint64_t addr_offset
= 0;
3900 uint32_t record_buf
[24];
3901 uint64_t record_buf_mem
[24];
3902 uint32_t reg_rn
, reg_rt
;
3903 uint32_t reg_index
= 0, mem_index
= 0;
3904 uint8_t opcode_bits
, size_bits
;
3906 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3907 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3908 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3909 opcode_bits
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3910 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
, &address
);
3913 debug_printf ("Process record: Advanced SIMD load/store\n");
3915 /* Load/store single structure. */
3916 if (bit (aarch64_insn_r
->aarch64_insn
, 24))
3918 uint8_t sindex
, scale
, selem
, esize
, replicate
= 0;
3919 scale
= opcode_bits
>> 2;
3920 selem
= ((opcode_bits
& 0x02) |
3921 bit (aarch64_insn_r
->aarch64_insn
, 21)) + 1;
3925 if (size_bits
& 0x01)
3926 return AARCH64_RECORD_UNKNOWN
;
3929 if ((size_bits
>> 1) & 0x01)
3930 return AARCH64_RECORD_UNKNOWN
;
3931 if (size_bits
& 0x01)
3933 if (!((opcode_bits
>> 1) & 0x01))
3936 return AARCH64_RECORD_UNKNOWN
;
3940 if (bit (aarch64_insn_r
->aarch64_insn
, 22) && !(opcode_bits
& 0x01))
3947 return AARCH64_RECORD_UNKNOWN
;
3953 for (sindex
= 0; sindex
< selem
; sindex
++)
3955 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3956 reg_rt
= (reg_rt
+ 1) % 32;
3960 for (sindex
= 0; sindex
< selem
; sindex
++)
3962 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3963 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3966 record_buf_mem
[mem_index
++] = esize
/ 8;
3967 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3969 addr_offset
= addr_offset
+ (esize
/ 8);
3970 reg_rt
= (reg_rt
+ 1) % 32;
3974 /* Load/store multiple structure. */
3977 uint8_t selem
, esize
, rpt
, elements
;
3978 uint8_t eindex
, rindex
;
3980 esize
= 8 << size_bits
;
3981 if (bit (aarch64_insn_r
->aarch64_insn
, 30))
3982 elements
= 128 / esize
;
3984 elements
= 64 / esize
;
3986 switch (opcode_bits
)
3988 /*LD/ST4 (4 Registers). */
3993 /*LD/ST1 (4 Registers). */
3998 /*LD/ST3 (3 Registers). */
4003 /*LD/ST1 (3 Registers). */
4008 /*LD/ST1 (1 Register). */
4013 /*LD/ST2 (2 Registers). */
4018 /*LD/ST1 (2 Registers). */
4024 return AARCH64_RECORD_UNSUPPORTED
;
4027 for (rindex
= 0; rindex
< rpt
; rindex
++)
4028 for (eindex
= 0; eindex
< elements
; eindex
++)
4030 uint8_t reg_tt
, sindex
;
4031 reg_tt
= (reg_rt
+ rindex
) % 32;
4032 for (sindex
= 0; sindex
< selem
; sindex
++)
4034 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
4035 record_buf
[reg_index
++] = reg_tt
+ AARCH64_V0_REGNUM
;
4038 record_buf_mem
[mem_index
++] = esize
/ 8;
4039 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
4041 addr_offset
= addr_offset
+ (esize
/ 8);
4042 reg_tt
= (reg_tt
+ 1) % 32;
4047 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
4048 record_buf
[reg_index
++] = reg_rn
;
4050 aarch64_insn_r
->reg_rec_count
= reg_index
;
4051 aarch64_insn_r
->mem_rec_count
= mem_index
/ 2;
4052 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
4054 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4056 return AARCH64_RECORD_SUCCESS
;
4059 /* Record handler for load and store instructions. */
4062 aarch64_record_load_store (insn_decode_record
*aarch64_insn_r
)
4064 uint8_t insn_bits24_27
, insn_bits28_29
, insn_bits10_11
;
4065 uint8_t insn_bit23
, insn_bit21
;
4066 uint8_t opc
, size_bits
, ld_flag
, vector_flag
;
4067 uint32_t reg_rn
, reg_rt
, reg_rt2
;
4068 uint64_t datasize
, offset
;
4069 uint32_t record_buf
[8];
4070 uint64_t record_buf_mem
[8];
4073 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
4074 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
4075 insn_bits28_29
= bits (aarch64_insn_r
->aarch64_insn
, 28, 29);
4076 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
4077 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
4078 ld_flag
= bit (aarch64_insn_r
->aarch64_insn
, 22);
4079 vector_flag
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4080 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
4081 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
4082 reg_rt2
= bits (aarch64_insn_r
->aarch64_insn
, 10, 14);
4083 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 30, 31);
4085 /* Load/store exclusive. */
4086 if (insn_bits24_27
== 0x08 && insn_bits28_29
== 0x00)
4089 debug_printf ("Process record: load/store exclusive\n");
4093 record_buf
[0] = reg_rt
;
4094 aarch64_insn_r
->reg_rec_count
= 1;
4097 record_buf
[1] = reg_rt2
;
4098 aarch64_insn_r
->reg_rec_count
= 2;
4104 datasize
= (8 << size_bits
) * 2;
4106 datasize
= (8 << size_bits
);
4107 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4109 record_buf_mem
[0] = datasize
/ 8;
4110 record_buf_mem
[1] = address
;
4111 aarch64_insn_r
->mem_rec_count
= 1;
4114 /* Save register rs. */
4115 record_buf
[0] = bits (aarch64_insn_r
->aarch64_insn
, 16, 20);
4116 aarch64_insn_r
->reg_rec_count
= 1;
4120 /* Load register (literal) instructions decoding. */
4121 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x01)
4124 debug_printf ("Process record: load register (literal)\n");
4126 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4128 record_buf
[0] = reg_rt
;
4129 aarch64_insn_r
->reg_rec_count
= 1;
4131 /* All types of load/store pair instructions decoding. */
4132 else if ((insn_bits24_27
& 0x0a) == 0x08 && insn_bits28_29
== 0x02)
4135 debug_printf ("Process record: load/store pair\n");
4141 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4142 record_buf
[1] = reg_rt2
+ AARCH64_V0_REGNUM
;
4146 record_buf
[0] = reg_rt
;
4147 record_buf
[1] = reg_rt2
;
4149 aarch64_insn_r
->reg_rec_count
= 2;
4154 imm7_off
= bits (aarch64_insn_r
->aarch64_insn
, 15, 21);
4156 size_bits
= size_bits
>> 1;
4157 datasize
= 8 << (2 + size_bits
);
4158 offset
= (imm7_off
& 0x40) ? (~imm7_off
& 0x007f) + 1 : imm7_off
;
4159 offset
= offset
<< (2 + size_bits
);
4160 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4162 if (!((insn_bits24_27
& 0x0b) == 0x08 && insn_bit23
))
4164 if (imm7_off
& 0x40)
4165 address
= address
- offset
;
4167 address
= address
+ offset
;
4170 record_buf_mem
[0] = datasize
/ 8;
4171 record_buf_mem
[1] = address
;
4172 record_buf_mem
[2] = datasize
/ 8;
4173 record_buf_mem
[3] = address
+ (datasize
/ 8);
4174 aarch64_insn_r
->mem_rec_count
= 2;
4176 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
4177 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4179 /* Load/store register (unsigned immediate) instructions. */
4180 else if ((insn_bits24_27
& 0x0b) == 0x09 && insn_bits28_29
== 0x03)
4182 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4192 if (size_bits
== 0x3 && vector_flag
== 0x0 && opc
== 0x2)
4194 /* PRFM (immediate) */
4195 return AARCH64_RECORD_SUCCESS
;
4197 else if (size_bits
== 0x2 && vector_flag
== 0x0 && opc
== 0x2)
4199 /* LDRSW (immediate) */
4213 debug_printf ("Process record: load/store (unsigned immediate):"
4214 " size %x V %d opc %x\n", size_bits
, vector_flag
,
4220 offset
= bits (aarch64_insn_r
->aarch64_insn
, 10, 21);
4221 datasize
= 8 << size_bits
;
4222 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4224 offset
= offset
<< size_bits
;
4225 address
= address
+ offset
;
4227 record_buf_mem
[0] = datasize
>> 3;
4228 record_buf_mem
[1] = address
;
4229 aarch64_insn_r
->mem_rec_count
= 1;
4234 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4236 record_buf
[0] = reg_rt
;
4237 aarch64_insn_r
->reg_rec_count
= 1;
4240 /* Load/store register (register offset) instructions. */
4241 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4242 && insn_bits10_11
== 0x02 && insn_bit21
)
4245 debug_printf ("Process record: load/store (register offset)\n");
4246 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4253 if (size_bits
!= 0x03)
4256 return AARCH64_RECORD_UNKNOWN
;
4260 ULONGEST reg_rm_val
;
4262 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
,
4263 bits (aarch64_insn_r
->aarch64_insn
, 16, 20), ®_rm_val
);
4264 if (bit (aarch64_insn_r
->aarch64_insn
, 12))
4265 offset
= reg_rm_val
<< size_bits
;
4267 offset
= reg_rm_val
;
4268 datasize
= 8 << size_bits
;
4269 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4271 address
= address
+ offset
;
4272 record_buf_mem
[0] = datasize
>> 3;
4273 record_buf_mem
[1] = address
;
4274 aarch64_insn_r
->mem_rec_count
= 1;
4279 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4281 record_buf
[0] = reg_rt
;
4282 aarch64_insn_r
->reg_rec_count
= 1;
4285 /* Load/store register (immediate and unprivileged) instructions. */
4286 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4291 debug_printf ("Process record: load/store "
4292 "(immediate and unprivileged)\n");
4294 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4301 if (size_bits
!= 0x03)
4304 return AARCH64_RECORD_UNKNOWN
;
4309 imm9_off
= bits (aarch64_insn_r
->aarch64_insn
, 12, 20);
4310 offset
= (imm9_off
& 0x0100) ? (((~imm9_off
) & 0x01ff) + 1) : imm9_off
;
4311 datasize
= 8 << size_bits
;
4312 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4314 if (insn_bits10_11
!= 0x01)
4316 if (imm9_off
& 0x0100)
4317 address
= address
- offset
;
4319 address
= address
+ offset
;
4321 record_buf_mem
[0] = datasize
>> 3;
4322 record_buf_mem
[1] = address
;
4323 aarch64_insn_r
->mem_rec_count
= 1;
4328 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4330 record_buf
[0] = reg_rt
;
4331 aarch64_insn_r
->reg_rec_count
= 1;
4333 if (insn_bits10_11
== 0x01 || insn_bits10_11
== 0x03)
4334 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4336 /* Advanced SIMD load/store instructions. */
4338 return aarch64_record_asimd_load_store (aarch64_insn_r
);
4340 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
4342 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4344 return AARCH64_RECORD_SUCCESS
;
4347 /* Record handler for data processing SIMD and floating point instructions. */
4350 aarch64_record_data_proc_simd_fp (insn_decode_record
*aarch64_insn_r
)
4352 uint8_t insn_bit21
, opcode
, rmode
, reg_rd
;
4353 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits10_11
, insn_bits12_15
;
4354 uint8_t insn_bits11_14
;
4355 uint32_t record_buf
[2];
4357 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
4358 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
4359 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
4360 insn_bits12_15
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
4361 insn_bits11_14
= bits (aarch64_insn_r
->aarch64_insn
, 11, 14);
4362 opcode
= bits (aarch64_insn_r
->aarch64_insn
, 16, 18);
4363 rmode
= bits (aarch64_insn_r
->aarch64_insn
, 19, 20);
4364 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
4365 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
4368 debug_printf ("Process record: data processing SIMD/FP: ");
4370 if ((insn_bits28_31
& 0x05) == 0x01 && insn_bits24_27
== 0x0e)
4372 /* Floating point - fixed point conversion instructions. */
4376 debug_printf ("FP - fixed point conversion");
4378 if ((opcode
>> 1) == 0x0 && rmode
== 0x03)
4379 record_buf
[0] = reg_rd
;
4381 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4383 /* Floating point - conditional compare instructions. */
4384 else if (insn_bits10_11
== 0x01)
4387 debug_printf ("FP - conditional compare");
4389 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4391 /* Floating point - data processing (2-source) and
4392 conditional select instructions. */
4393 else if (insn_bits10_11
== 0x02 || insn_bits10_11
== 0x03)
4396 debug_printf ("FP - DP (2-source)");
4398 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4400 else if (insn_bits10_11
== 0x00)
4402 /* Floating point - immediate instructions. */
4403 if ((insn_bits12_15
& 0x01) == 0x01
4404 || (insn_bits12_15
& 0x07) == 0x04)
4407 debug_printf ("FP - immediate");
4408 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4410 /* Floating point - compare instructions. */
4411 else if ((insn_bits12_15
& 0x03) == 0x02)
4414 debug_printf ("FP - immediate");
4415 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4417 /* Floating point - integer conversions instructions. */
4418 else if (insn_bits12_15
== 0x00)
4420 /* Convert float to integer instruction. */
4421 if (!(opcode
>> 1) || ((opcode
>> 1) == 0x02 && !rmode
))
4424 debug_printf ("float to int conversion");
4426 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4428 /* Convert integer to float instruction. */
4429 else if ((opcode
>> 1) == 0x01 && !rmode
)
4432 debug_printf ("int to float conversion");
4434 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4436 /* Move float to integer instruction. */
4437 else if ((opcode
>> 1) == 0x03)
4440 debug_printf ("move float to int");
4442 if (!(opcode
& 0x01))
4443 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4445 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4448 return AARCH64_RECORD_UNKNOWN
;
4451 return AARCH64_RECORD_UNKNOWN
;
4454 return AARCH64_RECORD_UNKNOWN
;
4456 else if ((insn_bits28_31
& 0x09) == 0x00 && insn_bits24_27
== 0x0e)
4459 debug_printf ("SIMD copy");
4461 /* Advanced SIMD copy instructions. */
4462 if (!bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
4463 && !bit (aarch64_insn_r
->aarch64_insn
, 15)
4464 && bit (aarch64_insn_r
->aarch64_insn
, 10))
4466 if (insn_bits11_14
== 0x05 || insn_bits11_14
== 0x07)
4467 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4469 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4472 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4474 /* All remaining floating point or advanced SIMD instructions. */
4478 debug_printf ("all remain");
4480 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4484 debug_printf ("\n");
4486 aarch64_insn_r
->reg_rec_count
++;
4487 gdb_assert (aarch64_insn_r
->reg_rec_count
== 1);
4488 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4490 return AARCH64_RECORD_SUCCESS
;
4493 /* Decodes insns type and invokes its record handler. */
4496 aarch64_record_decode_insn_handler (insn_decode_record
*aarch64_insn_r
)
4498 uint32_t ins_bit25
, ins_bit26
, ins_bit27
, ins_bit28
;
4500 ins_bit25
= bit (aarch64_insn_r
->aarch64_insn
, 25);
4501 ins_bit26
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4502 ins_bit27
= bit (aarch64_insn_r
->aarch64_insn
, 27);
4503 ins_bit28
= bit (aarch64_insn_r
->aarch64_insn
, 28);
4505 /* Data processing - immediate instructions. */
4506 if (!ins_bit26
&& !ins_bit27
&& ins_bit28
)
4507 return aarch64_record_data_proc_imm (aarch64_insn_r
);
4509 /* Branch, exception generation and system instructions. */
4510 if (ins_bit26
&& !ins_bit27
&& ins_bit28
)
4511 return aarch64_record_branch_except_sys (aarch64_insn_r
);
4513 /* Load and store instructions. */
4514 if (!ins_bit25
&& ins_bit27
)
4515 return aarch64_record_load_store (aarch64_insn_r
);
4517 /* Data processing - register instructions. */
4518 if (ins_bit25
&& !ins_bit26
&& ins_bit27
)
4519 return aarch64_record_data_proc_reg (aarch64_insn_r
);
4521 /* Data processing - SIMD and floating point instructions. */
4522 if (ins_bit25
&& ins_bit26
&& ins_bit27
)
4523 return aarch64_record_data_proc_simd_fp (aarch64_insn_r
);
4525 return AARCH64_RECORD_UNSUPPORTED
;
4528 /* Cleans up local record registers and memory allocations. */
4531 deallocate_reg_mem (insn_decode_record
*record
)
4533 xfree (record
->aarch64_regs
);
4534 xfree (record
->aarch64_mems
);
4538 namespace selftests
{
4541 aarch64_process_record_test (void)
4543 struct gdbarch_info info
;
4546 gdbarch_info_init (&info
);
4547 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
4549 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
4550 SELF_CHECK (gdbarch
!= NULL
);
4552 insn_decode_record aarch64_record
;
4554 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4555 aarch64_record
.regcache
= NULL
;
4556 aarch64_record
.this_addr
= 0;
4557 aarch64_record
.gdbarch
= gdbarch
;
4559 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4560 aarch64_record
.aarch64_insn
= 0xf9800020;
4561 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4562 SELF_CHECK (ret
== AARCH64_RECORD_SUCCESS
);
4563 SELF_CHECK (aarch64_record
.reg_rec_count
== 0);
4564 SELF_CHECK (aarch64_record
.mem_rec_count
== 0);
4566 deallocate_reg_mem (&aarch64_record
);
4569 } // namespace selftests
4570 #endif /* GDB_SELF_TEST */
4572 /* Parse the current instruction and record the values of the registers and
4573 memory that will be changed in current instruction to record_arch_list
4574 return -1 if something is wrong. */
4577 aarch64_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4578 CORE_ADDR insn_addr
)
4580 uint32_t rec_no
= 0;
4581 uint8_t insn_size
= 4;
4583 gdb_byte buf
[insn_size
];
4584 insn_decode_record aarch64_record
;
4586 memset (&buf
[0], 0, insn_size
);
4587 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4588 target_read_memory (insn_addr
, &buf
[0], insn_size
);
4589 aarch64_record
.aarch64_insn
4590 = (uint32_t) extract_unsigned_integer (&buf
[0],
4592 gdbarch_byte_order (gdbarch
));
4593 aarch64_record
.regcache
= regcache
;
4594 aarch64_record
.this_addr
= insn_addr
;
4595 aarch64_record
.gdbarch
= gdbarch
;
4597 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4598 if (ret
== AARCH64_RECORD_UNSUPPORTED
)
4600 printf_unfiltered (_("Process record does not support instruction "
4601 "0x%0x at address %s.\n"),
4602 aarch64_record
.aarch64_insn
,
4603 paddress (gdbarch
, insn_addr
));
4609 /* Record registers. */
4610 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4612 /* Always record register CPSR. */
4613 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4614 AARCH64_CPSR_REGNUM
);
4615 if (aarch64_record
.aarch64_regs
)
4616 for (rec_no
= 0; rec_no
< aarch64_record
.reg_rec_count
; rec_no
++)
4617 if (record_full_arch_list_add_reg (aarch64_record
.regcache
,
4618 aarch64_record
.aarch64_regs
[rec_no
]))
4621 /* Record memories. */
4622 if (aarch64_record
.aarch64_mems
)
4623 for (rec_no
= 0; rec_no
< aarch64_record
.mem_rec_count
; rec_no
++)
4624 if (record_full_arch_list_add_mem
4625 ((CORE_ADDR
)aarch64_record
.aarch64_mems
[rec_no
].addr
,
4626 aarch64_record
.aarch64_mems
[rec_no
].len
))
4629 if (record_full_arch_list_add_end ())
4633 deallocate_reg_mem (&aarch64_record
);