1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2016 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "x86-xstate.h"
44 #include "features/i386/amd64.c"
45 #include "features/i386/amd64-avx.c"
46 #include "features/i386/amd64-mpx.c"
47 #include "features/i386/amd64-avx-mpx.c"
48 #include "features/i386/amd64-avx512.c"
50 #include "features/i386/x32.c"
51 #include "features/i386/x32-avx.c"
52 #include "features/i386/x32-avx512.c"
57 /* Note that the AMD64 architecture was previously known as x86-64.
58 The latter is (forever) engraved into the canonical system name as
59 returned by config.guess, and used as the name for the AMD64 port
60 of GNU/Linux. The BSD's have renamed their ports to amd64; they
61 don't like to shout. For GDB we prefer the amd64_-prefix over the
62 x86_64_-prefix since it's so much easier to type. */
64 /* Register information. */
66 static const char *amd64_register_names
[] =
68 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
70 /* %r8 is indeed register number 8. */
71 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
72 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
74 /* %st0 is register number 24. */
75 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
76 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
78 /* %xmm0 is register number 40. */
79 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
80 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
84 static const char *amd64_ymm_names
[] =
86 "ymm0", "ymm1", "ymm2", "ymm3",
87 "ymm4", "ymm5", "ymm6", "ymm7",
88 "ymm8", "ymm9", "ymm10", "ymm11",
89 "ymm12", "ymm13", "ymm14", "ymm15"
92 static const char *amd64_ymm_avx512_names
[] =
94 "ymm16", "ymm17", "ymm18", "ymm19",
95 "ymm20", "ymm21", "ymm22", "ymm23",
96 "ymm24", "ymm25", "ymm26", "ymm27",
97 "ymm28", "ymm29", "ymm30", "ymm31"
100 static const char *amd64_ymmh_names
[] =
102 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
103 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
104 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
105 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
108 static const char *amd64_ymmh_avx512_names
[] =
110 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
111 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
112 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
113 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
116 static const char *amd64_mpx_names
[] =
118 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
121 static const char *amd64_k_names
[] =
123 "k0", "k1", "k2", "k3",
124 "k4", "k5", "k6", "k7"
127 static const char *amd64_zmmh_names
[] =
129 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
130 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
131 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
132 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
133 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
134 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
135 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
136 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
139 static const char *amd64_zmm_names
[] =
141 "zmm0", "zmm1", "zmm2", "zmm3",
142 "zmm4", "zmm5", "zmm6", "zmm7",
143 "zmm8", "zmm9", "zmm10", "zmm11",
144 "zmm12", "zmm13", "zmm14", "zmm15",
145 "zmm16", "zmm17", "zmm18", "zmm19",
146 "zmm20", "zmm21", "zmm22", "zmm23",
147 "zmm24", "zmm25", "zmm26", "zmm27",
148 "zmm28", "zmm29", "zmm30", "zmm31"
151 static const char *amd64_xmm_avx512_names
[] = {
152 "xmm16", "xmm17", "xmm18", "xmm19",
153 "xmm20", "xmm21", "xmm22", "xmm23",
154 "xmm24", "xmm25", "xmm26", "xmm27",
155 "xmm28", "xmm29", "xmm30", "xmm31"
158 /* DWARF Register Number Mapping as defined in the System V psABI,
161 static int amd64_dwarf_regmap
[] =
163 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
164 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
165 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
166 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
168 /* Frame Pointer Register RBP. */
171 /* Stack Pointer Register RSP. */
174 /* Extended Integer Registers 8 - 15. */
175 AMD64_R8_REGNUM
, /* %r8 */
176 AMD64_R9_REGNUM
, /* %r9 */
177 AMD64_R10_REGNUM
, /* %r10 */
178 AMD64_R11_REGNUM
, /* %r11 */
179 AMD64_R12_REGNUM
, /* %r12 */
180 AMD64_R13_REGNUM
, /* %r13 */
181 AMD64_R14_REGNUM
, /* %r14 */
182 AMD64_R15_REGNUM
, /* %r15 */
184 /* Return Address RA. Mapped to RIP. */
187 /* SSE Registers 0 - 7. */
188 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
189 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
190 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
191 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
193 /* Extended SSE Registers 8 - 15. */
194 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
195 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
196 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
197 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
199 /* Floating Point Registers 0-7. */
200 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
201 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
202 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
203 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
205 /* MMX Registers 0 - 7.
206 We have to handle those registers specifically, as their register
207 number within GDB depends on the target (or they may even not be
208 available at all). */
209 -1, -1, -1, -1, -1, -1, -1, -1,
211 /* Control and Status Flags Register. */
214 /* Selector Registers. */
224 /* Segment Base Address Registers. */
230 /* Special Selector Registers. */
234 /* Floating Point Control Registers. */
240 static const int amd64_dwarf_regmap_len
=
241 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
243 /* Convert DWARF register number REG to the appropriate register
244 number used by GDB. */
247 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
249 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
250 int ymm0_regnum
= tdep
->ymm0_regnum
;
253 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
254 regnum
= amd64_dwarf_regmap
[reg
];
257 && i386_xmm_regnum_p (gdbarch
, regnum
))
258 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
263 /* Map architectural register numbers to gdb register numbers. */
265 static const int amd64_arch_regmap
[16] =
267 AMD64_RAX_REGNUM
, /* %rax */
268 AMD64_RCX_REGNUM
, /* %rcx */
269 AMD64_RDX_REGNUM
, /* %rdx */
270 AMD64_RBX_REGNUM
, /* %rbx */
271 AMD64_RSP_REGNUM
, /* %rsp */
272 AMD64_RBP_REGNUM
, /* %rbp */
273 AMD64_RSI_REGNUM
, /* %rsi */
274 AMD64_RDI_REGNUM
, /* %rdi */
275 AMD64_R8_REGNUM
, /* %r8 */
276 AMD64_R9_REGNUM
, /* %r9 */
277 AMD64_R10_REGNUM
, /* %r10 */
278 AMD64_R11_REGNUM
, /* %r11 */
279 AMD64_R12_REGNUM
, /* %r12 */
280 AMD64_R13_REGNUM
, /* %r13 */
281 AMD64_R14_REGNUM
, /* %r14 */
282 AMD64_R15_REGNUM
/* %r15 */
285 static const int amd64_arch_regmap_len
=
286 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
288 /* Convert architectural register number REG to the appropriate register
289 number used by GDB. */
292 amd64_arch_reg_to_regnum (int reg
)
294 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
296 return amd64_arch_regmap
[reg
];
299 /* Register names for byte pseudo-registers. */
301 static const char *amd64_byte_names
[] =
303 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
304 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
305 "ah", "bh", "ch", "dh"
308 /* Number of lower byte registers. */
309 #define AMD64_NUM_LOWER_BYTE_REGS 16
311 /* Register names for word pseudo-registers. */
313 static const char *amd64_word_names
[] =
315 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
316 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
319 /* Register names for dword pseudo-registers. */
321 static const char *amd64_dword_names
[] =
323 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
324 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
328 /* Return the name of register REGNUM. */
331 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
333 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
334 if (i386_byte_regnum_p (gdbarch
, regnum
))
335 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
336 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
337 return amd64_zmm_names
[regnum
- tdep
->zmm0_regnum
];
338 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
339 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
340 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
341 return amd64_ymm_avx512_names
[regnum
- tdep
->ymm16_regnum
];
342 else if (i386_word_regnum_p (gdbarch
, regnum
))
343 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
344 else if (i386_dword_regnum_p (gdbarch
, regnum
))
345 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
347 return i386_pseudo_register_name (gdbarch
, regnum
);
350 static struct value
*
351 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
352 struct regcache
*regcache
,
355 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
356 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
357 enum register_status status
;
358 struct value
*result_value
;
361 result_value
= allocate_value (register_type (gdbarch
, regnum
));
362 VALUE_LVAL (result_value
) = lval_register
;
363 VALUE_REGNUM (result_value
) = regnum
;
364 buf
= value_contents_raw (result_value
);
366 if (i386_byte_regnum_p (gdbarch
, regnum
))
368 int gpnum
= regnum
- tdep
->al_regnum
;
370 /* Extract (always little endian). */
371 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
373 /* Special handling for AH, BH, CH, DH. */
374 status
= regcache_raw_read (regcache
,
375 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
,
377 if (status
== REG_VALID
)
378 memcpy (buf
, raw_buf
+ 1, 1);
380 mark_value_bytes_unavailable (result_value
, 0,
381 TYPE_LENGTH (value_type (result_value
)));
385 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
386 if (status
== REG_VALID
)
387 memcpy (buf
, raw_buf
, 1);
389 mark_value_bytes_unavailable (result_value
, 0,
390 TYPE_LENGTH (value_type (result_value
)));
393 else if (i386_dword_regnum_p (gdbarch
, regnum
))
395 int gpnum
= regnum
- tdep
->eax_regnum
;
396 /* Extract (always little endian). */
397 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
398 if (status
== REG_VALID
)
399 memcpy (buf
, raw_buf
, 4);
401 mark_value_bytes_unavailable (result_value
, 0,
402 TYPE_LENGTH (value_type (result_value
)));
405 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
412 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
413 struct regcache
*regcache
,
414 int regnum
, const gdb_byte
*buf
)
416 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
417 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
419 if (i386_byte_regnum_p (gdbarch
, regnum
))
421 int gpnum
= regnum
- tdep
->al_regnum
;
423 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
425 /* Read ... AH, BH, CH, DH. */
426 regcache_raw_read (regcache
,
427 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
428 /* ... Modify ... (always little endian). */
429 memcpy (raw_buf
+ 1, buf
, 1);
431 regcache_raw_write (regcache
,
432 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
437 regcache_raw_read (regcache
, gpnum
, raw_buf
);
438 /* ... Modify ... (always little endian). */
439 memcpy (raw_buf
, buf
, 1);
441 regcache_raw_write (regcache
, gpnum
, raw_buf
);
444 else if (i386_dword_regnum_p (gdbarch
, regnum
))
446 int gpnum
= regnum
- tdep
->eax_regnum
;
449 regcache_raw_read (regcache
, gpnum
, raw_buf
);
450 /* ... Modify ... (always little endian). */
451 memcpy (raw_buf
, buf
, 4);
453 regcache_raw_write (regcache
, gpnum
, raw_buf
);
456 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
459 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
462 amd64_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
463 struct agent_expr
*ax
, int regnum
)
465 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
467 if (i386_byte_regnum_p (gdbarch
, regnum
))
469 int gpnum
= regnum
- tdep
->al_regnum
;
471 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
472 ax_reg_mask (ax
, gpnum
- AMD64_NUM_LOWER_BYTE_REGS
);
474 ax_reg_mask (ax
, gpnum
);
477 else if (i386_dword_regnum_p (gdbarch
, regnum
))
479 int gpnum
= regnum
- tdep
->eax_regnum
;
481 ax_reg_mask (ax
, gpnum
);
485 return i386_ax_pseudo_register_collect (gdbarch
, ax
, regnum
);
490 /* Register classes as defined in the psABI. */
504 /* Return the union class of CLASS1 and CLASS2. See the psABI for
507 static enum amd64_reg_class
508 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
510 /* Rule (a): If both classes are equal, this is the resulting class. */
511 if (class1
== class2
)
514 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
515 is the other class. */
516 if (class1
== AMD64_NO_CLASS
)
518 if (class2
== AMD64_NO_CLASS
)
521 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
522 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
525 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
526 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
527 return AMD64_INTEGER
;
529 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
530 MEMORY is used as class. */
531 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
532 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
533 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
536 /* Rule (f): Otherwise class SSE is used. */
540 static void amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2]);
542 /* Return non-zero if TYPE is a non-POD structure or union type. */
545 amd64_non_pod_p (struct type
*type
)
547 /* ??? A class with a base class certainly isn't POD, but does this
548 catch all non-POD structure types? */
549 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
555 /* Classify TYPE according to the rules for aggregate (structures and
556 arrays) and union types, and store the result in CLASS. */
559 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class theclass
[2])
561 /* 1. If the size of an object is larger than two eightbytes, or in
562 C++, is a non-POD structure or union type, or contains
563 unaligned fields, it has class memory. */
564 if (TYPE_LENGTH (type
) > 16 || amd64_non_pod_p (type
))
566 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
570 /* 2. Both eightbytes get initialized to class NO_CLASS. */
571 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
573 /* 3. Each field of an object is classified recursively so that
574 always two fields are considered. The resulting class is
575 calculated according to the classes of the fields in the
578 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
580 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
582 /* All fields in an array have the same type. */
583 amd64_classify (subtype
, theclass
);
584 if (TYPE_LENGTH (type
) > 8 && theclass
[1] == AMD64_NO_CLASS
)
585 theclass
[1] = theclass
[0];
591 /* Structure or union. */
592 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
593 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
595 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
597 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
598 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
599 enum amd64_reg_class subclass
[2];
600 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
604 bitsize
= TYPE_LENGTH (subtype
) * 8;
605 endpos
= (TYPE_FIELD_BITPOS (type
, i
) + bitsize
- 1) / 64;
607 /* Ignore static fields. */
608 if (field_is_static (&TYPE_FIELD (type
, i
)))
611 gdb_assert (pos
== 0 || pos
== 1);
613 amd64_classify (subtype
, subclass
);
614 theclass
[pos
] = amd64_merge_classes (theclass
[pos
], subclass
[0]);
615 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
616 /* This is a bit of an odd case: We have a field that would
617 normally fit in one of the two eightbytes, except that
618 it is placed in a way that this field straddles them.
619 This has been seen with a structure containing an array.
621 The ABI is a bit unclear in this case, but we assume that
622 this field's class (stored in subclass[0]) must also be merged
623 into class[1]. In other words, our field has a piece stored
624 in the second eight-byte, and thus its class applies to
625 the second eight-byte as well.
627 In the case where the field length exceeds 8 bytes,
628 it should not be necessary to merge the field class
629 into class[1]. As LEN > 8, subclass[1] is necessarily
630 different from AMD64_NO_CLASS. If subclass[1] is equal
631 to subclass[0], then the normal class[1]/subclass[1]
632 merging will take care of everything. For subclass[1]
633 to be different from subclass[0], I can only see the case
634 where we have a SSE/SSEUP or X87/X87UP pair, which both
635 use up all 16 bytes of the aggregate, and are already
636 handled just fine (because each portion sits on its own
638 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[0]);
640 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[1]);
644 /* 4. Then a post merger cleanup is done: */
646 /* Rule (a): If one of the classes is MEMORY, the whole argument is
648 if (theclass
[0] == AMD64_MEMORY
|| theclass
[1] == AMD64_MEMORY
)
649 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
651 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
653 if (theclass
[0] == AMD64_SSEUP
)
654 theclass
[0] = AMD64_SSE
;
655 if (theclass
[1] == AMD64_SSEUP
&& theclass
[0] != AMD64_SSE
)
656 theclass
[1] = AMD64_SSE
;
659 /* Classify TYPE, and store the result in CLASS. */
662 amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2])
664 enum type_code code
= TYPE_CODE (type
);
665 int len
= TYPE_LENGTH (type
);
667 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
669 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
670 long, long long, and pointers are in the INTEGER class. Similarly,
671 range types, used by languages such as Ada, are also in the INTEGER
673 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
674 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
675 || code
== TYPE_CODE_CHAR
676 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
677 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
678 theclass
[0] = AMD64_INTEGER
;
680 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
682 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
683 && (len
== 4 || len
== 8))
685 theclass
[0] = AMD64_SSE
;
687 /* Arguments of types __float128, _Decimal128 and __m128 are split into
688 two halves. The least significant ones belong to class SSE, the most
689 significant one to class SSEUP. */
690 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
691 /* FIXME: __float128, __m128. */
692 theclass
[0] = AMD64_SSE
, theclass
[1] = AMD64_SSEUP
;
694 /* The 64-bit mantissa of arguments of type long double belongs to
695 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
697 else if (code
== TYPE_CODE_FLT
&& len
== 16)
698 /* Class X87 and X87UP. */
699 theclass
[0] = AMD64_X87
, theclass
[1] = AMD64_X87UP
;
701 /* Arguments of complex T where T is one of the types float or
702 double get treated as if they are implemented as:
710 else if (code
== TYPE_CODE_COMPLEX
&& len
== 8)
711 theclass
[0] = AMD64_SSE
;
712 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
713 theclass
[0] = theclass
[1] = AMD64_SSE
;
715 /* A variable of type complex long double is classified as type
717 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
718 theclass
[0] = AMD64_COMPLEX_X87
;
721 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
722 || code
== TYPE_CODE_UNION
)
723 amd64_classify_aggregate (type
, theclass
);
726 static enum return_value_convention
727 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
728 struct type
*type
, struct regcache
*regcache
,
729 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
731 enum amd64_reg_class theclass
[2];
732 int len
= TYPE_LENGTH (type
);
733 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
734 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
739 gdb_assert (!(readbuf
&& writebuf
));
741 /* 1. Classify the return type with the classification algorithm. */
742 amd64_classify (type
, theclass
);
744 /* 2. If the type has class MEMORY, then the caller provides space
745 for the return value and passes the address of this storage in
746 %rdi as if it were the first argument to the function. In effect,
747 this address becomes a hidden first argument.
749 On return %rax will contain the address that has been passed in
750 by the caller in %rdi. */
751 if (theclass
[0] == AMD64_MEMORY
)
753 /* As indicated by the comment above, the ABI guarantees that we
754 can always find the return value just after the function has
761 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
762 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
765 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
768 /* 8. If the class is COMPLEX_X87, the real part of the value is
769 returned in %st0 and the imaginary part in %st1. */
770 if (theclass
[0] == AMD64_COMPLEX_X87
)
774 regcache_raw_read (regcache
, AMD64_ST0_REGNUM
, readbuf
);
775 regcache_raw_read (regcache
, AMD64_ST1_REGNUM
, readbuf
+ 16);
780 i387_return_value (gdbarch
, regcache
);
781 regcache_raw_write (regcache
, AMD64_ST0_REGNUM
, writebuf
);
782 regcache_raw_write (regcache
, AMD64_ST1_REGNUM
, writebuf
+ 16);
784 /* Fix up the tag word such that both %st(0) and %st(1) are
786 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
789 return RETURN_VALUE_REGISTER_CONVENTION
;
792 gdb_assert (theclass
[1] != AMD64_MEMORY
);
793 gdb_assert (len
<= 16);
795 for (i
= 0; len
> 0; i
++, len
-= 8)
803 /* 3. If the class is INTEGER, the next available register
804 of the sequence %rax, %rdx is used. */
805 regnum
= integer_regnum
[integer_reg
++];
809 /* 4. If the class is SSE, the next available SSE register
810 of the sequence %xmm0, %xmm1 is used. */
811 regnum
= sse_regnum
[sse_reg
++];
815 /* 5. If the class is SSEUP, the eightbyte is passed in the
816 upper half of the last used SSE register. */
817 gdb_assert (sse_reg
> 0);
818 regnum
= sse_regnum
[sse_reg
- 1];
823 /* 6. If the class is X87, the value is returned on the X87
824 stack in %st0 as 80-bit x87 number. */
825 regnum
= AMD64_ST0_REGNUM
;
827 i387_return_value (gdbarch
, regcache
);
831 /* 7. If the class is X87UP, the value is returned together
832 with the previous X87 value in %st0. */
833 gdb_assert (i
> 0 && theclass
[0] == AMD64_X87
);
834 regnum
= AMD64_ST0_REGNUM
;
843 gdb_assert (!"Unexpected register class.");
846 gdb_assert (regnum
!= -1);
849 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
852 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
856 return RETURN_VALUE_REGISTER_CONVENTION
;
861 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
862 struct value
**args
, CORE_ADDR sp
, int struct_return
)
864 static int integer_regnum
[] =
866 AMD64_RDI_REGNUM
, /* %rdi */
867 AMD64_RSI_REGNUM
, /* %rsi */
868 AMD64_RDX_REGNUM
, /* %rdx */
869 AMD64_RCX_REGNUM
, /* %rcx */
870 AMD64_R8_REGNUM
, /* %r8 */
871 AMD64_R9_REGNUM
/* %r9 */
873 static int sse_regnum
[] =
875 /* %xmm0 ... %xmm7 */
876 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
877 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
878 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
879 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
881 struct value
**stack_args
= XALLOCAVEC (struct value
*, nargs
);
882 int num_stack_args
= 0;
883 int num_elements
= 0;
889 /* Reserve a register for the "hidden" argument. */
893 for (i
= 0; i
< nargs
; i
++)
895 struct type
*type
= value_type (args
[i
]);
896 int len
= TYPE_LENGTH (type
);
897 enum amd64_reg_class theclass
[2];
898 int needed_integer_regs
= 0;
899 int needed_sse_regs
= 0;
902 /* Classify argument. */
903 amd64_classify (type
, theclass
);
905 /* Calculate the number of integer and SSE registers needed for
907 for (j
= 0; j
< 2; j
++)
909 if (theclass
[j
] == AMD64_INTEGER
)
910 needed_integer_regs
++;
911 else if (theclass
[j
] == AMD64_SSE
)
915 /* Check whether enough registers are available, and if the
916 argument should be passed in registers at all. */
917 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
918 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
919 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
921 /* The argument will be passed on the stack. */
922 num_elements
+= ((len
+ 7) / 8);
923 stack_args
[num_stack_args
++] = args
[i
];
927 /* The argument will be passed in registers. */
928 const gdb_byte
*valbuf
= value_contents (args
[i
]);
931 gdb_assert (len
<= 16);
933 for (j
= 0; len
> 0; j
++, len
-= 8)
941 regnum
= integer_regnum
[integer_reg
++];
945 regnum
= sse_regnum
[sse_reg
++];
949 gdb_assert (sse_reg
> 0);
950 regnum
= sse_regnum
[sse_reg
- 1];
955 gdb_assert (!"Unexpected register class.");
958 gdb_assert (regnum
!= -1);
959 memset (buf
, 0, sizeof buf
);
960 memcpy (buf
, valbuf
+ j
* 8, min (len
, 8));
961 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
966 /* Allocate space for the arguments on the stack. */
967 sp
-= num_elements
* 8;
969 /* The psABI says that "The end of the input argument area shall be
970 aligned on a 16 byte boundary." */
973 /* Write out the arguments to the stack. */
974 for (i
= 0; i
< num_stack_args
; i
++)
976 struct type
*type
= value_type (stack_args
[i
]);
977 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
978 int len
= TYPE_LENGTH (type
);
980 write_memory (sp
+ element
* 8, valbuf
, len
);
981 element
+= ((len
+ 7) / 8);
984 /* The psABI says that "For calls that may call functions that use
985 varargs or stdargs (prototype-less calls or calls to functions
986 containing ellipsis (...) in the declaration) %al is used as
987 hidden argument to specify the number of SSE registers used. */
988 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
993 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
994 struct regcache
*regcache
, CORE_ADDR bp_addr
,
995 int nargs
, struct value
**args
, CORE_ADDR sp
,
996 int struct_return
, CORE_ADDR struct_addr
)
998 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1001 /* Pass arguments. */
1002 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, struct_return
);
1004 /* Pass "hidden" argument". */
1007 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
1008 regcache_cooked_write (regcache
, AMD64_RDI_REGNUM
, buf
);
1011 /* Store return address. */
1013 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
1014 write_memory (sp
, buf
, 8);
1016 /* Finally, update the stack pointer... */
1017 store_unsigned_integer (buf
, 8, byte_order
, sp
);
1018 regcache_cooked_write (regcache
, AMD64_RSP_REGNUM
, buf
);
1020 /* ...and fake a frame pointer. */
1021 regcache_cooked_write (regcache
, AMD64_RBP_REGNUM
, buf
);
1026 /* Displaced instruction handling. */
1028 /* A partially decoded instruction.
1029 This contains enough details for displaced stepping purposes. */
1033 /* The number of opcode bytes. */
1035 /* The offset of the rex prefix or -1 if not present. */
1037 /* The offset to the first opcode byte. */
1039 /* The offset to the modrm byte or -1 if not present. */
1042 /* The raw instruction. */
1046 struct displaced_step_closure
1048 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1053 /* Details of the instruction. */
1054 struct amd64_insn insn_details
;
1056 /* Amount of space allocated to insn_buf. */
1059 /* The possibly modified insn.
1060 This is a variable-length field. */
1061 gdb_byte insn_buf
[1];
1064 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1065 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1066 at which point delete these in favor of libopcodes' versions). */
1068 static const unsigned char onebyte_has_modrm
[256] = {
1069 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1070 /* ------------------------------- */
1071 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1072 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1073 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1074 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1075 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1076 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1077 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1078 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1079 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1080 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1081 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1082 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1083 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1084 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1085 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1086 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1087 /* ------------------------------- */
1088 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1091 static const unsigned char twobyte_has_modrm
[256] = {
1092 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1093 /* ------------------------------- */
1094 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1095 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1096 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1097 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1098 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1099 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1100 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1101 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1102 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1103 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1104 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1105 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1106 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1107 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1108 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1109 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1110 /* ------------------------------- */
1111 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1114 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1117 rex_prefix_p (gdb_byte pfx
)
1119 return REX_PREFIX_P (pfx
);
1122 /* Skip the legacy instruction prefixes in INSN.
1123 We assume INSN is properly sentineled so we don't have to worry
1124 about falling off the end of the buffer. */
1127 amd64_skip_prefixes (gdb_byte
*insn
)
1133 case DATA_PREFIX_OPCODE
:
1134 case ADDR_PREFIX_OPCODE
:
1135 case CS_PREFIX_OPCODE
:
1136 case DS_PREFIX_OPCODE
:
1137 case ES_PREFIX_OPCODE
:
1138 case FS_PREFIX_OPCODE
:
1139 case GS_PREFIX_OPCODE
:
1140 case SS_PREFIX_OPCODE
:
1141 case LOCK_PREFIX_OPCODE
:
1142 case REPE_PREFIX_OPCODE
:
1143 case REPNE_PREFIX_OPCODE
:
1155 /* Return an integer register (other than RSP) that is unused as an input
1157 In order to not require adding a rex prefix if the insn doesn't already
1158 have one, the result is restricted to RAX ... RDI, sans RSP.
1159 The register numbering of the result follows architecture ordering,
1163 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1165 /* 1 bit for each reg */
1166 int used_regs_mask
= 0;
1168 /* There can be at most 3 int regs used as inputs in an insn, and we have
1169 7 to choose from (RAX ... RDI, sans RSP).
1170 This allows us to take a conservative approach and keep things simple.
1171 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1172 that implicitly specify RAX. */
1175 used_regs_mask
|= 1 << EAX_REG_NUM
;
1176 /* Similarily avoid RDX, implicit operand in divides. */
1177 used_regs_mask
|= 1 << EDX_REG_NUM
;
1179 used_regs_mask
|= 1 << ESP_REG_NUM
;
1181 /* If the opcode is one byte long and there's no ModRM byte,
1182 assume the opcode specifies a register. */
1183 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1184 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1186 /* Mark used regs in the modrm/sib bytes. */
1187 if (details
->modrm_offset
!= -1)
1189 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1190 int mod
= MODRM_MOD_FIELD (modrm
);
1191 int reg
= MODRM_REG_FIELD (modrm
);
1192 int rm
= MODRM_RM_FIELD (modrm
);
1193 int have_sib
= mod
!= 3 && rm
== 4;
1195 /* Assume the reg field of the modrm byte specifies a register. */
1196 used_regs_mask
|= 1 << reg
;
1200 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1201 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1202 used_regs_mask
|= 1 << base
;
1203 used_regs_mask
|= 1 << idx
;
1207 used_regs_mask
|= 1 << rm
;
1211 gdb_assert (used_regs_mask
< 256);
1212 gdb_assert (used_regs_mask
!= 255);
1214 /* Finally, find a free reg. */
1218 for (i
= 0; i
< 8; ++i
)
1220 if (! (used_regs_mask
& (1 << i
)))
1224 /* We shouldn't get here. */
1225 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1229 /* Extract the details of INSN that we need. */
1232 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1234 gdb_byte
*start
= insn
;
1237 details
->raw_insn
= insn
;
1239 details
->opcode_len
= -1;
1240 details
->rex_offset
= -1;
1241 details
->opcode_offset
= -1;
1242 details
->modrm_offset
= -1;
1244 /* Skip legacy instruction prefixes. */
1245 insn
= amd64_skip_prefixes (insn
);
1247 /* Skip REX instruction prefix. */
1248 if (rex_prefix_p (*insn
))
1250 details
->rex_offset
= insn
- start
;
1254 details
->opcode_offset
= insn
- start
;
1256 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1258 /* Two or three-byte opcode. */
1260 need_modrm
= twobyte_has_modrm
[*insn
];
1262 /* Check for three-byte opcode. */
1272 details
->opcode_len
= 3;
1275 details
->opcode_len
= 2;
1281 /* One-byte opcode. */
1282 need_modrm
= onebyte_has_modrm
[*insn
];
1283 details
->opcode_len
= 1;
1289 details
->modrm_offset
= insn
- start
;
1293 /* Update %rip-relative addressing in INSN.
1295 %rip-relative addressing only uses a 32-bit displacement.
1296 32 bits is not enough to be guaranteed to cover the distance between where
1297 the real instruction is and where its copy is.
1298 Convert the insn to use base+disp addressing.
1299 We set base = pc + insn_length so we can leave disp unchanged. */
1302 fixup_riprel (struct gdbarch
*gdbarch
, struct displaced_step_closure
*dsc
,
1303 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1305 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1306 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1307 int modrm_offset
= insn_details
->modrm_offset
;
1308 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1312 int arch_tmp_regno
, tmp_regno
;
1313 ULONGEST orig_value
;
1315 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1318 /* Compute the rip-relative address. */
1319 disp
= extract_signed_integer (insn
, sizeof (int32_t), byte_order
);
1320 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
,
1321 dsc
->max_len
, from
);
1322 rip_base
= from
+ insn_length
;
1324 /* We need a register to hold the address.
1325 Pick one not used in the insn.
1326 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1327 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1328 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1330 /* REX.B should be unset as we were using rip-relative addressing,
1331 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1332 if (insn_details
->rex_offset
!= -1)
1333 dsc
->insn_buf
[insn_details
->rex_offset
] &= ~REX_B
;
1335 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1336 dsc
->tmp_regno
= tmp_regno
;
1337 dsc
->tmp_save
= orig_value
;
1340 /* Convert the ModRM field to be base+disp. */
1341 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1342 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1344 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1346 if (debug_displaced
)
1347 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1348 "displaced: using temp reg %d, old value %s, new value %s\n",
1349 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1350 paddress (gdbarch
, rip_base
));
1354 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1355 struct displaced_step_closure
*dsc
,
1356 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1358 const struct amd64_insn
*details
= &dsc
->insn_details
;
1360 if (details
->modrm_offset
!= -1)
1362 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1364 if ((modrm
& 0xc7) == 0x05)
1366 /* The insn uses rip-relative addressing.
1368 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1373 struct displaced_step_closure
*
1374 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1375 CORE_ADDR from
, CORE_ADDR to
,
1376 struct regcache
*regs
)
1378 int len
= gdbarch_max_insn_length (gdbarch
);
1379 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1380 continually watch for running off the end of the buffer. */
1381 int fixup_sentinel_space
= len
;
1382 struct displaced_step_closure
*dsc
1383 = ((struct displaced_step_closure
*)
1384 xmalloc (sizeof (*dsc
) + len
+ fixup_sentinel_space
));
1385 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1386 struct amd64_insn
*details
= &dsc
->insn_details
;
1389 dsc
->max_len
= len
+ fixup_sentinel_space
;
1391 read_memory (from
, buf
, len
);
1393 /* Set up the sentinel space so we don't have to worry about running
1394 off the end of the buffer. An excessive number of leading prefixes
1395 could otherwise cause this. */
1396 memset (buf
+ len
, 0, fixup_sentinel_space
);
1398 amd64_get_insn_details (buf
, details
);
1400 /* GDB may get control back after the insn after the syscall.
1401 Presumably this is a kernel bug.
1402 If this is a syscall, make sure there's a nop afterwards. */
1406 if (amd64_syscall_p (details
, &syscall_length
))
1407 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1410 /* Modify the insn to cope with the address where it will be executed from.
1411 In particular, handle any rip-relative addressing. */
1412 fixup_displaced_copy (gdbarch
, dsc
, from
, to
, regs
);
1414 write_memory (to
, buf
, len
);
1416 if (debug_displaced
)
1418 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1419 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1420 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1427 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1429 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1431 if (insn
[0] == 0xff)
1433 /* jump near, absolute indirect (/4) */
1434 if ((insn
[1] & 0x38) == 0x20)
1437 /* jump far, absolute indirect (/5) */
1438 if ((insn
[1] & 0x38) == 0x28)
1445 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1448 amd64_jmp_p (const struct amd64_insn
*details
)
1450 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1452 /* jump short, relative. */
1453 if (insn
[0] == 0xeb)
1456 /* jump near, relative. */
1457 if (insn
[0] == 0xe9)
1460 return amd64_absolute_jmp_p (details
);
1464 amd64_absolute_call_p (const struct amd64_insn
*details
)
1466 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1468 if (insn
[0] == 0xff)
1470 /* Call near, absolute indirect (/2) */
1471 if ((insn
[1] & 0x38) == 0x10)
1474 /* Call far, absolute indirect (/3) */
1475 if ((insn
[1] & 0x38) == 0x18)
1483 amd64_ret_p (const struct amd64_insn
*details
)
1485 /* NOTE: gcc can emit "repz ; ret". */
1486 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1490 case 0xc2: /* ret near, pop N bytes */
1491 case 0xc3: /* ret near */
1492 case 0xca: /* ret far, pop N bytes */
1493 case 0xcb: /* ret far */
1494 case 0xcf: /* iret */
1503 amd64_call_p (const struct amd64_insn
*details
)
1505 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1507 if (amd64_absolute_call_p (details
))
1510 /* call near, relative */
1511 if (insn
[0] == 0xe8)
1517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1518 length in bytes. Otherwise, return zero. */
1521 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1523 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1525 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1534 /* Classify the instruction at ADDR using PRED.
1535 Throw an error if the memory can't be read. */
1538 amd64_classify_insn_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1539 int (*pred
) (const struct amd64_insn
*))
1541 struct amd64_insn details
;
1543 int len
, classification
;
1545 len
= gdbarch_max_insn_length (gdbarch
);
1546 buf
= (gdb_byte
*) alloca (len
);
1548 read_code (addr
, buf
, len
);
1549 amd64_get_insn_details (buf
, &details
);
1551 classification
= pred (&details
);
1553 return classification
;
1556 /* The gdbarch insn_is_call method. */
1559 amd64_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1561 return amd64_classify_insn_at (gdbarch
, addr
, amd64_call_p
);
1564 /* The gdbarch insn_is_ret method. */
1567 amd64_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1569 return amd64_classify_insn_at (gdbarch
, addr
, amd64_ret_p
);
1572 /* The gdbarch insn_is_jump method. */
1575 amd64_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1577 return amd64_classify_insn_at (gdbarch
, addr
, amd64_jmp_p
);
1580 /* Fix up the state of registers and memory after having single-stepped
1581 a displaced instruction. */
1584 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1585 struct displaced_step_closure
*dsc
,
1586 CORE_ADDR from
, CORE_ADDR to
,
1587 struct regcache
*regs
)
1589 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1590 /* The offset we applied to the instruction's address. */
1591 ULONGEST insn_offset
= to
- from
;
1592 gdb_byte
*insn
= dsc
->insn_buf
;
1593 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1595 if (debug_displaced
)
1596 fprintf_unfiltered (gdb_stdlog
,
1597 "displaced: fixup (%s, %s), "
1598 "insn = 0x%02x 0x%02x ...\n",
1599 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1602 /* If we used a tmp reg, restore it. */
1606 if (debug_displaced
)
1607 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1608 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1609 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1612 /* The list of issues to contend with here is taken from
1613 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1614 Yay for Free Software! */
1616 /* Relocate the %rip back to the program's instruction stream,
1619 /* Except in the case of absolute or indirect jump or call
1620 instructions, or a return instruction, the new rip is relative to
1621 the displaced instruction; make it relative to the original insn.
1622 Well, signal handler returns don't need relocation either, but we use the
1623 value of %rip to recognize those; see below. */
1624 if (! amd64_absolute_jmp_p (insn_details
)
1625 && ! amd64_absolute_call_p (insn_details
)
1626 && ! amd64_ret_p (insn_details
))
1631 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1633 /* A signal trampoline system call changes the %rip, resuming
1634 execution of the main program after the signal handler has
1635 returned. That makes them like 'return' instructions; we
1636 shouldn't relocate %rip.
1638 But most system calls don't, and we do need to relocate %rip.
1640 Our heuristic for distinguishing these cases: if stepping
1641 over the system call instruction left control directly after
1642 the instruction, the we relocate --- control almost certainly
1643 doesn't belong in the displaced copy. Otherwise, we assume
1644 the instruction has put control where it belongs, and leave
1645 it unrelocated. Goodness help us if there are PC-relative
1647 if (amd64_syscall_p (insn_details
, &insn_len
)
1648 && orig_rip
!= to
+ insn_len
1649 /* GDB can get control back after the insn after the syscall.
1650 Presumably this is a kernel bug.
1651 Fixup ensures its a nop, we add one to the length for it. */
1652 && orig_rip
!= to
+ insn_len
+ 1)
1654 if (debug_displaced
)
1655 fprintf_unfiltered (gdb_stdlog
,
1656 "displaced: syscall changed %%rip; "
1657 "not relocating\n");
1661 ULONGEST rip
= orig_rip
- insn_offset
;
1663 /* If we just stepped over a breakpoint insn, we don't backup
1664 the pc on purpose; this is to match behaviour without
1667 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1669 if (debug_displaced
)
1670 fprintf_unfiltered (gdb_stdlog
,
1672 "relocated %%rip from %s to %s\n",
1673 paddress (gdbarch
, orig_rip
),
1674 paddress (gdbarch
, rip
));
1678 /* If the instruction was PUSHFL, then the TF bit will be set in the
1679 pushed value, and should be cleared. We'll leave this for later,
1680 since GDB already messes up the TF flag when stepping over a
1683 /* If the instruction was a call, the return address now atop the
1684 stack is the address following the copied instruction. We need
1685 to make it the address following the original instruction. */
1686 if (amd64_call_p (insn_details
))
1690 const ULONGEST retaddr_len
= 8;
1692 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1693 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1694 retaddr
= (retaddr
- insn_offset
) & 0xffffffffffffffffULL
;
1695 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1697 if (debug_displaced
)
1698 fprintf_unfiltered (gdb_stdlog
,
1699 "displaced: relocated return addr at %s "
1701 paddress (gdbarch
, rsp
),
1702 paddress (gdbarch
, retaddr
));
1706 /* If the instruction INSN uses RIP-relative addressing, return the
1707 offset into the raw INSN where the displacement to be adjusted is
1708 found. Returns 0 if the instruction doesn't use RIP-relative
1712 rip_relative_offset (struct amd64_insn
*insn
)
1714 if (insn
->modrm_offset
!= -1)
1716 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1718 if ((modrm
& 0xc7) == 0x05)
1720 /* The displacement is found right after the ModRM byte. */
1721 return insn
->modrm_offset
+ 1;
1729 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1731 target_write_memory (*to
, buf
, len
);
1736 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1737 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1739 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1740 int len
= gdbarch_max_insn_length (gdbarch
);
1741 /* Extra space for sentinels. */
1742 int fixup_sentinel_space
= len
;
1743 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
+ fixup_sentinel_space
);
1744 struct amd64_insn insn_details
;
1746 LONGEST rel32
, newrel
;
1750 read_memory (oldloc
, buf
, len
);
1752 /* Set up the sentinel space so we don't have to worry about running
1753 off the end of the buffer. An excessive number of leading prefixes
1754 could otherwise cause this. */
1755 memset (buf
+ len
, 0, fixup_sentinel_space
);
1758 amd64_get_insn_details (insn
, &insn_details
);
1760 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1762 /* Skip legacy instruction prefixes. */
1763 insn
= amd64_skip_prefixes (insn
);
1765 /* Adjust calls with 32-bit relative addresses as push/jump, with
1766 the address pushed being the location where the original call in
1767 the user program would return to. */
1768 if (insn
[0] == 0xe8)
1770 gdb_byte push_buf
[16];
1771 unsigned int ret_addr
;
1773 /* Where "ret" in the original code will return to. */
1774 ret_addr
= oldloc
+ insn_length
;
1775 push_buf
[0] = 0x68; /* pushq $... */
1776 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1777 /* Push the push. */
1778 append_insns (to
, 5, push_buf
);
1780 /* Convert the relative call to a relative jump. */
1783 /* Adjust the destination offset. */
1784 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1785 newrel
= (oldloc
- *to
) + rel32
;
1786 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1788 if (debug_displaced
)
1789 fprintf_unfiltered (gdb_stdlog
,
1790 "Adjusted insn rel32=%s at %s to"
1791 " rel32=%s at %s\n",
1792 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1793 hex_string (newrel
), paddress (gdbarch
, *to
));
1795 /* Write the adjusted jump into its displaced location. */
1796 append_insns (to
, 5, insn
);
1800 offset
= rip_relative_offset (&insn_details
);
1803 /* Adjust jumps with 32-bit relative addresses. Calls are
1804 already handled above. */
1805 if (insn
[0] == 0xe9)
1807 /* Adjust conditional jumps. */
1808 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1814 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1815 newrel
= (oldloc
- *to
) + rel32
;
1816 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1817 if (debug_displaced
)
1818 fprintf_unfiltered (gdb_stdlog
,
1819 "Adjusted insn rel32=%s at %s to"
1820 " rel32=%s at %s\n",
1821 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1822 hex_string (newrel
), paddress (gdbarch
, *to
));
1825 /* Write the adjusted instruction into its displaced location. */
1826 append_insns (to
, insn_length
, buf
);
1830 /* The maximum number of saved registers. This should include %rip. */
1831 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1833 struct amd64_frame_cache
1838 CORE_ADDR sp_offset
;
1841 /* Saved registers. */
1842 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1846 /* Do we have a frame? */
1850 /* Initialize a frame cache. */
1853 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1860 cache
->sp_offset
= -8;
1863 /* Saved registers. We initialize these to -1 since zero is a valid
1864 offset (that's where %rbp is supposed to be stored).
1865 The values start out as being offsets, and are later converted to
1866 addresses (at which point -1 is interpreted as an address, still meaning
1868 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1869 cache
->saved_regs
[i
] = -1;
1870 cache
->saved_sp
= 0;
1871 cache
->saved_sp_reg
= -1;
1873 /* Frameless until proven otherwise. */
1874 cache
->frameless_p
= 1;
1877 /* Allocate and initialize a frame cache. */
1879 static struct amd64_frame_cache
*
1880 amd64_alloc_frame_cache (void)
1882 struct amd64_frame_cache
*cache
;
1884 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1885 amd64_init_frame_cache (cache
);
1889 /* GCC 4.4 and later, can put code in the prologue to realign the
1890 stack pointer. Check whether PC points to such code, and update
1891 CACHE accordingly. Return the first instruction after the code
1892 sequence or CURRENT_PC, whichever is smaller. If we don't
1893 recognize the code, return PC. */
1896 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1897 struct amd64_frame_cache
*cache
)
1899 /* There are 2 code sequences to re-align stack before the frame
1902 1. Use a caller-saved saved register:
1908 2. Use a callee-saved saved register:
1915 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1917 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1918 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1923 int offset
, offset_and
;
1925 if (target_read_code (pc
, buf
, sizeof buf
))
1928 /* Check caller-saved saved register. The first instruction has
1929 to be "leaq 8(%rsp), %reg". */
1930 if ((buf
[0] & 0xfb) == 0x48
1935 /* MOD must be binary 10 and R/M must be binary 100. */
1936 if ((buf
[2] & 0xc7) != 0x44)
1939 /* REG has register number. */
1940 reg
= (buf
[2] >> 3) & 7;
1942 /* Check the REX.R bit. */
1950 /* Check callee-saved saved register. The first instruction
1951 has to be "pushq %reg". */
1953 if ((buf
[0] & 0xf8) == 0x50)
1955 else if ((buf
[0] & 0xf6) == 0x40
1956 && (buf
[1] & 0xf8) == 0x50)
1958 /* Check the REX.B bit. */
1959 if ((buf
[0] & 1) != 0)
1968 reg
+= buf
[offset
] & 0x7;
1972 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1973 if ((buf
[offset
] & 0xfb) != 0x48
1974 || buf
[offset
+ 1] != 0x8d
1975 || buf
[offset
+ 3] != 0x24
1976 || buf
[offset
+ 4] != 0x10)
1979 /* MOD must be binary 10 and R/M must be binary 100. */
1980 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
1983 /* REG has register number. */
1984 r
= (buf
[offset
+ 2] >> 3) & 7;
1986 /* Check the REX.R bit. */
1987 if (buf
[offset
] == 0x4c)
1990 /* Registers in pushq and leaq have to be the same. */
1997 /* Rigister can't be %rsp nor %rbp. */
1998 if (reg
== 4 || reg
== 5)
2001 /* The next instruction has to be "andq $-XXX, %rsp". */
2002 if (buf
[offset
] != 0x48
2003 || buf
[offset
+ 2] != 0xe4
2004 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2007 offset_and
= offset
;
2008 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2010 /* The next instruction has to be "pushq -8(%reg)". */
2012 if (buf
[offset
] == 0xff)
2014 else if ((buf
[offset
] & 0xf6) == 0x40
2015 && buf
[offset
+ 1] == 0xff)
2017 /* Check the REX.B bit. */
2018 if ((buf
[offset
] & 0x1) != 0)
2025 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2027 if (buf
[offset
+ 1] != 0xf8
2028 || (buf
[offset
] & 0xf8) != 0x70)
2031 /* R/M has register. */
2032 r
+= buf
[offset
] & 7;
2034 /* Registers in leaq and pushq have to be the same. */
2038 if (current_pc
> pc
+ offset_and
)
2039 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2041 return min (pc
+ offset
+ 2, current_pc
);
2044 /* Similar to amd64_analyze_stack_align for x32. */
2047 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2048 struct amd64_frame_cache
*cache
)
2050 /* There are 2 code sequences to re-align stack before the frame
2053 1. Use a caller-saved saved register:
2061 [addr32] leal 8(%rsp), %reg
2063 [addr32] pushq -8(%reg)
2065 2. Use a callee-saved saved register:
2075 [addr32] leal 16(%rsp), %reg
2077 [addr32] pushq -8(%reg)
2079 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2081 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2082 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2084 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2086 0x83 0xe4 0xf0 andl $-16, %esp
2087 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2092 int offset
, offset_and
;
2094 if (target_read_memory (pc
, buf
, sizeof buf
))
2097 /* Skip optional addr32 prefix. */
2098 offset
= buf
[0] == 0x67 ? 1 : 0;
2100 /* Check caller-saved saved register. The first instruction has
2101 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2102 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
2103 && buf
[offset
+ 1] == 0x8d
2104 && buf
[offset
+ 3] == 0x24
2105 && buf
[offset
+ 4] == 0x8)
2107 /* MOD must be binary 10 and R/M must be binary 100. */
2108 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2111 /* REG has register number. */
2112 reg
= (buf
[offset
+ 2] >> 3) & 7;
2114 /* Check the REX.R bit. */
2115 if ((buf
[offset
] & 0x4) != 0)
2122 /* Check callee-saved saved register. The first instruction
2123 has to be "pushq %reg". */
2125 if ((buf
[offset
] & 0xf6) == 0x40
2126 && (buf
[offset
+ 1] & 0xf8) == 0x50)
2128 /* Check the REX.B bit. */
2129 if ((buf
[offset
] & 1) != 0)
2134 else if ((buf
[offset
] & 0xf8) != 0x50)
2138 reg
+= buf
[offset
] & 0x7;
2142 /* Skip optional addr32 prefix. */
2143 if (buf
[offset
] == 0x67)
2146 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2147 "leal 16(%rsp), %reg". */
2148 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
2149 || buf
[offset
+ 1] != 0x8d
2150 || buf
[offset
+ 3] != 0x24
2151 || buf
[offset
+ 4] != 0x10)
2154 /* MOD must be binary 10 and R/M must be binary 100. */
2155 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2158 /* REG has register number. */
2159 r
= (buf
[offset
+ 2] >> 3) & 7;
2161 /* Check the REX.R bit. */
2162 if ((buf
[offset
] & 0x4) != 0)
2165 /* Registers in pushq and leaq have to be the same. */
2172 /* Rigister can't be %rsp nor %rbp. */
2173 if (reg
== 4 || reg
== 5)
2176 /* The next instruction may be "andq $-XXX, %rsp" or
2177 "andl $-XXX, %esp". */
2178 if (buf
[offset
] != 0x48)
2181 if (buf
[offset
+ 2] != 0xe4
2182 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2185 offset_and
= offset
;
2186 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2188 /* Skip optional addr32 prefix. */
2189 if (buf
[offset
] == 0x67)
2192 /* The next instruction has to be "pushq -8(%reg)". */
2194 if (buf
[offset
] == 0xff)
2196 else if ((buf
[offset
] & 0xf6) == 0x40
2197 && buf
[offset
+ 1] == 0xff)
2199 /* Check the REX.B bit. */
2200 if ((buf
[offset
] & 0x1) != 0)
2207 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2209 if (buf
[offset
+ 1] != 0xf8
2210 || (buf
[offset
] & 0xf8) != 0x70)
2213 /* R/M has register. */
2214 r
+= buf
[offset
] & 7;
2216 /* Registers in leaq and pushq have to be the same. */
2220 if (current_pc
> pc
+ offset_and
)
2221 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2223 return min (pc
+ offset
+ 2, current_pc
);
2226 /* Do a limited analysis of the prologue at PC and update CACHE
2227 accordingly. Bail out early if CURRENT_PC is reached. Return the
2228 address where the analysis stopped.
2230 We will handle only functions beginning with:
2233 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2235 or (for the X32 ABI):
2238 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2240 Any function that doesn't start with one of these sequences will be
2241 assumed to have no prologue and thus no valid frame pointer in
2245 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2246 CORE_ADDR pc
, CORE_ADDR current_pc
,
2247 struct amd64_frame_cache
*cache
)
2249 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2250 /* There are two variations of movq %rsp, %rbp. */
2251 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2252 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2253 /* Ditto for movl %esp, %ebp. */
2254 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2255 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2260 if (current_pc
<= pc
)
2263 if (gdbarch_ptr_bit (gdbarch
) == 32)
2264 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2266 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2268 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2270 if (op
== 0x55) /* pushq %rbp */
2272 /* Take into account that we've executed the `pushq %rbp' that
2273 starts this instruction sequence. */
2274 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2275 cache
->sp_offset
+= 8;
2277 /* If that's all, return now. */
2278 if (current_pc
<= pc
+ 1)
2281 read_code (pc
+ 1, buf
, 3);
2283 /* Check for `movq %rsp, %rbp'. */
2284 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2285 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2287 /* OK, we actually have a frame. */
2288 cache
->frameless_p
= 0;
2292 /* For X32, also check for `movq %esp, %ebp'. */
2293 if (gdbarch_ptr_bit (gdbarch
) == 32)
2295 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2296 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2298 /* OK, we actually have a frame. */
2299 cache
->frameless_p
= 0;
2310 /* Work around false termination of prologue - GCC PR debug/48827.
2312 START_PC is the first instruction of a function, PC is its minimal already
2313 determined advanced address. Function returns PC if it has nothing to do.
2317 <-- here is 0 lines advance - the false prologue end marker.
2318 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2319 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2320 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2321 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2322 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2323 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2324 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2325 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2329 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2331 struct symtab_and_line start_pc_sal
, next_sal
;
2332 gdb_byte buf
[4 + 8 * 7];
2338 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2339 if (start_pc_sal
.symtab
== NULL
2340 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2341 (SYMTAB_COMPUNIT (start_pc_sal
.symtab
))) < 6
2342 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2345 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2346 if (next_sal
.line
!= start_pc_sal
.line
)
2349 /* START_PC can be from overlayed memory, ignored here. */
2350 if (target_read_code (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2354 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2361 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2363 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2364 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2365 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2369 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2371 /* 8-bit displacement. */
2375 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2377 /* 32-bit displacement. */
2385 if (offset
- 4 != buf
[3])
2388 return next_sal
.end
;
2391 /* Return PC of first real instruction. */
2394 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2396 struct amd64_frame_cache cache
;
2398 CORE_ADDR func_addr
;
2400 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2402 CORE_ADDR post_prologue_pc
2403 = skip_prologue_using_sal (gdbarch
, func_addr
);
2404 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
2406 /* Clang always emits a line note before the prologue and another
2407 one after. We trust clang to emit usable line notes. */
2408 if (post_prologue_pc
2410 && COMPUNIT_PRODUCER (cust
) != NULL
2411 && startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
2412 return max (start_pc
, post_prologue_pc
);
2415 amd64_init_frame_cache (&cache
);
2416 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2418 if (cache
.frameless_p
)
2421 return amd64_skip_xmm_prologue (pc
, start_pc
);
2425 /* Normal frames. */
2428 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2429 struct amd64_frame_cache
*cache
)
2431 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2432 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2436 cache
->pc
= get_frame_func (this_frame
);
2438 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2441 if (cache
->frameless_p
)
2443 /* We didn't find a valid frame. If we're at the start of a
2444 function, or somewhere half-way its prologue, the function's
2445 frame probably hasn't been fully setup yet. Try to
2446 reconstruct the base address for the stack frame by looking
2447 at the stack pointer. For truly "frameless" functions this
2450 if (cache
->saved_sp_reg
!= -1)
2452 /* Stack pointer has been saved. */
2453 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2454 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2456 /* We're halfway aligning the stack. */
2457 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2458 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2460 /* This will be added back below. */
2461 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2465 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2466 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2472 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2473 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2476 /* Now that we have the base address for the stack frame we can
2477 calculate the value of %rsp in the calling frame. */
2478 cache
->saved_sp
= cache
->base
+ 16;
2480 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2481 frame we find it at the same offset from the reconstructed base
2482 address. If we're halfway aligning the stack, %rip is handled
2483 differently (see above). */
2484 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2485 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2487 /* Adjust all the saved registers such that they contain addresses
2488 instead of offsets. */
2489 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2490 if (cache
->saved_regs
[i
] != -1)
2491 cache
->saved_regs
[i
] += cache
->base
;
2496 static struct amd64_frame_cache
*
2497 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2499 struct amd64_frame_cache
*cache
;
2502 return (struct amd64_frame_cache
*) *this_cache
;
2504 cache
= amd64_alloc_frame_cache ();
2505 *this_cache
= cache
;
2509 amd64_frame_cache_1 (this_frame
, cache
);
2511 CATCH (ex
, RETURN_MASK_ERROR
)
2513 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2514 throw_exception (ex
);
2521 static enum unwind_stop_reason
2522 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2525 struct amd64_frame_cache
*cache
=
2526 amd64_frame_cache (this_frame
, this_cache
);
2529 return UNWIND_UNAVAILABLE
;
2531 /* This marks the outermost frame. */
2532 if (cache
->base
== 0)
2533 return UNWIND_OUTERMOST
;
2535 return UNWIND_NO_REASON
;
2539 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2540 struct frame_id
*this_id
)
2542 struct amd64_frame_cache
*cache
=
2543 amd64_frame_cache (this_frame
, this_cache
);
2546 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2547 else if (cache
->base
== 0)
2549 /* This marks the outermost frame. */
2553 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2556 static struct value
*
2557 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2560 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2561 struct amd64_frame_cache
*cache
=
2562 amd64_frame_cache (this_frame
, this_cache
);
2564 gdb_assert (regnum
>= 0);
2566 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2567 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2569 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2570 return frame_unwind_got_memory (this_frame
, regnum
,
2571 cache
->saved_regs
[regnum
]);
2573 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2576 static const struct frame_unwind amd64_frame_unwind
=
2579 amd64_frame_unwind_stop_reason
,
2580 amd64_frame_this_id
,
2581 amd64_frame_prev_register
,
2583 default_frame_sniffer
2586 /* Generate a bytecode expression to get the value of the saved PC. */
2589 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2590 struct agent_expr
*ax
, struct axs_value
*value
,
2593 /* The following sequence assumes the traditional use of the base
2595 ax_reg (ax
, AMD64_RBP_REGNUM
);
2597 ax_simple (ax
, aop_add
);
2598 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2599 value
->kind
= axs_lvalue_memory
;
2603 /* Signal trampolines. */
2605 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2606 64-bit variants. This would require using identical frame caches
2607 on both platforms. */
2609 static struct amd64_frame_cache
*
2610 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2612 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2613 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2614 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2615 struct amd64_frame_cache
*cache
;
2621 return (struct amd64_frame_cache
*) *this_cache
;
2623 cache
= amd64_alloc_frame_cache ();
2627 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2628 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2630 addr
= tdep
->sigcontext_addr (this_frame
);
2631 gdb_assert (tdep
->sc_reg_offset
);
2632 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2633 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2634 if (tdep
->sc_reg_offset
[i
] != -1)
2635 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2639 CATCH (ex
, RETURN_MASK_ERROR
)
2641 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2642 throw_exception (ex
);
2646 *this_cache
= cache
;
2650 static enum unwind_stop_reason
2651 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2654 struct amd64_frame_cache
*cache
=
2655 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2658 return UNWIND_UNAVAILABLE
;
2660 return UNWIND_NO_REASON
;
2664 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2665 void **this_cache
, struct frame_id
*this_id
)
2667 struct amd64_frame_cache
*cache
=
2668 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2671 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2672 else if (cache
->base
== 0)
2674 /* This marks the outermost frame. */
2678 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2681 static struct value
*
2682 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2683 void **this_cache
, int regnum
)
2685 /* Make sure we've initialized the cache. */
2686 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2688 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2692 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2693 struct frame_info
*this_frame
,
2696 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2698 /* We shouldn't even bother if we don't have a sigcontext_addr
2700 if (tdep
->sigcontext_addr
== NULL
)
2703 if (tdep
->sigtramp_p
!= NULL
)
2705 if (tdep
->sigtramp_p (this_frame
))
2709 if (tdep
->sigtramp_start
!= 0)
2711 CORE_ADDR pc
= get_frame_pc (this_frame
);
2713 gdb_assert (tdep
->sigtramp_end
!= 0);
2714 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2721 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2724 amd64_sigtramp_frame_unwind_stop_reason
,
2725 amd64_sigtramp_frame_this_id
,
2726 amd64_sigtramp_frame_prev_register
,
2728 amd64_sigtramp_frame_sniffer
2733 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2735 struct amd64_frame_cache
*cache
=
2736 amd64_frame_cache (this_frame
, this_cache
);
2741 static const struct frame_base amd64_frame_base
=
2743 &amd64_frame_unwind
,
2744 amd64_frame_base_address
,
2745 amd64_frame_base_address
,
2746 amd64_frame_base_address
2749 /* Normal frames, but in a function epilogue. */
2751 /* Implement the stack_frame_destroyed_p gdbarch method.
2753 The epilogue is defined here as the 'ret' instruction, which will
2754 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2755 the function's stack frame. */
2758 amd64_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2761 struct compunit_symtab
*cust
;
2763 cust
= find_pc_compunit_symtab (pc
);
2764 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2767 if (target_read_memory (pc
, &insn
, 1))
2768 return 0; /* Can't read memory at pc. */
2770 if (insn
!= 0xc3) /* 'ret' instruction. */
2777 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2778 struct frame_info
*this_frame
,
2779 void **this_prologue_cache
)
2781 if (frame_relative_level (this_frame
) == 0)
2782 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2783 get_frame_pc (this_frame
));
2788 static struct amd64_frame_cache
*
2789 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2791 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2792 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2793 struct amd64_frame_cache
*cache
;
2797 return (struct amd64_frame_cache
*) *this_cache
;
2799 cache
= amd64_alloc_frame_cache ();
2800 *this_cache
= cache
;
2804 /* Cache base will be %esp plus cache->sp_offset (-8). */
2805 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2806 cache
->base
= extract_unsigned_integer (buf
, 8,
2807 byte_order
) + cache
->sp_offset
;
2809 /* Cache pc will be the frame func. */
2810 cache
->pc
= get_frame_pc (this_frame
);
2812 /* The saved %esp will be at cache->base plus 16. */
2813 cache
->saved_sp
= cache
->base
+ 16;
2815 /* The saved %eip will be at cache->base plus 8. */
2816 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2820 CATCH (ex
, RETURN_MASK_ERROR
)
2822 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2823 throw_exception (ex
);
2830 static enum unwind_stop_reason
2831 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2834 struct amd64_frame_cache
*cache
2835 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2838 return UNWIND_UNAVAILABLE
;
2840 return UNWIND_NO_REASON
;
2844 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2846 struct frame_id
*this_id
)
2848 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2852 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2854 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2857 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2860 amd64_epilogue_frame_unwind_stop_reason
,
2861 amd64_epilogue_frame_this_id
,
2862 amd64_frame_prev_register
,
2864 amd64_epilogue_frame_sniffer
2867 static struct frame_id
2868 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2872 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2874 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2877 /* 16 byte align the SP per frame requirements. */
2880 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2882 return sp
& -(CORE_ADDR
)16;
2886 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2887 in the floating-point register set REGSET to register cache
2888 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2891 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2892 int regnum
, const void *fpregs
, size_t len
)
2894 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2895 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2897 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2898 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
2901 /* Collect register REGNUM from the register cache REGCACHE and store
2902 it in the buffer specified by FPREGS and LEN as described by the
2903 floating-point register set REGSET. If REGNUM is -1, do this for
2904 all registers in REGSET. */
2907 amd64_collect_fpregset (const struct regset
*regset
,
2908 const struct regcache
*regcache
,
2909 int regnum
, void *fpregs
, size_t len
)
2911 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2912 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2914 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2915 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
2918 const struct regset amd64_fpregset
=
2920 NULL
, amd64_supply_fpregset
, amd64_collect_fpregset
2924 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2925 %rdi. We expect its value to be a pointer to the jmp_buf structure
2926 from which we extract the address that we will land at. This
2927 address is copied into PC. This routine returns non-zero on
2931 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2935 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2936 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2937 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
2939 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2940 longjmp will land. */
2941 if (jb_pc_offset
== -1)
2944 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
2945 jb_addr
= extract_typed_address
2946 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
2947 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
2950 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
2955 static const int amd64_record_regmap
[] =
2957 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
2958 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
2959 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
2960 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
2961 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
2962 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
2966 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2968 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2969 const struct target_desc
*tdesc
= info
.target_desc
;
2970 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
2971 static const char *const stap_register_prefixes
[] = { "%", NULL
};
2972 static const char *const stap_register_indirection_prefixes
[] = { "(",
2974 static const char *const stap_register_indirection_suffixes
[] = { ")",
2977 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2978 floating-point registers. */
2979 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
2980 tdep
->fpregset
= &amd64_fpregset
;
2982 if (! tdesc_has_registers (tdesc
))
2983 tdesc
= tdesc_amd64
;
2984 tdep
->tdesc
= tdesc
;
2986 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
2987 tdep
->register_names
= amd64_register_names
;
2989 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512") != NULL
)
2991 tdep
->zmmh_register_names
= amd64_zmmh_names
;
2992 tdep
->k_register_names
= amd64_k_names
;
2993 tdep
->xmm_avx512_register_names
= amd64_xmm_avx512_names
;
2994 tdep
->ymm16h_register_names
= amd64_ymmh_avx512_names
;
2996 tdep
->num_zmm_regs
= 32;
2997 tdep
->num_xmm_avx512_regs
= 16;
2998 tdep
->num_ymm_avx512_regs
= 16;
3000 tdep
->zmm0h_regnum
= AMD64_ZMM0H_REGNUM
;
3001 tdep
->k0_regnum
= AMD64_K0_REGNUM
;
3002 tdep
->xmm16_regnum
= AMD64_XMM16_REGNUM
;
3003 tdep
->ymm16h_regnum
= AMD64_YMM16H_REGNUM
;
3006 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
3008 tdep
->ymmh_register_names
= amd64_ymmh_names
;
3009 tdep
->num_ymm_regs
= 16;
3010 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
3013 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
)
3015 tdep
->mpx_register_names
= amd64_mpx_names
;
3016 tdep
->bndcfgu_regnum
= AMD64_BNDCFGU_REGNUM
;
3017 tdep
->bnd0r_regnum
= AMD64_BND0R_REGNUM
;
3020 tdep
->num_byte_regs
= 20;
3021 tdep
->num_word_regs
= 16;
3022 tdep
->num_dword_regs
= 16;
3023 /* Avoid wiring in the MMX registers for now. */
3024 tdep
->num_mmx_regs
= 0;
3026 set_gdbarch_pseudo_register_read_value (gdbarch
,
3027 amd64_pseudo_register_read_value
);
3028 set_gdbarch_pseudo_register_write (gdbarch
,
3029 amd64_pseudo_register_write
);
3030 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
3031 amd64_ax_pseudo_register_collect
);
3033 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
3035 /* AMD64 has an FPU and 16 SSE registers. */
3036 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
3037 tdep
->num_xmm_regs
= 16;
3039 /* This is what all the fuss is about. */
3040 set_gdbarch_long_bit (gdbarch
, 64);
3041 set_gdbarch_long_long_bit (gdbarch
, 64);
3042 set_gdbarch_ptr_bit (gdbarch
, 64);
3044 /* In contrast to the i386, on AMD64 a `long double' actually takes
3045 up 128 bits, even though it's still based on the i387 extended
3046 floating-point format which has only 80 significant bits. */
3047 set_gdbarch_long_double_bit (gdbarch
, 128);
3049 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
3051 /* Register numbers of various important registers. */
3052 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
3053 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
3054 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
3055 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
3057 /* The "default" register numbering scheme for AMD64 is referred to
3058 as the "DWARF Register Number Mapping" in the System V psABI.
3059 The preferred debugging format for all known AMD64 targets is
3060 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3061 DWARF-1), but we provide the same mapping just in case. This
3062 mapping is also used for stabs, which GCC does support. */
3063 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3064 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3066 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3067 be in use on any of the supported AMD64 targets. */
3069 /* Call dummy code. */
3070 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
3071 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
3072 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
3074 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
3075 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
3076 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
3078 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
3080 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
3082 tdep
->record_regmap
= amd64_record_regmap
;
3084 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
3086 /* Hook the function epilogue frame unwinder. This unwinder is
3087 appended to the list first, so that it supercedes the other
3088 unwinders in function epilogues. */
3089 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
3091 /* Hook the prologue-based frame unwinders. */
3092 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
3093 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
3094 frame_base_set_default (gdbarch
, &amd64_frame_base
);
3096 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
3098 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
3100 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
3102 /* SystemTap variables and functions. */
3103 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
3104 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
3105 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
3106 stap_register_indirection_prefixes
);
3107 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
3108 stap_register_indirection_suffixes
);
3109 set_gdbarch_stap_is_single_operand (gdbarch
,
3110 i386_stap_is_single_operand
);
3111 set_gdbarch_stap_parse_special_token (gdbarch
,
3112 i386_stap_parse_special_token
);
3113 set_gdbarch_insn_is_call (gdbarch
, amd64_insn_is_call
);
3114 set_gdbarch_insn_is_ret (gdbarch
, amd64_insn_is_ret
);
3115 set_gdbarch_insn_is_jump (gdbarch
, amd64_insn_is_jump
);
3119 static struct type
*
3120 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3122 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3124 switch (regnum
- tdep
->eax_regnum
)
3126 case AMD64_RBP_REGNUM
: /* %ebp */
3127 case AMD64_RSP_REGNUM
: /* %esp */
3128 return builtin_type (gdbarch
)->builtin_data_ptr
;
3129 case AMD64_RIP_REGNUM
: /* %eip */
3130 return builtin_type (gdbarch
)->builtin_func_ptr
;
3133 return i386_pseudo_register_type (gdbarch
, regnum
);
3137 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3139 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3140 const struct target_desc
*tdesc
= info
.target_desc
;
3142 amd64_init_abi (info
, gdbarch
);
3144 if (! tdesc_has_registers (tdesc
))
3146 tdep
->tdesc
= tdesc
;
3148 tdep
->num_dword_regs
= 17;
3149 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
3151 set_gdbarch_long_bit (gdbarch
, 32);
3152 set_gdbarch_ptr_bit (gdbarch
, 32);
3155 /* Return the target description for a specified XSAVE feature mask. */
3157 const struct target_desc
*
3158 amd64_target_description (uint64_t xcr0
)
3160 switch (xcr0
& X86_XSTATE_ALL_MASK
)
3162 case X86_XSTATE_MPX_AVX512_MASK
:
3163 case X86_XSTATE_AVX512_MASK
:
3164 return tdesc_amd64_avx512
;
3165 case X86_XSTATE_MPX_MASK
:
3166 return tdesc_amd64_mpx
;
3167 case X86_XSTATE_AVX_MPX_MASK
:
3168 return tdesc_amd64_avx_mpx
;
3169 case X86_XSTATE_AVX_MASK
:
3170 return tdesc_amd64_avx
;
3176 /* Provide a prototype to silence -Wmissing-prototypes. */
3177 void _initialize_amd64_tdep (void);
3180 _initialize_amd64_tdep (void)
3182 initialize_tdesc_amd64 ();
3183 initialize_tdesc_amd64_avx ();
3184 initialize_tdesc_amd64_mpx ();
3185 initialize_tdesc_amd64_avx_mpx ();
3186 initialize_tdesc_amd64_avx512 ();
3188 initialize_tdesc_x32 ();
3189 initialize_tdesc_x32_avx ();
3190 initialize_tdesc_x32_avx512 ();
3194 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3195 sense that the instruction pointer and data pointer are simply
3196 64-bit offsets into the code segment and the data segment instead
3197 of a selector offset pair. The functions below store the upper 32
3198 bits of these pointers (instead of just the 16-bits of the segment
3201 /* Fill register REGNUM in REGCACHE with the appropriate
3202 floating-point or SSE register value from *FXSAVE. If REGNUM is
3203 -1, do this for all registers. This function masks off any of the
3204 reserved bits in *FXSAVE. */
3207 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3210 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3211 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3213 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3216 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3218 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
3220 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3221 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3222 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3223 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3227 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3230 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3233 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3234 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3236 i387_supply_xsave (regcache
, regnum
, xsave
);
3239 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3241 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
3243 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3244 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
),
3246 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3247 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
),
3252 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3253 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3254 all registers. This function doesn't touch any of the reserved
3258 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3261 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3262 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3263 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
3265 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3267 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3269 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3270 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3271 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3272 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3276 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3279 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3280 void *xsave
, int gcore
)
3282 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3283 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3284 gdb_byte
*regs
= (gdb_byte
*) xsave
;
3286 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3288 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3290 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3291 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
),
3293 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3294 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
),