1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 Contributed by Jiri Smid, SuSE Labs.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "opcode/i386.h"
26 #include "arch-utils.h"
28 #include "dummy-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
40 #include "gdb_assert.h"
42 #include "amd64-tdep.h"
43 #include "i387-tdep.h"
45 /* Note that the AMD64 architecture was previously known as x86-64.
46 The latter is (forever) engraved into the canonical system name as
47 returned by config.guess, and used as the name for the AMD64 port
48 of GNU/Linux. The BSD's have renamed their ports to amd64; they
49 don't like to shout. For GDB we prefer the amd64_-prefix over the
50 x86_64_-prefix since it's so much easier to type. */
52 /* Register information. */
54 static const char *amd64_register_names
[] =
56 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
58 /* %r8 is indeed register number 8. */
59 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
60 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
62 /* %st0 is register number 24. */
63 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
64 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
66 /* %xmm0 is register number 40. */
67 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
68 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
72 /* Total number of registers. */
73 #define AMD64_NUM_REGS ARRAY_SIZE (amd64_register_names)
75 /* The registers used to pass integer arguments during a function call. */
76 static int amd64_dummy_call_integer_regs
[] =
78 AMD64_RDI_REGNUM
, /* %rdi */
79 AMD64_RSI_REGNUM
, /* %rsi */
80 AMD64_RDX_REGNUM
, /* %rdx */
81 AMD64_RCX_REGNUM
, /* %rcx */
86 /* Return the name of register REGNUM. */
89 amd64_register_name (struct gdbarch
*gdbarch
, int regnum
)
91 if (regnum
>= 0 && regnum
< AMD64_NUM_REGS
)
92 return amd64_register_names
[regnum
];
97 /* Return the GDB type object for the "standard" data type of data in
101 amd64_register_type (struct gdbarch
*gdbarch
, int regnum
)
103 if (regnum
>= AMD64_RAX_REGNUM
&& regnum
<= AMD64_RDI_REGNUM
)
104 return builtin_type (gdbarch
)->builtin_int64
;
105 if (regnum
== AMD64_RBP_REGNUM
|| regnum
== AMD64_RSP_REGNUM
)
106 return builtin_type (gdbarch
)->builtin_data_ptr
;
107 if (regnum
>= AMD64_R8_REGNUM
&& regnum
<= AMD64_R15_REGNUM
)
108 return builtin_type (gdbarch
)->builtin_int64
;
109 if (regnum
== AMD64_RIP_REGNUM
)
110 return builtin_type (gdbarch
)->builtin_func_ptr
;
111 if (regnum
== AMD64_EFLAGS_REGNUM
)
112 return i386_eflags_type (gdbarch
);
113 if (regnum
>= AMD64_CS_REGNUM
&& regnum
<= AMD64_GS_REGNUM
)
114 return builtin_type (gdbarch
)->builtin_int32
;
115 if (regnum
>= AMD64_ST0_REGNUM
&& regnum
<= AMD64_ST0_REGNUM
+ 7)
116 return i387_ext_type (gdbarch
);
117 if (regnum
>= AMD64_FCTRL_REGNUM
&& regnum
<= AMD64_FCTRL_REGNUM
+ 7)
118 return builtin_type (gdbarch
)->builtin_int32
;
119 if (regnum
>= AMD64_XMM0_REGNUM
&& regnum
<= AMD64_XMM0_REGNUM
+ 15)
120 return i386_sse_type (gdbarch
);
121 if (regnum
== AMD64_MXCSR_REGNUM
)
122 return i386_mxcsr_type (gdbarch
);
124 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
127 /* DWARF Register Number Mapping as defined in the System V psABI,
130 static int amd64_dwarf_regmap
[] =
132 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
133 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
134 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
135 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
137 /* Frame Pointer Register RBP. */
140 /* Stack Pointer Register RSP. */
143 /* Extended Integer Registers 8 - 15. */
144 8, 9, 10, 11, 12, 13, 14, 15,
146 /* Return Address RA. Mapped to RIP. */
149 /* SSE Registers 0 - 7. */
150 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
151 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
152 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
153 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
155 /* Extended SSE Registers 8 - 15. */
156 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
157 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
158 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
159 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
161 /* Floating Point Registers 0-7. */
162 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
163 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
164 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
165 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
167 /* Control and Status Flags Register. */
170 /* Selector Registers. */
180 /* Segment Base Address Registers. */
186 /* Special Selector Registers. */
190 /* Floating Point Control Registers. */
196 static const int amd64_dwarf_regmap_len
=
197 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
199 /* Convert DWARF register number REG to the appropriate register
200 number used by GDB. */
203 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
207 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
208 regnum
= amd64_dwarf_regmap
[reg
];
211 warning (_("Unmapped DWARF Register #%d encountered."), reg
);
216 /* Map architectural register numbers to gdb register numbers. */
218 static const int amd64_arch_regmap
[16] =
220 AMD64_RAX_REGNUM
, /* %rax */
221 AMD64_RCX_REGNUM
, /* %rcx */
222 AMD64_RDX_REGNUM
, /* %rdx */
223 AMD64_RBX_REGNUM
, /* %rbx */
224 AMD64_RSP_REGNUM
, /* %rsp */
225 AMD64_RBP_REGNUM
, /* %rbp */
226 AMD64_RSI_REGNUM
, /* %rsi */
227 AMD64_RDI_REGNUM
, /* %rdi */
228 AMD64_R8_REGNUM
, /* %r8 */
229 AMD64_R9_REGNUM
, /* %r9 */
230 AMD64_R10_REGNUM
, /* %r10 */
231 AMD64_R11_REGNUM
, /* %r11 */
232 AMD64_R12_REGNUM
, /* %r12 */
233 AMD64_R13_REGNUM
, /* %r13 */
234 AMD64_R14_REGNUM
, /* %r14 */
235 AMD64_R15_REGNUM
/* %r15 */
238 static const int amd64_arch_regmap_len
=
239 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
241 /* Convert architectural register number REG to the appropriate register
242 number used by GDB. */
245 amd64_arch_reg_to_regnum (int reg
)
247 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
249 return amd64_arch_regmap
[reg
];
254 /* Return the union class of CLASS1 and CLASS2. See the psABI for
257 static enum amd64_reg_class
258 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
260 /* Rule (a): If both classes are equal, this is the resulting class. */
261 if (class1
== class2
)
264 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
265 is the other class. */
266 if (class1
== AMD64_NO_CLASS
)
268 if (class2
== AMD64_NO_CLASS
)
271 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
272 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
275 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
276 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
277 return AMD64_INTEGER
;
279 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
280 MEMORY is used as class. */
281 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
282 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
283 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
286 /* Rule (f): Otherwise class SSE is used. */
290 /* Return non-zero if TYPE is a non-POD structure or union type. */
293 amd64_non_pod_p (struct type
*type
)
295 /* ??? A class with a base class certainly isn't POD, but does this
296 catch all non-POD structure types? */
297 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
303 /* Classify TYPE according to the rules for aggregate (structures and
304 arrays) and union types, and store the result in CLASS. */
307 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class
class[2])
309 int len
= TYPE_LENGTH (type
);
311 /* 1. If the size of an object is larger than two eightbytes, or in
312 C++, is a non-POD structure or union type, or contains
313 unaligned fields, it has class memory. */
314 if (len
> 16 || amd64_non_pod_p (type
))
316 class[0] = class[1] = AMD64_MEMORY
;
320 /* 2. Both eightbytes get initialized to class NO_CLASS. */
321 class[0] = class[1] = AMD64_NO_CLASS
;
323 /* 3. Each field of an object is classified recursively so that
324 always two fields are considered. The resulting class is
325 calculated according to the classes of the fields in the
328 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
330 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
332 /* All fields in an array have the same type. */
333 amd64_classify (subtype
, class);
334 if (len
> 8 && class[1] == AMD64_NO_CLASS
)
341 /* Structure or union. */
342 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
343 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
345 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
347 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
348 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
349 enum amd64_reg_class subclass
[2];
350 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
354 bitsize
= TYPE_LENGTH (subtype
) * 8;
355 endpos
= (TYPE_FIELD_BITPOS (type
, i
) + bitsize
- 1) / 64;
357 /* Ignore static fields. */
358 if (field_is_static (&TYPE_FIELD (type
, i
)))
361 gdb_assert (pos
== 0 || pos
== 1);
363 amd64_classify (subtype
, subclass
);
364 class[pos
] = amd64_merge_classes (class[pos
], subclass
[0]);
365 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
366 /* This is a bit of an odd case: We have a field that would
367 normally fit in one of the two eightbytes, except that
368 it is placed in a way that this field straddles them.
369 This has been seen with a structure containing an array.
371 The ABI is a bit unclear in this case, but we assume that
372 this field's class (stored in subclass[0]) must also be merged
373 into class[1]. In other words, our field has a piece stored
374 in the second eight-byte, and thus its class applies to
375 the second eight-byte as well.
377 In the case where the field length exceeds 8 bytes,
378 it should not be necessary to merge the field class
379 into class[1]. As LEN > 8, subclass[1] is necessarily
380 different from AMD64_NO_CLASS. If subclass[1] is equal
381 to subclass[0], then the normal class[1]/subclass[1]
382 merging will take care of everything. For subclass[1]
383 to be different from subclass[0], I can only see the case
384 where we have a SSE/SSEUP or X87/X87UP pair, which both
385 use up all 16 bytes of the aggregate, and are already
386 handled just fine (because each portion sits on its own
388 class[1] = amd64_merge_classes (class[1], subclass
[0]);
390 class[1] = amd64_merge_classes (class[1], subclass
[1]);
394 /* 4. Then a post merger cleanup is done: */
396 /* Rule (a): If one of the classes is MEMORY, the whole argument is
398 if (class[0] == AMD64_MEMORY
|| class[1] == AMD64_MEMORY
)
399 class[0] = class[1] = AMD64_MEMORY
;
401 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
403 if (class[0] == AMD64_SSEUP
)
404 class[0] = AMD64_SSE
;
405 if (class[1] == AMD64_SSEUP
&& class[0] != AMD64_SSE
)
406 class[1] = AMD64_SSE
;
409 /* Classify TYPE, and store the result in CLASS. */
412 amd64_classify (struct type
*type
, enum amd64_reg_class
class[2])
414 enum type_code code
= TYPE_CODE (type
);
415 int len
= TYPE_LENGTH (type
);
417 class[0] = class[1] = AMD64_NO_CLASS
;
419 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
420 long, long long, and pointers are in the INTEGER class. Similarly,
421 range types, used by languages such as Ada, are also in the INTEGER
423 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
424 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
425 || code
== TYPE_CODE_CHAR
426 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
427 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
428 class[0] = AMD64_INTEGER
;
430 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
432 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
433 && (len
== 4 || len
== 8))
435 class[0] = AMD64_SSE
;
437 /* Arguments of types __float128, _Decimal128 and __m128 are split into
438 two halves. The least significant ones belong to class SSE, the most
439 significant one to class SSEUP. */
440 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
441 /* FIXME: __float128, __m128. */
442 class[0] = AMD64_SSE
, class[1] = AMD64_SSEUP
;
444 /* The 64-bit mantissa of arguments of type long double belongs to
445 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
447 else if (code
== TYPE_CODE_FLT
&& len
== 16)
448 /* Class X87 and X87UP. */
449 class[0] = AMD64_X87
, class[1] = AMD64_X87UP
;
452 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
453 || code
== TYPE_CODE_UNION
)
454 amd64_classify_aggregate (type
, class);
457 static enum return_value_convention
458 amd64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
459 struct type
*type
, struct regcache
*regcache
,
460 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
462 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
463 enum amd64_reg_class
class[2];
464 int len
= TYPE_LENGTH (type
);
465 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
466 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
471 gdb_assert (!(readbuf
&& writebuf
));
472 gdb_assert (tdep
->classify
);
474 /* 1. Classify the return type with the classification algorithm. */
475 tdep
->classify (type
, class);
477 /* 2. If the type has class MEMORY, then the caller provides space
478 for the return value and passes the address of this storage in
479 %rdi as if it were the first argument to the function. In effect,
480 this address becomes a hidden first argument.
482 On return %rax will contain the address that has been passed in
483 by the caller in %rdi. */
484 if (class[0] == AMD64_MEMORY
)
486 /* As indicated by the comment above, the ABI guarantees that we
487 can always find the return value just after the function has
494 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
495 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
498 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
501 gdb_assert (class[1] != AMD64_MEMORY
);
502 gdb_assert (len
<= 16);
504 for (i
= 0; len
> 0; i
++, len
-= 8)
512 /* 3. If the class is INTEGER, the next available register
513 of the sequence %rax, %rdx is used. */
514 regnum
= integer_regnum
[integer_reg
++];
518 /* 4. If the class is SSE, the next available SSE register
519 of the sequence %xmm0, %xmm1 is used. */
520 regnum
= sse_regnum
[sse_reg
++];
524 /* 5. If the class is SSEUP, the eightbyte is passed in the
525 upper half of the last used SSE register. */
526 gdb_assert (sse_reg
> 0);
527 regnum
= sse_regnum
[sse_reg
- 1];
532 /* 6. If the class is X87, the value is returned on the X87
533 stack in %st0 as 80-bit x87 number. */
534 regnum
= AMD64_ST0_REGNUM
;
536 i387_return_value (gdbarch
, regcache
);
540 /* 7. If the class is X87UP, the value is returned together
541 with the previous X87 value in %st0. */
542 gdb_assert (i
> 0 && class[0] == AMD64_X87
);
543 regnum
= AMD64_ST0_REGNUM
;
552 gdb_assert (!"Unexpected register class.");
555 gdb_assert (regnum
!= -1);
558 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
561 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
565 return RETURN_VALUE_REGISTER_CONVENTION
;
570 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
571 struct value
**args
, CORE_ADDR sp
, int struct_return
)
573 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
574 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
575 int *integer_regs
= tdep
->call_dummy_integer_regs
;
576 int num_integer_regs
= tdep
->call_dummy_num_integer_regs
;
578 static int sse_regnum
[] =
580 /* %xmm0 ... %xmm7 */
581 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
582 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
583 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
584 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
586 struct value
**stack_args
= alloca (nargs
* sizeof (struct value
*));
587 /* An array that mirrors the stack_args array. For all arguments
588 that are passed by MEMORY, if that argument's address also needs
589 to be stored in a register, the ARG_ADDR_REGNO array will contain
590 that register number (or a negative value otherwise). */
591 int *arg_addr_regno
= alloca (nargs
* sizeof (int));
592 int num_stack_args
= 0;
593 int num_elements
= 0;
599 gdb_assert (tdep
->classify
);
601 /* Reserve a register for the "hidden" argument. */
605 for (i
= 0; i
< nargs
; i
++)
607 struct type
*type
= value_type (args
[i
]);
608 int len
= TYPE_LENGTH (type
);
609 enum amd64_reg_class
class[2];
610 int needed_integer_regs
= 0;
611 int needed_sse_regs
= 0;
614 /* Classify argument. */
615 tdep
->classify (type
, class);
617 /* Calculate the number of integer and SSE registers needed for
619 for (j
= 0; j
< 2; j
++)
621 if (class[j
] == AMD64_INTEGER
)
622 needed_integer_regs
++;
623 else if (class[j
] == AMD64_SSE
)
627 /* Check whether enough registers are available, and if the
628 argument should be passed in registers at all. */
629 if (integer_reg
+ needed_integer_regs
> num_integer_regs
630 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
631 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
633 /* The argument will be passed on the stack. */
634 num_elements
+= ((len
+ 7) / 8);
635 stack_args
[num_stack_args
] = args
[i
];
636 /* If this is an AMD64_MEMORY argument whose address must also
637 be passed in one of the integer registers, reserve that
638 register and associate this value to that register so that
639 we can store the argument address as soon as we know it. */
640 if (class[0] == AMD64_MEMORY
641 && tdep
->memory_args_by_pointer
642 && integer_reg
< tdep
->call_dummy_num_integer_regs
)
643 arg_addr_regno
[num_stack_args
] =
644 tdep
->call_dummy_integer_regs
[integer_reg
++];
646 arg_addr_regno
[num_stack_args
] = -1;
651 /* The argument will be passed in registers. */
652 const gdb_byte
*valbuf
= value_contents (args
[i
]);
655 gdb_assert (len
<= 16);
657 for (j
= 0; len
> 0; j
++, len
-= 8)
665 regnum
= integer_regs
[integer_reg
++];
669 regnum
= sse_regnum
[sse_reg
++];
673 gdb_assert (sse_reg
> 0);
674 regnum
= sse_regnum
[sse_reg
- 1];
679 gdb_assert (!"Unexpected register class.");
682 gdb_assert (regnum
!= -1);
683 memset (buf
, 0, sizeof buf
);
684 memcpy (buf
, valbuf
+ j
* 8, min (len
, 8));
685 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
690 /* Allocate space for the arguments on the stack. */
691 sp
-= num_elements
* 8;
693 /* The psABI says that "The end of the input argument area shall be
694 aligned on a 16 byte boundary." */
697 /* Write out the arguments to the stack. */
698 for (i
= 0; i
< num_stack_args
; i
++)
700 struct type
*type
= value_type (stack_args
[i
]);
701 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
702 int len
= TYPE_LENGTH (type
);
703 CORE_ADDR arg_addr
= sp
+ element
* 8;
705 write_memory (arg_addr
, valbuf
, len
);
706 if (arg_addr_regno
[i
] >= 0)
708 /* We also need to store the address of that argument in
709 the given register. */
711 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
713 store_unsigned_integer (buf
, 8, byte_order
, arg_addr
);
714 regcache_cooked_write (regcache
, arg_addr_regno
[i
], buf
);
716 element
+= ((len
+ 7) / 8);
719 /* The psABI says that "For calls that may call functions that use
720 varargs or stdargs (prototype-less calls or calls to functions
721 containing ellipsis (...) in the declaration) %al is used as
722 hidden argument to specify the number of SSE registers used. */
723 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
728 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
729 struct regcache
*regcache
, CORE_ADDR bp_addr
,
730 int nargs
, struct value
**args
, CORE_ADDR sp
,
731 int struct_return
, CORE_ADDR struct_addr
)
733 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
734 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
737 /* Pass arguments. */
738 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, struct_return
);
740 /* Pass "hidden" argument". */
743 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
744 /* The "hidden" argument is passed throught the first argument
746 const int arg_regnum
= tdep
->call_dummy_integer_regs
[0];
748 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
749 regcache_cooked_write (regcache
, arg_regnum
, buf
);
752 /* Reserve some memory on the stack for the integer-parameter registers,
753 if required by the ABI. */
754 if (tdep
->integer_param_regs_saved_in_caller_frame
)
755 sp
-= tdep
->call_dummy_num_integer_regs
* 8;
757 /* Store return address. */
759 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
760 write_memory (sp
, buf
, 8);
762 /* Finally, update the stack pointer... */
763 store_unsigned_integer (buf
, 8, byte_order
, sp
);
764 regcache_cooked_write (regcache
, AMD64_RSP_REGNUM
, buf
);
766 /* ...and fake a frame pointer. */
767 regcache_cooked_write (regcache
, AMD64_RBP_REGNUM
, buf
);
772 /* Displaced instruction handling. */
774 /* A partially decoded instruction.
775 This contains enough details for displaced stepping purposes. */
779 /* The number of opcode bytes. */
781 /* The offset of the rex prefix or -1 if not present. */
783 /* The offset to the first opcode byte. */
785 /* The offset to the modrm byte or -1 if not present. */
788 /* The raw instruction. */
792 struct displaced_step_closure
794 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
799 /* Details of the instruction. */
800 struct amd64_insn insn_details
;
802 /* Amount of space allocated to insn_buf. */
805 /* The possibly modified insn.
806 This is a variable-length field. */
807 gdb_byte insn_buf
[1];
810 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
811 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
812 at which point delete these in favor of libopcodes' versions). */
814 static const unsigned char onebyte_has_modrm
[256] = {
815 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
816 /* ------------------------------- */
817 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
818 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
819 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
820 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
821 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
822 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
823 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
824 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
825 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
826 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
827 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
828 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
829 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
830 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
831 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
832 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
833 /* ------------------------------- */
834 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
837 static const unsigned char twobyte_has_modrm
[256] = {
838 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
839 /* ------------------------------- */
840 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
841 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
842 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
843 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
844 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
845 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
846 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
847 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
848 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
849 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
850 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
851 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
852 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
853 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
854 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
855 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
856 /* ------------------------------- */
857 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
860 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
863 rex_prefix_p (gdb_byte pfx
)
865 return REX_PREFIX_P (pfx
);
868 /* Skip the legacy instruction prefixes in INSN.
869 We assume INSN is properly sentineled so we don't have to worry
870 about falling off the end of the buffer. */
873 amd64_skip_prefixes (gdb_byte
*insn
)
879 case DATA_PREFIX_OPCODE
:
880 case ADDR_PREFIX_OPCODE
:
881 case CS_PREFIX_OPCODE
:
882 case DS_PREFIX_OPCODE
:
883 case ES_PREFIX_OPCODE
:
884 case FS_PREFIX_OPCODE
:
885 case GS_PREFIX_OPCODE
:
886 case SS_PREFIX_OPCODE
:
887 case LOCK_PREFIX_OPCODE
:
888 case REPE_PREFIX_OPCODE
:
889 case REPNE_PREFIX_OPCODE
:
901 /* fprintf-function for amd64_insn_length.
902 This function is a nop, we don't want to print anything, we just want to
903 compute the length of the insn. */
905 static int ATTR_FORMAT (printf
, 2, 3)
906 amd64_insn_length_fprintf (void *stream
, const char *format
, ...)
911 /* Initialize a struct disassemble_info for amd64_insn_length. */
914 amd64_insn_length_init_dis (struct gdbarch
*gdbarch
,
915 struct disassemble_info
*di
,
916 const gdb_byte
*insn
, int max_len
,
919 init_disassemble_info (di
, NULL
, amd64_insn_length_fprintf
);
921 /* init_disassemble_info installs buffer_read_memory, etc.
922 so we don't need to do that here.
923 The cast is necessary until disassemble_info is const-ified. */
924 di
->buffer
= (gdb_byte
*) insn
;
925 di
->buffer_length
= max_len
;
926 di
->buffer_vma
= addr
;
928 di
->arch
= gdbarch_bfd_arch_info (gdbarch
)->arch
;
929 di
->mach
= gdbarch_bfd_arch_info (gdbarch
)->mach
;
930 di
->endian
= gdbarch_byte_order (gdbarch
);
931 di
->endian_code
= gdbarch_byte_order_for_code (gdbarch
);
933 disassemble_init_for_target (di
);
936 /* Return the length in bytes of INSN.
937 MAX_LEN is the size of the buffer containing INSN.
938 libopcodes currently doesn't export a utility to compute the
939 instruction length, so use the disassembler until then. */
942 amd64_insn_length (struct gdbarch
*gdbarch
,
943 const gdb_byte
*insn
, int max_len
, CORE_ADDR addr
)
945 struct disassemble_info di
;
947 amd64_insn_length_init_dis (gdbarch
, &di
, insn
, max_len
, addr
);
949 return gdbarch_print_insn (gdbarch
, addr
, &di
);
952 /* Return an integer register (other than RSP) that is unused as an input
954 In order to not require adding a rex prefix if the insn doesn't already
955 have one, the result is restricted to RAX ... RDI, sans RSP.
956 The register numbering of the result follows architecture ordering,
960 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
962 /* 1 bit for each reg */
963 int used_regs_mask
= 0;
965 /* There can be at most 3 int regs used as inputs in an insn, and we have
966 7 to choose from (RAX ... RDI, sans RSP).
967 This allows us to take a conservative approach and keep things simple.
968 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
969 that implicitly specify RAX. */
972 used_regs_mask
|= 1 << EAX_REG_NUM
;
973 /* Similarily avoid RDX, implicit operand in divides. */
974 used_regs_mask
|= 1 << EDX_REG_NUM
;
976 used_regs_mask
|= 1 << ESP_REG_NUM
;
978 /* If the opcode is one byte long and there's no ModRM byte,
979 assume the opcode specifies a register. */
980 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
981 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
983 /* Mark used regs in the modrm/sib bytes. */
984 if (details
->modrm_offset
!= -1)
986 int modrm
= details
->raw_insn
[details
->modrm_offset
];
987 int mod
= MODRM_MOD_FIELD (modrm
);
988 int reg
= MODRM_REG_FIELD (modrm
);
989 int rm
= MODRM_RM_FIELD (modrm
);
990 int have_sib
= mod
!= 3 && rm
== 4;
992 /* Assume the reg field of the modrm byte specifies a register. */
993 used_regs_mask
|= 1 << reg
;
997 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
998 int index
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
999 used_regs_mask
|= 1 << base
;
1000 used_regs_mask
|= 1 << index
;
1004 used_regs_mask
|= 1 << rm
;
1008 gdb_assert (used_regs_mask
< 256);
1009 gdb_assert (used_regs_mask
!= 255);
1011 /* Finally, find a free reg. */
1015 for (i
= 0; i
< 8; ++i
)
1017 if (! (used_regs_mask
& (1 << i
)))
1021 /* We shouldn't get here. */
1022 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1026 /* Extract the details of INSN that we need. */
1029 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1031 gdb_byte
*start
= insn
;
1034 details
->raw_insn
= insn
;
1036 details
->opcode_len
= -1;
1037 details
->rex_offset
= -1;
1038 details
->opcode_offset
= -1;
1039 details
->modrm_offset
= -1;
1041 /* Skip legacy instruction prefixes. */
1042 insn
= amd64_skip_prefixes (insn
);
1044 /* Skip REX instruction prefix. */
1045 if (rex_prefix_p (*insn
))
1047 details
->rex_offset
= insn
- start
;
1051 details
->opcode_offset
= insn
- start
;
1053 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1055 /* Two or three-byte opcode. */
1057 need_modrm
= twobyte_has_modrm
[*insn
];
1059 /* Check for three-byte opcode. */
1069 details
->opcode_len
= 3;
1072 details
->opcode_len
= 2;
1078 /* One-byte opcode. */
1079 need_modrm
= onebyte_has_modrm
[*insn
];
1080 details
->opcode_len
= 1;
1086 details
->modrm_offset
= insn
- start
;
1090 /* Update %rip-relative addressing in INSN.
1092 %rip-relative addressing only uses a 32-bit displacement.
1093 32 bits is not enough to be guaranteed to cover the distance between where
1094 the real instruction is and where its copy is.
1095 Convert the insn to use base+disp addressing.
1096 We set base = pc + insn_length so we can leave disp unchanged. */
1099 fixup_riprel (struct gdbarch
*gdbarch
, struct displaced_step_closure
*dsc
,
1100 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1102 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1103 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1104 int modrm_offset
= insn_details
->modrm_offset
;
1105 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1109 int arch_tmp_regno
, tmp_regno
;
1110 ULONGEST orig_value
;
1112 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1115 /* Compute the rip-relative address. */
1116 disp
= extract_signed_integer (insn
, sizeof (int32_t), byte_order
);
1117 insn_length
= amd64_insn_length (gdbarch
, dsc
->insn_buf
, dsc
->max_len
, from
);
1118 rip_base
= from
+ insn_length
;
1120 /* We need a register to hold the address.
1121 Pick one not used in the insn.
1122 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1123 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1124 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1126 /* REX.B should be unset as we were using rip-relative addressing,
1127 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1128 if (insn_details
->rex_offset
!= -1)
1129 dsc
->insn_buf
[insn_details
->rex_offset
] &= ~REX_B
;
1131 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1132 dsc
->tmp_regno
= tmp_regno
;
1133 dsc
->tmp_save
= orig_value
;
1136 /* Convert the ModRM field to be base+disp. */
1137 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1138 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1140 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1142 if (debug_displaced
)
1143 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1144 "displaced: using temp reg %d, old value %s, new value %s\n",
1145 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1146 paddress (gdbarch
, rip_base
));
1150 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1151 struct displaced_step_closure
*dsc
,
1152 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1154 const struct amd64_insn
*details
= &dsc
->insn_details
;
1156 if (details
->modrm_offset
!= -1)
1158 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1160 if ((modrm
& 0xc7) == 0x05)
1162 /* The insn uses rip-relative addressing.
1164 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1169 struct displaced_step_closure
*
1170 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1171 CORE_ADDR from
, CORE_ADDR to
,
1172 struct regcache
*regs
)
1174 int len
= gdbarch_max_insn_length (gdbarch
);
1175 /* Extra space for sentinels so fixup_{riprel,displaced_copy don't have to
1176 continually watch for running off the end of the buffer. */
1177 int fixup_sentinel_space
= len
;
1178 struct displaced_step_closure
*dsc
=
1179 xmalloc (sizeof (*dsc
) + len
+ fixup_sentinel_space
);
1180 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1181 struct amd64_insn
*details
= &dsc
->insn_details
;
1184 dsc
->max_len
= len
+ fixup_sentinel_space
;
1186 read_memory (from
, buf
, len
);
1188 /* Set up the sentinel space so we don't have to worry about running
1189 off the end of the buffer. An excessive number of leading prefixes
1190 could otherwise cause this. */
1191 memset (buf
+ len
, 0, fixup_sentinel_space
);
1193 amd64_get_insn_details (buf
, details
);
1195 /* GDB may get control back after the insn after the syscall.
1196 Presumably this is a kernel bug.
1197 If this is a syscall, make sure there's a nop afterwards. */
1201 if (amd64_syscall_p (details
, &syscall_length
))
1202 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1205 /* Modify the insn to cope with the address where it will be executed from.
1206 In particular, handle any rip-relative addressing. */
1207 fixup_displaced_copy (gdbarch
, dsc
, from
, to
, regs
);
1209 write_memory (to
, buf
, len
);
1211 if (debug_displaced
)
1213 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1214 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1215 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1222 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1224 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1226 if (insn
[0] == 0xff)
1228 /* jump near, absolute indirect (/4) */
1229 if ((insn
[1] & 0x38) == 0x20)
1232 /* jump far, absolute indirect (/5) */
1233 if ((insn
[1] & 0x38) == 0x28)
1241 amd64_absolute_call_p (const struct amd64_insn
*details
)
1243 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1245 if (insn
[0] == 0xff)
1247 /* Call near, absolute indirect (/2) */
1248 if ((insn
[1] & 0x38) == 0x10)
1251 /* Call far, absolute indirect (/3) */
1252 if ((insn
[1] & 0x38) == 0x18)
1260 amd64_ret_p (const struct amd64_insn
*details
)
1262 /* NOTE: gcc can emit "repz ; ret". */
1263 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1267 case 0xc2: /* ret near, pop N bytes */
1268 case 0xc3: /* ret near */
1269 case 0xca: /* ret far, pop N bytes */
1270 case 0xcb: /* ret far */
1271 case 0xcf: /* iret */
1280 amd64_call_p (const struct amd64_insn
*details
)
1282 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1284 if (amd64_absolute_call_p (details
))
1287 /* call near, relative */
1288 if (insn
[0] == 0xe8)
1294 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1295 length in bytes. Otherwise, return zero. */
1298 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1300 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1302 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1311 /* Fix up the state of registers and memory after having single-stepped
1312 a displaced instruction. */
1315 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1316 struct displaced_step_closure
*dsc
,
1317 CORE_ADDR from
, CORE_ADDR to
,
1318 struct regcache
*regs
)
1320 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1321 /* The offset we applied to the instruction's address. */
1322 ULONGEST insn_offset
= to
- from
;
1323 gdb_byte
*insn
= dsc
->insn_buf
;
1324 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1326 if (debug_displaced
)
1327 fprintf_unfiltered (gdb_stdlog
,
1328 "displaced: fixup (%s, %s), "
1329 "insn = 0x%02x 0x%02x ...\n",
1330 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1333 /* If we used a tmp reg, restore it. */
1337 if (debug_displaced
)
1338 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1339 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1340 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1343 /* The list of issues to contend with here is taken from
1344 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1345 Yay for Free Software! */
1347 /* Relocate the %rip back to the program's instruction stream,
1350 /* Except in the case of absolute or indirect jump or call
1351 instructions, or a return instruction, the new rip is relative to
1352 the displaced instruction; make it relative to the original insn.
1353 Well, signal handler returns don't need relocation either, but we use the
1354 value of %rip to recognize those; see below. */
1355 if (! amd64_absolute_jmp_p (insn_details
)
1356 && ! amd64_absolute_call_p (insn_details
)
1357 && ! amd64_ret_p (insn_details
))
1362 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1364 /* A signal trampoline system call changes the %rip, resuming
1365 execution of the main program after the signal handler has
1366 returned. That makes them like 'return' instructions; we
1367 shouldn't relocate %rip.
1369 But most system calls don't, and we do need to relocate %rip.
1371 Our heuristic for distinguishing these cases: if stepping
1372 over the system call instruction left control directly after
1373 the instruction, the we relocate --- control almost certainly
1374 doesn't belong in the displaced copy. Otherwise, we assume
1375 the instruction has put control where it belongs, and leave
1376 it unrelocated. Goodness help us if there are PC-relative
1378 if (amd64_syscall_p (insn_details
, &insn_len
)
1379 && orig_rip
!= to
+ insn_len
1380 /* GDB can get control back after the insn after the syscall.
1381 Presumably this is a kernel bug.
1382 Fixup ensures its a nop, we add one to the length for it. */
1383 && orig_rip
!= to
+ insn_len
+ 1)
1385 if (debug_displaced
)
1386 fprintf_unfiltered (gdb_stdlog
,
1387 "displaced: syscall changed %%rip; "
1388 "not relocating\n");
1392 ULONGEST rip
= orig_rip
- insn_offset
;
1394 /* If we just stepped over a breakpoint insn, we don't backup
1395 the pc on purpose; this is to match behaviour without
1398 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1400 if (debug_displaced
)
1401 fprintf_unfiltered (gdb_stdlog
,
1403 "relocated %%rip from %s to %s\n",
1404 paddress (gdbarch
, orig_rip
),
1405 paddress (gdbarch
, rip
));
1409 /* If the instruction was PUSHFL, then the TF bit will be set in the
1410 pushed value, and should be cleared. We'll leave this for later,
1411 since GDB already messes up the TF flag when stepping over a
1414 /* If the instruction was a call, the return address now atop the
1415 stack is the address following the copied instruction. We need
1416 to make it the address following the original instruction. */
1417 if (amd64_call_p (insn_details
))
1421 const ULONGEST retaddr_len
= 8;
1423 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1424 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1425 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
1426 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1428 if (debug_displaced
)
1429 fprintf_unfiltered (gdb_stdlog
,
1430 "displaced: relocated return addr at %s "
1432 paddress (gdbarch
, rsp
),
1433 paddress (gdbarch
, retaddr
));
1437 /* The maximum number of saved registers. This should include %rip. */
1438 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1440 struct amd64_frame_cache
1444 CORE_ADDR sp_offset
;
1447 /* Saved registers. */
1448 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1452 /* Do we have a frame? */
1456 /* Initialize a frame cache. */
1459 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1465 cache
->sp_offset
= -8;
1468 /* Saved registers. We initialize these to -1 since zero is a valid
1469 offset (that's where %rbp is supposed to be stored).
1470 The values start out as being offsets, and are later converted to
1471 addresses (at which point -1 is interpreted as an address, still meaning
1473 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1474 cache
->saved_regs
[i
] = -1;
1475 cache
->saved_sp
= 0;
1476 cache
->saved_sp_reg
= -1;
1478 /* Frameless until proven otherwise. */
1479 cache
->frameless_p
= 1;
1482 /* Allocate and initialize a frame cache. */
1484 static struct amd64_frame_cache
*
1485 amd64_alloc_frame_cache (void)
1487 struct amd64_frame_cache
*cache
;
1489 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1490 amd64_init_frame_cache (cache
);
1494 /* GCC 4.4 and later, can put code in the prologue to realign the
1495 stack pointer. Check whether PC points to such code, and update
1496 CACHE accordingly. Return the first instruction after the code
1497 sequence or CURRENT_PC, whichever is smaller. If we don't
1498 recognize the code, return PC. */
1501 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1502 struct amd64_frame_cache
*cache
)
1504 /* There are 2 code sequences to re-align stack before the frame
1507 1. Use a caller-saved saved register:
1513 2. Use a callee-saved saved register:
1520 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1522 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1523 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1528 int offset
, offset_and
;
1530 if (target_read_memory (pc
, buf
, sizeof buf
))
1533 /* Check caller-saved saved register. The first instruction has
1534 to be "leaq 8(%rsp), %reg". */
1535 if ((buf
[0] & 0xfb) == 0x48
1540 /* MOD must be binary 10 and R/M must be binary 100. */
1541 if ((buf
[2] & 0xc7) != 0x44)
1544 /* REG has register number. */
1545 reg
= (buf
[2] >> 3) & 7;
1547 /* Check the REX.R bit. */
1555 /* Check callee-saved saved register. The first instruction
1556 has to be "pushq %reg". */
1558 if ((buf
[0] & 0xf8) == 0x50)
1560 else if ((buf
[0] & 0xf6) == 0x40
1561 && (buf
[1] & 0xf8) == 0x50)
1563 /* Check the REX.B bit. */
1564 if ((buf
[0] & 1) != 0)
1573 reg
+= buf
[offset
] & 0x7;
1577 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1578 if ((buf
[offset
] & 0xfb) != 0x48
1579 || buf
[offset
+ 1] != 0x8d
1580 || buf
[offset
+ 3] != 0x24
1581 || buf
[offset
+ 4] != 0x10)
1584 /* MOD must be binary 10 and R/M must be binary 100. */
1585 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
1588 /* REG has register number. */
1589 r
= (buf
[offset
+ 2] >> 3) & 7;
1591 /* Check the REX.R bit. */
1592 if (buf
[offset
] == 0x4c)
1595 /* Registers in pushq and leaq have to be the same. */
1602 /* Rigister can't be %rsp nor %rbp. */
1603 if (reg
== 4 || reg
== 5)
1606 /* The next instruction has to be "andq $-XXX, %rsp". */
1607 if (buf
[offset
] != 0x48
1608 || buf
[offset
+ 2] != 0xe4
1609 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
1612 offset_and
= offset
;
1613 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
1615 /* The next instruction has to be "pushq -8(%reg)". */
1617 if (buf
[offset
] == 0xff)
1619 else if ((buf
[offset
] & 0xf6) == 0x40
1620 && buf
[offset
+ 1] == 0xff)
1622 /* Check the REX.B bit. */
1623 if ((buf
[offset
] & 0x1) != 0)
1630 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
1632 if (buf
[offset
+ 1] != 0xf8
1633 || (buf
[offset
] & 0xf8) != 0x70)
1636 /* R/M has register. */
1637 r
+= buf
[offset
] & 7;
1639 /* Registers in leaq and pushq have to be the same. */
1643 if (current_pc
> pc
+ offset_and
)
1644 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
1646 return min (pc
+ offset
+ 2, current_pc
);
1649 /* Do a limited analysis of the prologue at PC and update CACHE
1650 accordingly. Bail out early if CURRENT_PC is reached. Return the
1651 address where the analysis stopped.
1653 We will handle only functions beginning with:
1656 movq %rsp, %rbp 0x48 0x89 0xe5
1658 Any function that doesn't start with this sequence will be assumed
1659 to have no prologue and thus no valid frame pointer in %rbp. */
1662 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
1663 CORE_ADDR pc
, CORE_ADDR current_pc
,
1664 struct amd64_frame_cache
*cache
)
1666 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1667 static gdb_byte proto
[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */
1671 if (current_pc
<= pc
)
1674 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
1676 op
= read_memory_unsigned_integer (pc
, 1, byte_order
);
1678 if (op
== 0x55) /* pushq %rbp */
1680 /* Take into account that we've executed the `pushq %rbp' that
1681 starts this instruction sequence. */
1682 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
1683 cache
->sp_offset
+= 8;
1685 /* If that's all, return now. */
1686 if (current_pc
<= pc
+ 1)
1689 /* Check for `movq %rsp, %rbp'. */
1690 read_memory (pc
+ 1, buf
, 3);
1691 if (memcmp (buf
, proto
, 3) != 0)
1694 /* OK, we actually have a frame. */
1695 cache
->frameless_p
= 0;
1702 /* Return PC of first real instruction. */
1705 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1707 struct amd64_frame_cache cache
;
1710 amd64_init_frame_cache (&cache
);
1711 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
1713 if (cache
.frameless_p
)
1720 /* Normal frames. */
1722 static struct amd64_frame_cache
*
1723 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1725 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1726 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1727 struct amd64_frame_cache
*cache
;
1734 cache
= amd64_alloc_frame_cache ();
1735 *this_cache
= cache
;
1737 cache
->pc
= get_frame_func (this_frame
);
1739 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1742 if (cache
->saved_sp_reg
!= -1)
1744 /* Stack pointer has been saved. */
1745 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1746 cache
->saved_sp
= extract_unsigned_integer(buf
, 8, byte_order
);
1749 if (cache
->frameless_p
)
1751 /* We didn't find a valid frame. If we're at the start of a
1752 function, or somewhere half-way its prologue, the function's
1753 frame probably hasn't been fully setup yet. Try to
1754 reconstruct the base address for the stack frame by looking
1755 at the stack pointer. For truly "frameless" functions this
1758 if (cache
->saved_sp_reg
!= -1)
1760 /* We're halfway aligning the stack. */
1761 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
1762 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
1764 /* This will be added back below. */
1765 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
1769 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
1770 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
1776 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
1777 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
1780 /* Now that we have the base address for the stack frame we can
1781 calculate the value of %rsp in the calling frame. */
1782 cache
->saved_sp
= cache
->base
+ 16;
1784 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
1785 frame we find it at the same offset from the reconstructed base
1786 address. If we're halfway aligning the stack, %rip is handled
1787 differently (see above). */
1788 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
1789 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
1791 /* Adjust all the saved registers such that they contain addresses
1792 instead of offsets. */
1793 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1794 if (cache
->saved_regs
[i
] != -1)
1795 cache
->saved_regs
[i
] += cache
->base
;
1801 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1802 struct frame_id
*this_id
)
1804 struct amd64_frame_cache
*cache
=
1805 amd64_frame_cache (this_frame
, this_cache
);
1807 /* This marks the outermost frame. */
1808 if (cache
->base
== 0)
1811 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
1814 static struct value
*
1815 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1818 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1819 struct amd64_frame_cache
*cache
=
1820 amd64_frame_cache (this_frame
, this_cache
);
1822 gdb_assert (regnum
>= 0);
1824 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
1825 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1827 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1828 return frame_unwind_got_memory (this_frame
, regnum
,
1829 cache
->saved_regs
[regnum
]);
1831 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1834 static const struct frame_unwind amd64_frame_unwind
=
1837 amd64_frame_this_id
,
1838 amd64_frame_prev_register
,
1840 default_frame_sniffer
1844 /* Signal trampolines. */
1846 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
1847 64-bit variants. This would require using identical frame caches
1848 on both platforms. */
1850 static struct amd64_frame_cache
*
1851 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1853 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1854 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1855 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1856 struct amd64_frame_cache
*cache
;
1864 cache
= amd64_alloc_frame_cache ();
1866 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
1867 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
1869 addr
= tdep
->sigcontext_addr (this_frame
);
1870 gdb_assert (tdep
->sc_reg_offset
);
1871 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
1872 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1873 if (tdep
->sc_reg_offset
[i
] != -1)
1874 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1876 *this_cache
= cache
;
1881 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
1882 void **this_cache
, struct frame_id
*this_id
)
1884 struct amd64_frame_cache
*cache
=
1885 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
1887 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
1890 static struct value
*
1891 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
1892 void **this_cache
, int regnum
)
1894 /* Make sure we've initialized the cache. */
1895 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
1897 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
1901 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
1902 struct frame_info
*this_frame
,
1905 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1907 /* We shouldn't even bother if we don't have a sigcontext_addr
1909 if (tdep
->sigcontext_addr
== NULL
)
1912 if (tdep
->sigtramp_p
!= NULL
)
1914 if (tdep
->sigtramp_p (this_frame
))
1918 if (tdep
->sigtramp_start
!= 0)
1920 CORE_ADDR pc
= get_frame_pc (this_frame
);
1922 gdb_assert (tdep
->sigtramp_end
!= 0);
1923 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
1930 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
1933 amd64_sigtramp_frame_this_id
,
1934 amd64_sigtramp_frame_prev_register
,
1936 amd64_sigtramp_frame_sniffer
1941 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1943 struct amd64_frame_cache
*cache
=
1944 amd64_frame_cache (this_frame
, this_cache
);
1949 static const struct frame_base amd64_frame_base
=
1951 &amd64_frame_unwind
,
1952 amd64_frame_base_address
,
1953 amd64_frame_base_address
,
1954 amd64_frame_base_address
1957 /* Normal frames, but in a function epilogue. */
1959 /* The epilogue is defined here as the 'ret' instruction, which will
1960 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1961 the function's stack frame. */
1964 amd64_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1968 if (target_read_memory (pc
, &insn
, 1))
1969 return 0; /* Can't read memory at pc. */
1971 if (insn
!= 0xc3) /* 'ret' instruction. */
1978 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1979 struct frame_info
*this_frame
,
1980 void **this_prologue_cache
)
1982 if (frame_relative_level (this_frame
) == 0)
1983 return amd64_in_function_epilogue_p (get_frame_arch (this_frame
),
1984 get_frame_pc (this_frame
));
1989 static struct amd64_frame_cache
*
1990 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1992 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1993 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1994 struct amd64_frame_cache
*cache
;
2000 cache
= amd64_alloc_frame_cache ();
2001 *this_cache
= cache
;
2003 /* Cache base will be %esp plus cache->sp_offset (-8). */
2004 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2005 cache
->base
= extract_unsigned_integer (buf
, 8,
2006 byte_order
) + cache
->sp_offset
;
2008 /* Cache pc will be the frame func. */
2009 cache
->pc
= get_frame_pc (this_frame
);
2011 /* The saved %esp will be at cache->base plus 16. */
2012 cache
->saved_sp
= cache
->base
+ 16;
2014 /* The saved %eip will be at cache->base plus 8. */
2015 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2021 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2023 struct frame_id
*this_id
)
2025 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2028 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2031 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2034 amd64_epilogue_frame_this_id
,
2035 amd64_frame_prev_register
,
2037 amd64_epilogue_frame_sniffer
2040 static struct frame_id
2041 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2045 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2047 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2050 /* 16 byte align the SP per frame requirements. */
2053 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2055 return sp
& -(CORE_ADDR
)16;
2059 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2060 in the floating-point register set REGSET to register cache
2061 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2064 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2065 int regnum
, const void *fpregs
, size_t len
)
2067 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2069 gdb_assert (len
== tdep
->sizeof_fpregset
);
2070 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
2073 /* Collect register REGNUM from the register cache REGCACHE and store
2074 it in the buffer specified by FPREGS and LEN as described by the
2075 floating-point register set REGSET. If REGNUM is -1, do this for
2076 all registers in REGSET. */
2079 amd64_collect_fpregset (const struct regset
*regset
,
2080 const struct regcache
*regcache
,
2081 int regnum
, void *fpregs
, size_t len
)
2083 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2085 gdb_assert (len
== tdep
->sizeof_fpregset
);
2086 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
2089 /* Return the appropriate register set for the core section identified
2090 by SECT_NAME and SECT_SIZE. */
2092 static const struct regset
*
2093 amd64_regset_from_core_section (struct gdbarch
*gdbarch
,
2094 const char *sect_name
, size_t sect_size
)
2096 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2098 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2100 if (tdep
->fpregset
== NULL
)
2101 tdep
->fpregset
= regset_alloc (gdbarch
, amd64_supply_fpregset
,
2102 amd64_collect_fpregset
);
2104 return tdep
->fpregset
;
2107 return i386_regset_from_core_section (gdbarch
, sect_name
, sect_size
);
2111 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2112 %rdi. We expect its value to be a pointer to the jmp_buf structure
2113 from which we extract the address that we will land at. This
2114 address is copied into PC. This routine returns non-zero on
2118 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2122 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2123 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2124 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
2126 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2127 longjmp will land. */
2128 if (jb_pc_offset
== -1)
2131 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
2132 jb_addr
= extract_typed_address
2133 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
2134 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
2137 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
2142 static const int amd64_record_regmap
[] =
2144 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
2145 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
2146 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
2147 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
2148 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
2149 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
2153 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2155 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2157 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2158 floating-point registers. */
2159 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
2161 /* AMD64 has an FPU and 16 SSE registers. */
2162 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
2163 tdep
->num_xmm_regs
= 16;
2165 /* This is what all the fuss is about. */
2166 set_gdbarch_long_bit (gdbarch
, 64);
2167 set_gdbarch_long_long_bit (gdbarch
, 64);
2168 set_gdbarch_ptr_bit (gdbarch
, 64);
2170 /* In contrast to the i386, on AMD64 a `long double' actually takes
2171 up 128 bits, even though it's still based on the i387 extended
2172 floating-point format which has only 80 significant bits. */
2173 set_gdbarch_long_double_bit (gdbarch
, 128);
2175 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
2176 set_gdbarch_register_name (gdbarch
, amd64_register_name
);
2177 set_gdbarch_register_type (gdbarch
, amd64_register_type
);
2179 /* Register numbers of various important registers. */
2180 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
2181 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
2182 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
2183 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
2185 /* The "default" register numbering scheme for AMD64 is referred to
2186 as the "DWARF Register Number Mapping" in the System V psABI.
2187 The preferred debugging format for all known AMD64 targets is
2188 actually DWARF2, and GCC doesn't seem to support DWARF (that is
2189 DWARF-1), but we provide the same mapping just in case. This
2190 mapping is also used for stabs, which GCC does support. */
2191 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
2192 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
2194 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
2195 be in use on any of the supported AMD64 targets. */
2197 /* Call dummy code. */
2198 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
2199 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
2200 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
2201 tdep
->call_dummy_num_integer_regs
=
2202 ARRAY_SIZE (amd64_dummy_call_integer_regs
);
2203 tdep
->call_dummy_integer_regs
= amd64_dummy_call_integer_regs
;
2204 tdep
->classify
= amd64_classify
;
2206 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
2207 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
2208 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
2210 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
2212 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
2214 /* Avoid wiring in the MMX registers for now. */
2215 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2216 tdep
->mm0_regnum
= -1;
2218 tdep
->record_regmap
= amd64_record_regmap
;
2220 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
2222 /* Hook the function epilogue frame unwinder. This unwinder is
2223 appended to the list first, so that it supercedes the other
2224 unwinders in function epilogues. */
2225 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
2227 /* Hook the prologue-based frame unwinders. */
2228 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
2229 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
2230 frame_base_set_default (gdbarch
, &amd64_frame_base
);
2232 /* If we have a register mapping, enable the generic core file support. */
2233 if (tdep
->gregset_reg_offset
)
2234 set_gdbarch_regset_from_core_section (gdbarch
,
2235 amd64_regset_from_core_section
);
2237 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
2241 /* The 64-bit FXSAVE format differs from the 32-bit format in the
2242 sense that the instruction pointer and data pointer are simply
2243 64-bit offsets into the code segment and the data segment instead
2244 of a selector offset pair. The functions below store the upper 32
2245 bits of these pointers (instead of just the 16-bits of the segment
2248 /* Fill register REGNUM in REGCACHE with the appropriate
2249 floating-point or SSE register value from *FXSAVE. If REGNUM is
2250 -1, do this for all registers. This function masks off any of the
2251 reserved bits in *FXSAVE. */
2254 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
2257 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2258 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2260 i387_supply_fxsave (regcache
, regnum
, fxsave
);
2262 if (fxsave
&& gdbarch_ptr_bit (gdbarch
) == 64)
2264 const gdb_byte
*regs
= fxsave
;
2266 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
2267 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
2268 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
2269 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
2273 /* Fill register REGNUM (if it is a floating-point or SSE register) in
2274 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
2275 all registers. This function doesn't touch any of the reserved
2279 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
2282 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2283 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2284 gdb_byte
*regs
= fxsave
;
2286 i387_collect_fxsave (regcache
, regnum
, fxsave
);
2288 if (gdbarch_ptr_bit (gdbarch
) == 64)
2290 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
2291 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
2292 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
2293 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);