1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 Contributed by Jiri Smid, SuSE Labs.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
26 #include "arch-utils.h"
28 #include "dummy-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
40 #include "gdb_assert.h"
42 #include "amd64-tdep.h"
43 #include "i387-tdep.h"
45 /* Note that the AMD64 architecture was previously known as x86-64.
46 The latter is (forever) engraved into the canonical system name as
47 returned by config.guess, and used as the name for the AMD64 port
48 of GNU/Linux. The BSD's have renamed their ports to amd64; they
49 don't like to shout. For GDB we prefer the amd64_-prefix over the
50 x86_64_-prefix since it's so much easier to type. */
52 /* Register information. */
54 static const char *amd64_register_names
[] =
56 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
58 /* %r8 is indeed register number 8. */
59 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
60 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
62 /* %st0 is register number 24. */
63 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
64 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
66 /* %xmm0 is register number 40. */
67 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
68 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
72 /* Total number of registers. */
73 #define AMD64_NUM_REGS ARRAY_SIZE (amd64_register_names)
75 /* Return the name of register REGNUM. */
78 amd64_register_name (int regnum
)
80 if (regnum
>= 0 && regnum
< AMD64_NUM_REGS
)
81 return amd64_register_names
[regnum
];
86 /* Return the GDB type object for the "standard" data type of data in
90 amd64_register_type (struct gdbarch
*gdbarch
, int regnum
)
92 if (regnum
>= AMD64_RAX_REGNUM
&& regnum
<= AMD64_RDI_REGNUM
)
93 return builtin_type_int64
;
94 if (regnum
== AMD64_RBP_REGNUM
|| regnum
== AMD64_RSP_REGNUM
)
95 return builtin_type_void_data_ptr
;
96 if (regnum
>= AMD64_R8_REGNUM
&& regnum
<= AMD64_R15_REGNUM
)
97 return builtin_type_int64
;
98 if (regnum
== AMD64_RIP_REGNUM
)
99 return builtin_type_void_func_ptr
;
100 if (regnum
== AMD64_EFLAGS_REGNUM
)
101 return i386_eflags_type
;
102 if (regnum
>= AMD64_CS_REGNUM
&& regnum
<= AMD64_GS_REGNUM
)
103 return builtin_type_int32
;
104 if (regnum
>= AMD64_ST0_REGNUM
&& regnum
<= AMD64_ST0_REGNUM
+ 7)
105 return builtin_type_i387_ext
;
106 if (regnum
>= AMD64_FCTRL_REGNUM
&& regnum
<= AMD64_FCTRL_REGNUM
+ 7)
107 return builtin_type_int32
;
108 if (regnum
>= AMD64_XMM0_REGNUM
&& regnum
<= AMD64_XMM0_REGNUM
+ 15)
109 return i386_sse_type (gdbarch
);
110 if (regnum
== AMD64_MXCSR_REGNUM
)
111 return i386_mxcsr_type
;
113 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
116 /* DWARF Register Number Mapping as defined in the System V psABI,
119 static int amd64_dwarf_regmap
[] =
121 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
122 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
123 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
124 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
126 /* Frame Pointer Register RBP. */
129 /* Stack Pointer Register RSP. */
132 /* Extended Integer Registers 8 - 15. */
133 8, 9, 10, 11, 12, 13, 14, 15,
135 /* Return Address RA. Mapped to RIP. */
138 /* SSE Registers 0 - 7. */
139 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
140 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
141 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
142 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
144 /* Extended SSE Registers 8 - 15. */
145 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
146 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
147 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
148 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
150 /* Floating Point Registers 0-7. */
151 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
152 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
153 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
154 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
156 /* Control and Status Flags Register. */
159 /* Selector Registers. */
169 /* Segment Base Address Registers. */
175 /* Special Selector Registers. */
179 /* Floating Point Control Registers. */
185 static const int amd64_dwarf_regmap_len
=
186 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
188 /* Convert DWARF register number REG to the appropriate register
189 number used by GDB. */
192 amd64_dwarf_reg_to_regnum (int reg
)
196 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
197 regnum
= amd64_dwarf_regmap
[reg
];
200 warning (_("Unmapped DWARF Register #%d encountered."), reg
);
205 /* Return nonzero if a value of type TYPE stored in register REGNUM
206 needs any special handling. */
209 amd64_convert_register_p (int regnum
, struct type
*type
)
211 return i386_fp_regnum_p (regnum
);
215 /* Register classes as defined in the psABI. */
229 /* Return the union class of CLASS1 and CLASS2. See the psABI for
232 static enum amd64_reg_class
233 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
235 /* Rule (a): If both classes are equal, this is the resulting class. */
236 if (class1
== class2
)
239 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
240 is the other class. */
241 if (class1
== AMD64_NO_CLASS
)
243 if (class2
== AMD64_NO_CLASS
)
246 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
247 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
250 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
251 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
252 return AMD64_INTEGER
;
254 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
255 MEMORY is used as class. */
256 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
257 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
258 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
261 /* Rule (f): Otherwise class SSE is used. */
265 static void amd64_classify (struct type
*type
, enum amd64_reg_class
class[2]);
267 /* Return non-zero if TYPE is a non-POD structure or union type. */
270 amd64_non_pod_p (struct type
*type
)
272 /* ??? A class with a base class certainly isn't POD, but does this
273 catch all non-POD structure types? */
274 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
280 /* Classify TYPE according to the rules for aggregate (structures and
281 arrays) and union types, and store the result in CLASS. */
284 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class
class[2])
286 int len
= TYPE_LENGTH (type
);
288 /* 1. If the size of an object is larger than two eightbytes, or in
289 C++, is a non-POD structure or union type, or contains
290 unaligned fields, it has class memory. */
291 if (len
> 16 || amd64_non_pod_p (type
))
293 class[0] = class[1] = AMD64_MEMORY
;
297 /* 2. Both eightbytes get initialized to class NO_CLASS. */
298 class[0] = class[1] = AMD64_NO_CLASS
;
300 /* 3. Each field of an object is classified recursively so that
301 always two fields are considered. The resulting class is
302 calculated according to the classes of the fields in the
305 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
307 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
309 /* All fields in an array have the same type. */
310 amd64_classify (subtype
, class);
311 if (len
> 8 && class[1] == AMD64_NO_CLASS
)
318 /* Structure or union. */
319 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
320 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
322 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
324 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
325 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
326 enum amd64_reg_class subclass
[2];
328 /* Ignore static fields. */
329 if (TYPE_FIELD_STATIC (type
, i
))
332 gdb_assert (pos
== 0 || pos
== 1);
334 amd64_classify (subtype
, subclass
);
335 class[pos
] = amd64_merge_classes (class[pos
], subclass
[0]);
337 class[1] = amd64_merge_classes (class[1], subclass
[1]);
341 /* 4. Then a post merger cleanup is done: */
343 /* Rule (a): If one of the classes is MEMORY, the whole argument is
345 if (class[0] == AMD64_MEMORY
|| class[1] == AMD64_MEMORY
)
346 class[0] = class[1] = AMD64_MEMORY
;
348 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
350 if (class[0] == AMD64_SSEUP
)
351 class[0] = AMD64_SSE
;
352 if (class[1] == AMD64_SSEUP
&& class[0] != AMD64_SSE
)
353 class[1] = AMD64_SSE
;
356 /* Classify TYPE, and store the result in CLASS. */
359 amd64_classify (struct type
*type
, enum amd64_reg_class
class[2])
361 enum type_code code
= TYPE_CODE (type
);
362 int len
= TYPE_LENGTH (type
);
364 class[0] = class[1] = AMD64_NO_CLASS
;
366 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
367 long, long long, and pointers are in the INTEGER class. Similarly,
368 range types, used by languages such as Ada, are also in the INTEGER
370 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
371 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
372 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
373 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
374 class[0] = AMD64_INTEGER
;
376 /* Arguments of types float, double and __m64 are in class SSE. */
377 else if (code
== TYPE_CODE_FLT
&& (len
== 4 || len
== 8))
379 class[0] = AMD64_SSE
;
381 /* Arguments of types __float128 and __m128 are split into two
382 halves. The least significant ones belong to class SSE, the most
383 significant one to class SSEUP. */
384 /* FIXME: __float128, __m128. */
386 /* The 64-bit mantissa of arguments of type long double belongs to
387 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
389 else if (code
== TYPE_CODE_FLT
&& len
== 16)
390 /* Class X87 and X87UP. */
391 class[0] = AMD64_X87
, class[1] = AMD64_X87UP
;
394 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
395 || code
== TYPE_CODE_UNION
)
396 amd64_classify_aggregate (type
, class);
399 static enum return_value_convention
400 amd64_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
401 struct regcache
*regcache
,
402 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
404 enum amd64_reg_class
class[2];
405 int len
= TYPE_LENGTH (type
);
406 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
407 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
412 gdb_assert (!(readbuf
&& writebuf
));
414 /* 1. Classify the return type with the classification algorithm. */
415 amd64_classify (type
, class);
417 /* 2. If the type has class MEMORY, then the caller provides space
418 for the return value and passes the address of this storage in
419 %rdi as if it were the first argument to the function. In effect,
420 this address becomes a hidden first argument.
422 On return %rax will contain the address that has been passed in
423 by the caller in %rdi. */
424 if (class[0] == AMD64_MEMORY
)
426 /* As indicated by the comment above, the ABI guarantees that we
427 can always find the return value just after the function has
434 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
435 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
438 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
441 gdb_assert (class[1] != AMD64_MEMORY
);
442 gdb_assert (len
<= 16);
444 for (i
= 0; len
> 0; i
++, len
-= 8)
452 /* 3. If the class is INTEGER, the next available register
453 of the sequence %rax, %rdx is used. */
454 regnum
= integer_regnum
[integer_reg
++];
458 /* 4. If the class is SSE, the next available SSE register
459 of the sequence %xmm0, %xmm1 is used. */
460 regnum
= sse_regnum
[sse_reg
++];
464 /* 5. If the class is SSEUP, the eightbyte is passed in the
465 upper half of the last used SSE register. */
466 gdb_assert (sse_reg
> 0);
467 regnum
= sse_regnum
[sse_reg
- 1];
472 /* 6. If the class is X87, the value is returned on the X87
473 stack in %st0 as 80-bit x87 number. */
474 regnum
= AMD64_ST0_REGNUM
;
476 i387_return_value (gdbarch
, regcache
);
480 /* 7. If the class is X87UP, the value is returned together
481 with the previous X87 value in %st0. */
482 gdb_assert (i
> 0 && class[0] == AMD64_X87
);
483 regnum
= AMD64_ST0_REGNUM
;
492 gdb_assert (!"Unexpected register class.");
495 gdb_assert (regnum
!= -1);
498 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
501 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
505 return RETURN_VALUE_REGISTER_CONVENTION
;
510 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
511 struct value
**args
, CORE_ADDR sp
, int struct_return
)
513 static int integer_regnum
[] =
515 AMD64_RDI_REGNUM
, /* %rdi */
516 AMD64_RSI_REGNUM
, /* %rsi */
517 AMD64_RDX_REGNUM
, /* %rdx */
518 AMD64_RCX_REGNUM
, /* %rcx */
522 static int sse_regnum
[] =
524 /* %xmm0 ... %xmm7 */
525 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
526 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
527 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
528 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
530 struct value
**stack_args
= alloca (nargs
* sizeof (struct value
*));
531 int num_stack_args
= 0;
532 int num_elements
= 0;
538 /* Reserve a register for the "hidden" argument. */
542 for (i
= 0; i
< nargs
; i
++)
544 struct type
*type
= value_type (args
[i
]);
545 int len
= TYPE_LENGTH (type
);
546 enum amd64_reg_class
class[2];
547 int needed_integer_regs
= 0;
548 int needed_sse_regs
= 0;
551 /* Classify argument. */
552 amd64_classify (type
, class);
554 /* Calculate the number of integer and SSE registers needed for
556 for (j
= 0; j
< 2; j
++)
558 if (class[j
] == AMD64_INTEGER
)
559 needed_integer_regs
++;
560 else if (class[j
] == AMD64_SSE
)
564 /* Check whether enough registers are available, and if the
565 argument should be passed in registers at all. */
566 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
567 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
568 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
570 /* The argument will be passed on the stack. */
571 num_elements
+= ((len
+ 7) / 8);
572 stack_args
[num_stack_args
++] = args
[i
];
576 /* The argument will be passed in registers. */
577 const gdb_byte
*valbuf
= value_contents (args
[i
]);
580 gdb_assert (len
<= 16);
582 for (j
= 0; len
> 0; j
++, len
-= 8)
590 regnum
= integer_regnum
[integer_reg
++];
594 regnum
= sse_regnum
[sse_reg
++];
598 gdb_assert (sse_reg
> 0);
599 regnum
= sse_regnum
[sse_reg
- 1];
604 gdb_assert (!"Unexpected register class.");
607 gdb_assert (regnum
!= -1);
608 memset (buf
, 0, sizeof buf
);
609 memcpy (buf
, valbuf
+ j
* 8, min (len
, 8));
610 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
615 /* Allocate space for the arguments on the stack. */
616 sp
-= num_elements
* 8;
618 /* The psABI says that "The end of the input argument area shall be
619 aligned on a 16 byte boundary." */
622 /* Write out the arguments to the stack. */
623 for (i
= 0; i
< num_stack_args
; i
++)
625 struct type
*type
= value_type (stack_args
[i
]);
626 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
627 int len
= TYPE_LENGTH (type
);
629 write_memory (sp
+ element
* 8, valbuf
, len
);
630 element
+= ((len
+ 7) / 8);
633 /* The psABI says that "For calls that may call functions that use
634 varargs or stdargs (prototype-less calls or calls to functions
635 containing ellipsis (...) in the declaration) %al is used as
636 hidden argument to specify the number of SSE registers used. */
637 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
642 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
643 struct regcache
*regcache
, CORE_ADDR bp_addr
,
644 int nargs
, struct value
**args
, CORE_ADDR sp
,
645 int struct_return
, CORE_ADDR struct_addr
)
649 /* Pass arguments. */
650 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, struct_return
);
652 /* Pass "hidden" argument". */
655 store_unsigned_integer (buf
, 8, struct_addr
);
656 regcache_cooked_write (regcache
, AMD64_RDI_REGNUM
, buf
);
659 /* Store return address. */
661 store_unsigned_integer (buf
, 8, bp_addr
);
662 write_memory (sp
, buf
, 8);
664 /* Finally, update the stack pointer... */
665 store_unsigned_integer (buf
, 8, sp
);
666 regcache_cooked_write (regcache
, AMD64_RSP_REGNUM
, buf
);
668 /* ...and fake a frame pointer. */
669 regcache_cooked_write (regcache
, AMD64_RBP_REGNUM
, buf
);
675 /* The maximum number of saved registers. This should include %rip. */
676 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
678 struct amd64_frame_cache
685 /* Saved registers. */
686 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
689 /* Do we have a frame? */
693 /* Initialize a frame cache. */
696 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
702 cache
->sp_offset
= -8;
705 /* Saved registers. We initialize these to -1 since zero is a valid
706 offset (that's where %rbp is supposed to be stored). */
707 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
708 cache
->saved_regs
[i
] = -1;
711 /* Frameless until proven otherwise. */
712 cache
->frameless_p
= 1;
715 /* Allocate and initialize a frame cache. */
717 static struct amd64_frame_cache
*
718 amd64_alloc_frame_cache (void)
720 struct amd64_frame_cache
*cache
;
722 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
723 amd64_init_frame_cache (cache
);
727 /* Do a limited analysis of the prologue at PC and update CACHE
728 accordingly. Bail out early if CURRENT_PC is reached. Return the
729 address where the analysis stopped.
731 We will handle only functions beginning with:
734 movq %rsp, %rbp 0x48 0x89 0xe5
736 Any function that doesn't start with this sequence will be assumed
737 to have no prologue and thus no valid frame pointer in %rbp. */
740 amd64_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
741 struct amd64_frame_cache
*cache
)
743 static gdb_byte proto
[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */
747 if (current_pc
<= pc
)
750 op
= read_memory_unsigned_integer (pc
, 1);
752 if (op
== 0x55) /* pushq %rbp */
754 /* Take into account that we've executed the `pushq %rbp' that
755 starts this instruction sequence. */
756 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
757 cache
->sp_offset
+= 8;
759 /* If that's all, return now. */
760 if (current_pc
<= pc
+ 1)
763 /* Check for `movq %rsp, %rbp'. */
764 read_memory (pc
+ 1, buf
, 3);
765 if (memcmp (buf
, proto
, 3) != 0)
768 /* OK, we actually have a frame. */
769 cache
->frameless_p
= 0;
776 /* Return PC of first real instruction. */
779 amd64_skip_prologue (CORE_ADDR start_pc
)
781 struct amd64_frame_cache cache
;
784 amd64_init_frame_cache (&cache
);
785 pc
= amd64_analyze_prologue (start_pc
, 0xffffffffffffffffLL
, &cache
);
786 if (cache
.frameless_p
)
795 static struct amd64_frame_cache
*
796 amd64_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
798 struct amd64_frame_cache
*cache
;
805 cache
= amd64_alloc_frame_cache ();
808 cache
->pc
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
810 amd64_analyze_prologue (cache
->pc
, frame_pc_unwind (next_frame
), cache
);
812 if (cache
->frameless_p
)
814 /* We didn't find a valid frame. If we're at the start of a
815 function, or somewhere half-way its prologue, the function's
816 frame probably hasn't been fully setup yet. Try to
817 reconstruct the base address for the stack frame by looking
818 at the stack pointer. For truly "frameless" functions this
821 frame_unwind_register (next_frame
, AMD64_RSP_REGNUM
, buf
);
822 cache
->base
= extract_unsigned_integer (buf
, 8) + cache
->sp_offset
;
826 frame_unwind_register (next_frame
, AMD64_RBP_REGNUM
, buf
);
827 cache
->base
= extract_unsigned_integer (buf
, 8);
830 /* Now that we have the base address for the stack frame we can
831 calculate the value of %rsp in the calling frame. */
832 cache
->saved_sp
= cache
->base
+ 16;
834 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
835 frame we find it at the same offset from the reconstructed base
837 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
839 /* Adjust all the saved registers such that they contain addresses
840 instead of offsets. */
841 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
842 if (cache
->saved_regs
[i
] != -1)
843 cache
->saved_regs
[i
] += cache
->base
;
849 amd64_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
850 struct frame_id
*this_id
)
852 struct amd64_frame_cache
*cache
=
853 amd64_frame_cache (next_frame
, this_cache
);
855 /* This marks the outermost frame. */
856 if (cache
->base
== 0)
859 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
863 amd64_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
864 int regnum
, int *optimizedp
,
865 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
866 int *realnump
, gdb_byte
*valuep
)
868 struct amd64_frame_cache
*cache
=
869 amd64_frame_cache (next_frame
, this_cache
);
871 gdb_assert (regnum
>= 0);
873 if (regnum
== gdbarch_sp_regnum (current_gdbarch
) && cache
->saved_sp
)
881 /* Store the value. */
882 store_unsigned_integer (valuep
, 8, cache
->saved_sp
);
887 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
890 *lvalp
= lval_memory
;
891 *addrp
= cache
->saved_regs
[regnum
];
895 /* Read the value in from memory. */
896 read_memory (*addrp
, valuep
,
897 register_size (current_gdbarch
, regnum
));
903 *lvalp
= lval_register
;
907 frame_unwind_register (next_frame
, (*realnump
), valuep
);
910 static const struct frame_unwind amd64_frame_unwind
=
914 amd64_frame_prev_register
917 static const struct frame_unwind
*
918 amd64_frame_sniffer (struct frame_info
*next_frame
)
920 return &amd64_frame_unwind
;
924 /* Signal trampolines. */
926 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
927 64-bit variants. This would require using identical frame caches
928 on both platforms. */
930 static struct amd64_frame_cache
*
931 amd64_sigtramp_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
933 struct amd64_frame_cache
*cache
;
934 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
942 cache
= amd64_alloc_frame_cache ();
944 frame_unwind_register (next_frame
, AMD64_RSP_REGNUM
, buf
);
945 cache
->base
= extract_unsigned_integer (buf
, 8) - 8;
947 addr
= tdep
->sigcontext_addr (next_frame
);
948 gdb_assert (tdep
->sc_reg_offset
);
949 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
950 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
951 if (tdep
->sc_reg_offset
[i
] != -1)
952 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
959 amd64_sigtramp_frame_this_id (struct frame_info
*next_frame
,
960 void **this_cache
, struct frame_id
*this_id
)
962 struct amd64_frame_cache
*cache
=
963 amd64_sigtramp_frame_cache (next_frame
, this_cache
);
965 (*this_id
) = frame_id_build (cache
->base
+ 16, frame_pc_unwind (next_frame
));
969 amd64_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
971 int regnum
, int *optimizedp
,
972 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
973 int *realnump
, gdb_byte
*valuep
)
975 /* Make sure we've initialized the cache. */
976 amd64_sigtramp_frame_cache (next_frame
, this_cache
);
978 amd64_frame_prev_register (next_frame
, this_cache
, regnum
,
979 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
982 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
985 amd64_sigtramp_frame_this_id
,
986 amd64_sigtramp_frame_prev_register
989 static const struct frame_unwind
*
990 amd64_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
992 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (next_frame
));
994 /* We shouldn't even bother if we don't have a sigcontext_addr
996 if (tdep
->sigcontext_addr
== NULL
)
999 if (tdep
->sigtramp_p
!= NULL
)
1001 if (tdep
->sigtramp_p (next_frame
))
1002 return &amd64_sigtramp_frame_unwind
;
1005 if (tdep
->sigtramp_start
!= 0)
1007 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1009 gdb_assert (tdep
->sigtramp_end
!= 0);
1010 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
1011 return &amd64_sigtramp_frame_unwind
;
1019 amd64_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1021 struct amd64_frame_cache
*cache
=
1022 amd64_frame_cache (next_frame
, this_cache
);
1027 static const struct frame_base amd64_frame_base
=
1029 &amd64_frame_unwind
,
1030 amd64_frame_base_address
,
1031 amd64_frame_base_address
,
1032 amd64_frame_base_address
1035 static struct frame_id
1036 amd64_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1041 frame_unwind_register (next_frame
, AMD64_RBP_REGNUM
, buf
);
1042 fp
= extract_unsigned_integer (buf
, 8);
1044 return frame_id_build (fp
+ 16, frame_pc_unwind (next_frame
));
1047 /* 16 byte align the SP per frame requirements. */
1050 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1052 return sp
& -(CORE_ADDR
)16;
1056 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
1057 in the floating-point register set REGSET to register cache
1058 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
1061 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
1062 int regnum
, const void *fpregs
, size_t len
)
1064 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
1066 gdb_assert (len
== tdep
->sizeof_fpregset
);
1067 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
1070 /* Collect register REGNUM from the register cache REGCACHE and store
1071 it in the buffer specified by FPREGS and LEN as described by the
1072 floating-point register set REGSET. If REGNUM is -1, do this for
1073 all registers in REGSET. */
1076 amd64_collect_fpregset (const struct regset
*regset
,
1077 const struct regcache
*regcache
,
1078 int regnum
, void *fpregs
, size_t len
)
1080 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
1082 gdb_assert (len
== tdep
->sizeof_fpregset
);
1083 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
1086 /* Return the appropriate register set for the core section identified
1087 by SECT_NAME and SECT_SIZE. */
1089 static const struct regset
*
1090 amd64_regset_from_core_section (struct gdbarch
*gdbarch
,
1091 const char *sect_name
, size_t sect_size
)
1093 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1095 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
1097 if (tdep
->fpregset
== NULL
)
1098 tdep
->fpregset
= regset_alloc (gdbarch
, amd64_supply_fpregset
,
1099 amd64_collect_fpregset
);
1101 return tdep
->fpregset
;
1104 return i386_regset_from_core_section (gdbarch
, sect_name
, sect_size
);
1109 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
1111 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1113 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
1114 floating-point registers. */
1115 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
1117 /* AMD64 has an FPU and 16 SSE registers. */
1118 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
1119 tdep
->num_xmm_regs
= 16;
1121 /* This is what all the fuss is about. */
1122 set_gdbarch_long_bit (gdbarch
, 64);
1123 set_gdbarch_long_long_bit (gdbarch
, 64);
1124 set_gdbarch_ptr_bit (gdbarch
, 64);
1126 /* In contrast to the i386, on AMD64 a `long double' actually takes
1127 up 128 bits, even though it's still based on the i387 extended
1128 floating-point format which has only 80 significant bits. */
1129 set_gdbarch_long_double_bit (gdbarch
, 128);
1131 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
1132 set_gdbarch_register_name (gdbarch
, amd64_register_name
);
1133 set_gdbarch_register_type (gdbarch
, amd64_register_type
);
1135 /* Register numbers of various important registers. */
1136 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
1137 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
1138 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
1139 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
1141 /* The "default" register numbering scheme for AMD64 is referred to
1142 as the "DWARF Register Number Mapping" in the System V psABI.
1143 The preferred debugging format for all known AMD64 targets is
1144 actually DWARF2, and GCC doesn't seem to support DWARF (that is
1145 DWARF-1), but we provide the same mapping just in case. This
1146 mapping is also used for stabs, which GCC does support. */
1147 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
1148 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
1149 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
1151 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1152 be in use on any of the supported AMD64 targets. */
1154 /* Call dummy code. */
1155 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
1156 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
1157 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
1159 set_gdbarch_convert_register_p (gdbarch
, amd64_convert_register_p
);
1160 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
1161 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
1163 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
1165 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
1167 /* Avoid wiring in the MMX registers for now. */
1168 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
1169 tdep
->mm0_regnum
= -1;
1171 set_gdbarch_unwind_dummy_id (gdbarch
, amd64_unwind_dummy_id
);
1173 frame_unwind_append_sniffer (gdbarch
, amd64_sigtramp_frame_sniffer
);
1174 frame_unwind_append_sniffer (gdbarch
, amd64_frame_sniffer
);
1175 frame_base_set_default (gdbarch
, &amd64_frame_base
);
1177 /* If we have a register mapping, enable the generic core file support. */
1178 if (tdep
->gregset_reg_offset
)
1179 set_gdbarch_regset_from_core_section (gdbarch
,
1180 amd64_regset_from_core_section
);
1184 #define I387_ST0_REGNUM AMD64_ST0_REGNUM
1186 /* The 64-bit FXSAVE format differs from the 32-bit format in the
1187 sense that the instruction pointer and data pointer are simply
1188 64-bit offsets into the code segment and the data segment instead
1189 of a selector offset pair. The functions below store the upper 32
1190 bits of these pointers (instead of just the 16-bits of the segment
1193 /* Fill register REGNUM in REGCACHE with the appropriate
1194 floating-point or SSE register value from *FXSAVE. If REGNUM is
1195 -1, do this for all registers. This function masks off any of the
1196 reserved bits in *FXSAVE. */
1199 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
1202 i387_supply_fxsave (regcache
, regnum
, fxsave
);
1204 if (fxsave
&& gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1206 const gdb_byte
*regs
= fxsave
;
1208 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM
)
1209 regcache_raw_supply (regcache
, I387_FISEG_REGNUM
, regs
+ 12);
1210 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM
)
1211 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM
, regs
+ 20);
1215 /* Fill register REGNUM (if it is a floating-point or SSE register) in
1216 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
1217 all registers. This function doesn't touch any of the reserved
1221 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
1224 gdb_byte
*regs
= fxsave
;
1226 i387_collect_fxsave (regcache
, regnum
, fxsave
);
1228 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1230 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM
)
1231 regcache_raw_collect (regcache
, I387_FISEG_REGNUM
, regs
+ 12);
1232 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM
)
1233 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM
, regs
+ 20);