1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 Contributed by Jiri Smid, SuSE Labs.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "opcode/i386.h"
26 #include "arch-utils.h"
28 #include "dummy-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
40 #include "gdb_assert.h"
42 #include "amd64-tdep.h"
43 #include "i387-tdep.h"
45 #include "features/i386/amd64.c"
46 #include "features/i386/amd64-avx.c"
48 /* Note that the AMD64 architecture was previously known as x86-64.
49 The latter is (forever) engraved into the canonical system name as
50 returned by config.guess, and used as the name for the AMD64 port
51 of GNU/Linux. The BSD's have renamed their ports to amd64; they
52 don't like to shout. For GDB we prefer the amd64_-prefix over the
53 x86_64_-prefix since it's so much easier to type. */
55 /* Register information. */
57 static const char *amd64_register_names
[] =
59 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
61 /* %r8 is indeed register number 8. */
62 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
63 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
65 /* %st0 is register number 24. */
66 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
67 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
69 /* %xmm0 is register number 40. */
70 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
71 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
75 static const char *amd64_ymm_names
[] =
77 "ymm0", "ymm1", "ymm2", "ymm3",
78 "ymm4", "ymm5", "ymm6", "ymm7",
79 "ymm8", "ymm9", "ymm10", "ymm11",
80 "ymm12", "ymm13", "ymm14", "ymm15"
83 static const char *amd64_ymmh_names
[] =
85 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
86 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
87 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
88 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
91 /* The registers used to pass integer arguments during a function call. */
92 static int amd64_dummy_call_integer_regs
[] =
94 AMD64_RDI_REGNUM
, /* %rdi */
95 AMD64_RSI_REGNUM
, /* %rsi */
96 AMD64_RDX_REGNUM
, /* %rdx */
97 AMD64_RCX_REGNUM
, /* %rcx */
102 /* DWARF Register Number Mapping as defined in the System V psABI,
105 static int amd64_dwarf_regmap
[] =
107 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
108 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
109 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
110 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
112 /* Frame Pointer Register RBP. */
115 /* Stack Pointer Register RSP. */
118 /* Extended Integer Registers 8 - 15. */
119 8, 9, 10, 11, 12, 13, 14, 15,
121 /* Return Address RA. Mapped to RIP. */
124 /* SSE Registers 0 - 7. */
125 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
126 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
127 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
128 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
130 /* Extended SSE Registers 8 - 15. */
131 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
132 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
133 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
134 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
136 /* Floating Point Registers 0-7. */
137 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
138 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
139 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
140 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
142 /* Control and Status Flags Register. */
145 /* Selector Registers. */
155 /* Segment Base Address Registers. */
161 /* Special Selector Registers. */
165 /* Floating Point Control Registers. */
171 static const int amd64_dwarf_regmap_len
=
172 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
174 /* Convert DWARF register number REG to the appropriate register
175 number used by GDB. */
178 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
181 int ymm0_regnum
= tdep
->ymm0_regnum
;
184 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
185 regnum
= amd64_dwarf_regmap
[reg
];
188 warning (_("Unmapped DWARF Register #%d encountered."), reg
);
189 else if (ymm0_regnum
>= 0
190 && i386_xmm_regnum_p (gdbarch
, regnum
))
191 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
196 /* Map architectural register numbers to gdb register numbers. */
198 static const int amd64_arch_regmap
[16] =
200 AMD64_RAX_REGNUM
, /* %rax */
201 AMD64_RCX_REGNUM
, /* %rcx */
202 AMD64_RDX_REGNUM
, /* %rdx */
203 AMD64_RBX_REGNUM
, /* %rbx */
204 AMD64_RSP_REGNUM
, /* %rsp */
205 AMD64_RBP_REGNUM
, /* %rbp */
206 AMD64_RSI_REGNUM
, /* %rsi */
207 AMD64_RDI_REGNUM
, /* %rdi */
208 AMD64_R8_REGNUM
, /* %r8 */
209 AMD64_R9_REGNUM
, /* %r9 */
210 AMD64_R10_REGNUM
, /* %r10 */
211 AMD64_R11_REGNUM
, /* %r11 */
212 AMD64_R12_REGNUM
, /* %r12 */
213 AMD64_R13_REGNUM
, /* %r13 */
214 AMD64_R14_REGNUM
, /* %r14 */
215 AMD64_R15_REGNUM
/* %r15 */
218 static const int amd64_arch_regmap_len
=
219 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
221 /* Convert architectural register number REG to the appropriate register
222 number used by GDB. */
225 amd64_arch_reg_to_regnum (int reg
)
227 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
229 return amd64_arch_regmap
[reg
];
232 /* Register names for byte pseudo-registers. */
234 static const char *amd64_byte_names
[] =
236 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
237 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
238 "ah", "bh", "ch", "dh"
241 /* Number of lower byte registers. */
242 #define AMD64_NUM_LOWER_BYTE_REGS 16
244 /* Register names for word pseudo-registers. */
246 static const char *amd64_word_names
[] =
248 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
249 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
252 /* Register names for dword pseudo-registers. */
254 static const char *amd64_dword_names
[] =
256 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
257 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
260 /* Return the name of register REGNUM, or the empty string if it is
261 an anonymous register. */
264 amd64_register_name (struct gdbarch
*gdbarch
, int regnum
)
266 /* Hide the upper YMM registers. */
267 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
270 return tdesc_register_name (gdbarch
, regnum
);
273 /* Return the name of register REGNUM. */
276 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
278 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
279 if (i386_byte_regnum_p (gdbarch
, regnum
))
280 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
281 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
282 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
283 else if (i386_word_regnum_p (gdbarch
, regnum
))
284 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
285 else if (i386_dword_regnum_p (gdbarch
, regnum
))
286 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
288 return i386_pseudo_register_name (gdbarch
, regnum
);
292 amd64_pseudo_register_read (struct gdbarch
*gdbarch
,
293 struct regcache
*regcache
,
294 int regnum
, gdb_byte
*buf
)
296 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
297 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
299 if (i386_byte_regnum_p (gdbarch
, regnum
))
301 int gpnum
= regnum
- tdep
->al_regnum
;
303 /* Extract (always little endian). */
304 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
306 /* Special handling for AH, BH, CH, DH. */
307 regcache_raw_read (regcache
,
308 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
309 memcpy (buf
, raw_buf
+ 1, 1);
313 regcache_raw_read (regcache
, gpnum
, raw_buf
);
314 memcpy (buf
, raw_buf
, 1);
317 else if (i386_dword_regnum_p (gdbarch
, regnum
))
319 int gpnum
= regnum
- tdep
->eax_regnum
;
320 /* Extract (always little endian). */
321 regcache_raw_read (regcache
, gpnum
, raw_buf
);
322 memcpy (buf
, raw_buf
, 4);
325 i386_pseudo_register_read (gdbarch
, regcache
, regnum
, buf
);
329 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
330 struct regcache
*regcache
,
331 int regnum
, const gdb_byte
*buf
)
333 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
334 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
336 if (i386_byte_regnum_p (gdbarch
, regnum
))
338 int gpnum
= regnum
- tdep
->al_regnum
;
340 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
342 /* Read ... AH, BH, CH, DH. */
343 regcache_raw_read (regcache
,
344 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
345 /* ... Modify ... (always little endian). */
346 memcpy (raw_buf
+ 1, buf
, 1);
348 regcache_raw_write (regcache
,
349 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
354 regcache_raw_read (regcache
, gpnum
, raw_buf
);
355 /* ... Modify ... (always little endian). */
356 memcpy (raw_buf
, buf
, 1);
358 regcache_raw_write (regcache
, gpnum
, raw_buf
);
361 else if (i386_dword_regnum_p (gdbarch
, regnum
))
363 int gpnum
= regnum
- tdep
->eax_regnum
;
366 regcache_raw_read (regcache
, gpnum
, raw_buf
);
367 /* ... Modify ... (always little endian). */
368 memcpy (raw_buf
, buf
, 4);
370 regcache_raw_write (regcache
, gpnum
, raw_buf
);
373 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
378 /* Return the union class of CLASS1 and CLASS2. See the psABI for
381 static enum amd64_reg_class
382 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
384 /* Rule (a): If both classes are equal, this is the resulting class. */
385 if (class1
== class2
)
388 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
389 is the other class. */
390 if (class1
== AMD64_NO_CLASS
)
392 if (class2
== AMD64_NO_CLASS
)
395 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
396 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
399 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
400 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
401 return AMD64_INTEGER
;
403 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
404 MEMORY is used as class. */
405 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
406 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
407 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
410 /* Rule (f): Otherwise class SSE is used. */
414 /* Return non-zero if TYPE is a non-POD structure or union type. */
417 amd64_non_pod_p (struct type
*type
)
419 /* ??? A class with a base class certainly isn't POD, but does this
420 catch all non-POD structure types? */
421 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
427 /* Classify TYPE according to the rules for aggregate (structures and
428 arrays) and union types, and store the result in CLASS. */
431 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class
class[2])
433 int len
= TYPE_LENGTH (type
);
435 /* 1. If the size of an object is larger than two eightbytes, or in
436 C++, is a non-POD structure or union type, or contains
437 unaligned fields, it has class memory. */
438 if (len
> 16 || amd64_non_pod_p (type
))
440 class[0] = class[1] = AMD64_MEMORY
;
444 /* 2. Both eightbytes get initialized to class NO_CLASS. */
445 class[0] = class[1] = AMD64_NO_CLASS
;
447 /* 3. Each field of an object is classified recursively so that
448 always two fields are considered. The resulting class is
449 calculated according to the classes of the fields in the
452 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
454 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
456 /* All fields in an array have the same type. */
457 amd64_classify (subtype
, class);
458 if (len
> 8 && class[1] == AMD64_NO_CLASS
)
465 /* Structure or union. */
466 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
467 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
469 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
471 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
472 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
473 enum amd64_reg_class subclass
[2];
474 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
478 bitsize
= TYPE_LENGTH (subtype
) * 8;
479 endpos
= (TYPE_FIELD_BITPOS (type
, i
) + bitsize
- 1) / 64;
481 /* Ignore static fields. */
482 if (field_is_static (&TYPE_FIELD (type
, i
)))
485 gdb_assert (pos
== 0 || pos
== 1);
487 amd64_classify (subtype
, subclass
);
488 class[pos
] = amd64_merge_classes (class[pos
], subclass
[0]);
489 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
490 /* This is a bit of an odd case: We have a field that would
491 normally fit in one of the two eightbytes, except that
492 it is placed in a way that this field straddles them.
493 This has been seen with a structure containing an array.
495 The ABI is a bit unclear in this case, but we assume that
496 this field's class (stored in subclass[0]) must also be merged
497 into class[1]. In other words, our field has a piece stored
498 in the second eight-byte, and thus its class applies to
499 the second eight-byte as well.
501 In the case where the field length exceeds 8 bytes,
502 it should not be necessary to merge the field class
503 into class[1]. As LEN > 8, subclass[1] is necessarily
504 different from AMD64_NO_CLASS. If subclass[1] is equal
505 to subclass[0], then the normal class[1]/subclass[1]
506 merging will take care of everything. For subclass[1]
507 to be different from subclass[0], I can only see the case
508 where we have a SSE/SSEUP or X87/X87UP pair, which both
509 use up all 16 bytes of the aggregate, and are already
510 handled just fine (because each portion sits on its own
512 class[1] = amd64_merge_classes (class[1], subclass
[0]);
514 class[1] = amd64_merge_classes (class[1], subclass
[1]);
518 /* 4. Then a post merger cleanup is done: */
520 /* Rule (a): If one of the classes is MEMORY, the whole argument is
522 if (class[0] == AMD64_MEMORY
|| class[1] == AMD64_MEMORY
)
523 class[0] = class[1] = AMD64_MEMORY
;
525 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
527 if (class[0] == AMD64_SSEUP
)
528 class[0] = AMD64_SSE
;
529 if (class[1] == AMD64_SSEUP
&& class[0] != AMD64_SSE
)
530 class[1] = AMD64_SSE
;
533 /* Classify TYPE, and store the result in CLASS. */
536 amd64_classify (struct type
*type
, enum amd64_reg_class
class[2])
538 enum type_code code
= TYPE_CODE (type
);
539 int len
= TYPE_LENGTH (type
);
541 class[0] = class[1] = AMD64_NO_CLASS
;
543 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
544 long, long long, and pointers are in the INTEGER class. Similarly,
545 range types, used by languages such as Ada, are also in the INTEGER
547 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
548 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
549 || code
== TYPE_CODE_CHAR
550 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
551 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
552 class[0] = AMD64_INTEGER
;
554 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
556 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
557 && (len
== 4 || len
== 8))
559 class[0] = AMD64_SSE
;
561 /* Arguments of types __float128, _Decimal128 and __m128 are split into
562 two halves. The least significant ones belong to class SSE, the most
563 significant one to class SSEUP. */
564 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
565 /* FIXME: __float128, __m128. */
566 class[0] = AMD64_SSE
, class[1] = AMD64_SSEUP
;
568 /* The 64-bit mantissa of arguments of type long double belongs to
569 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
571 else if (code
== TYPE_CODE_FLT
&& len
== 16)
572 /* Class X87 and X87UP. */
573 class[0] = AMD64_X87
, class[1] = AMD64_X87UP
;
576 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
577 || code
== TYPE_CODE_UNION
)
578 amd64_classify_aggregate (type
, class);
581 static enum return_value_convention
582 amd64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
583 struct type
*type
, struct regcache
*regcache
,
584 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
586 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
587 enum amd64_reg_class
class[2];
588 int len
= TYPE_LENGTH (type
);
589 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
590 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
595 gdb_assert (!(readbuf
&& writebuf
));
596 gdb_assert (tdep
->classify
);
598 /* 1. Classify the return type with the classification algorithm. */
599 tdep
->classify (type
, class);
601 /* 2. If the type has class MEMORY, then the caller provides space
602 for the return value and passes the address of this storage in
603 %rdi as if it were the first argument to the function. In effect,
604 this address becomes a hidden first argument.
606 On return %rax will contain the address that has been passed in
607 by the caller in %rdi. */
608 if (class[0] == AMD64_MEMORY
)
610 /* As indicated by the comment above, the ABI guarantees that we
611 can always find the return value just after the function has
618 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
619 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
622 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
625 gdb_assert (class[1] != AMD64_MEMORY
);
626 gdb_assert (len
<= 16);
628 for (i
= 0; len
> 0; i
++, len
-= 8)
636 /* 3. If the class is INTEGER, the next available register
637 of the sequence %rax, %rdx is used. */
638 regnum
= integer_regnum
[integer_reg
++];
642 /* 4. If the class is SSE, the next available SSE register
643 of the sequence %xmm0, %xmm1 is used. */
644 regnum
= sse_regnum
[sse_reg
++];
648 /* 5. If the class is SSEUP, the eightbyte is passed in the
649 upper half of the last used SSE register. */
650 gdb_assert (sse_reg
> 0);
651 regnum
= sse_regnum
[sse_reg
- 1];
656 /* 6. If the class is X87, the value is returned on the X87
657 stack in %st0 as 80-bit x87 number. */
658 regnum
= AMD64_ST0_REGNUM
;
660 i387_return_value (gdbarch
, regcache
);
664 /* 7. If the class is X87UP, the value is returned together
665 with the previous X87 value in %st0. */
666 gdb_assert (i
> 0 && class[0] == AMD64_X87
);
667 regnum
= AMD64_ST0_REGNUM
;
676 gdb_assert (!"Unexpected register class.");
679 gdb_assert (regnum
!= -1);
682 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
685 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
689 return RETURN_VALUE_REGISTER_CONVENTION
;
694 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
695 struct value
**args
, CORE_ADDR sp
, int struct_return
)
697 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
698 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
699 int *integer_regs
= tdep
->call_dummy_integer_regs
;
700 int num_integer_regs
= tdep
->call_dummy_num_integer_regs
;
702 static int sse_regnum
[] =
704 /* %xmm0 ... %xmm7 */
705 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
706 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
707 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
708 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
710 struct value
**stack_args
= alloca (nargs
* sizeof (struct value
*));
711 /* An array that mirrors the stack_args array. For all arguments
712 that are passed by MEMORY, if that argument's address also needs
713 to be stored in a register, the ARG_ADDR_REGNO array will contain
714 that register number (or a negative value otherwise). */
715 int *arg_addr_regno
= alloca (nargs
* sizeof (int));
716 int num_stack_args
= 0;
717 int num_elements
= 0;
723 gdb_assert (tdep
->classify
);
725 /* Reserve a register for the "hidden" argument. */
729 for (i
= 0; i
< nargs
; i
++)
731 struct type
*type
= value_type (args
[i
]);
732 int len
= TYPE_LENGTH (type
);
733 enum amd64_reg_class
class[2];
734 int needed_integer_regs
= 0;
735 int needed_sse_regs
= 0;
738 /* Classify argument. */
739 tdep
->classify (type
, class);
741 /* Calculate the number of integer and SSE registers needed for
743 for (j
= 0; j
< 2; j
++)
745 if (class[j
] == AMD64_INTEGER
)
746 needed_integer_regs
++;
747 else if (class[j
] == AMD64_SSE
)
751 /* Check whether enough registers are available, and if the
752 argument should be passed in registers at all. */
753 if (integer_reg
+ needed_integer_regs
> num_integer_regs
754 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
755 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
757 /* The argument will be passed on the stack. */
758 num_elements
+= ((len
+ 7) / 8);
759 stack_args
[num_stack_args
] = args
[i
];
760 /* If this is an AMD64_MEMORY argument whose address must also
761 be passed in one of the integer registers, reserve that
762 register and associate this value to that register so that
763 we can store the argument address as soon as we know it. */
764 if (class[0] == AMD64_MEMORY
765 && tdep
->memory_args_by_pointer
766 && integer_reg
< tdep
->call_dummy_num_integer_regs
)
767 arg_addr_regno
[num_stack_args
] =
768 tdep
->call_dummy_integer_regs
[integer_reg
++];
770 arg_addr_regno
[num_stack_args
] = -1;
775 /* The argument will be passed in registers. */
776 const gdb_byte
*valbuf
= value_contents (args
[i
]);
779 gdb_assert (len
<= 16);
781 for (j
= 0; len
> 0; j
++, len
-= 8)
789 regnum
= integer_regs
[integer_reg
++];
793 regnum
= sse_regnum
[sse_reg
++];
797 gdb_assert (sse_reg
> 0);
798 regnum
= sse_regnum
[sse_reg
- 1];
803 gdb_assert (!"Unexpected register class.");
806 gdb_assert (regnum
!= -1);
807 memset (buf
, 0, sizeof buf
);
808 memcpy (buf
, valbuf
+ j
* 8, min (len
, 8));
809 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
814 /* Allocate space for the arguments on the stack. */
815 sp
-= num_elements
* 8;
817 /* The psABI says that "The end of the input argument area shall be
818 aligned on a 16 byte boundary." */
821 /* Write out the arguments to the stack. */
822 for (i
= 0; i
< num_stack_args
; i
++)
824 struct type
*type
= value_type (stack_args
[i
]);
825 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
826 int len
= TYPE_LENGTH (type
);
827 CORE_ADDR arg_addr
= sp
+ element
* 8;
829 write_memory (arg_addr
, valbuf
, len
);
830 if (arg_addr_regno
[i
] >= 0)
832 /* We also need to store the address of that argument in
833 the given register. */
835 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
837 store_unsigned_integer (buf
, 8, byte_order
, arg_addr
);
838 regcache_cooked_write (regcache
, arg_addr_regno
[i
], buf
);
840 element
+= ((len
+ 7) / 8);
843 /* The psABI says that "For calls that may call functions that use
844 varargs or stdargs (prototype-less calls or calls to functions
845 containing ellipsis (...) in the declaration) %al is used as
846 hidden argument to specify the number of SSE registers used. */
847 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
852 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
853 struct regcache
*regcache
, CORE_ADDR bp_addr
,
854 int nargs
, struct value
**args
, CORE_ADDR sp
,
855 int struct_return
, CORE_ADDR struct_addr
)
857 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
858 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
861 /* Pass arguments. */
862 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, struct_return
);
864 /* Pass "hidden" argument". */
867 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
868 /* The "hidden" argument is passed throught the first argument
870 const int arg_regnum
= tdep
->call_dummy_integer_regs
[0];
872 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
873 regcache_cooked_write (regcache
, arg_regnum
, buf
);
876 /* Reserve some memory on the stack for the integer-parameter registers,
877 if required by the ABI. */
878 if (tdep
->integer_param_regs_saved_in_caller_frame
)
879 sp
-= tdep
->call_dummy_num_integer_regs
* 8;
881 /* Store return address. */
883 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
884 write_memory (sp
, buf
, 8);
886 /* Finally, update the stack pointer... */
887 store_unsigned_integer (buf
, 8, byte_order
, sp
);
888 regcache_cooked_write (regcache
, AMD64_RSP_REGNUM
, buf
);
890 /* ...and fake a frame pointer. */
891 regcache_cooked_write (regcache
, AMD64_RBP_REGNUM
, buf
);
896 /* Displaced instruction handling. */
898 /* A partially decoded instruction.
899 This contains enough details for displaced stepping purposes. */
903 /* The number of opcode bytes. */
905 /* The offset of the rex prefix or -1 if not present. */
907 /* The offset to the first opcode byte. */
909 /* The offset to the modrm byte or -1 if not present. */
912 /* The raw instruction. */
916 struct displaced_step_closure
918 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
923 /* Details of the instruction. */
924 struct amd64_insn insn_details
;
926 /* Amount of space allocated to insn_buf. */
929 /* The possibly modified insn.
930 This is a variable-length field. */
931 gdb_byte insn_buf
[1];
934 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
935 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
936 at which point delete these in favor of libopcodes' versions). */
938 static const unsigned char onebyte_has_modrm
[256] = {
939 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
940 /* ------------------------------- */
941 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
942 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
943 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
944 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
945 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
946 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
947 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
948 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
949 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
950 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
951 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
952 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
953 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
954 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
955 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
956 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
957 /* ------------------------------- */
958 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
961 static const unsigned char twobyte_has_modrm
[256] = {
962 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
963 /* ------------------------------- */
964 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
965 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
966 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
967 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
968 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
969 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
970 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
971 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
972 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
973 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
974 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
975 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
976 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
977 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
978 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
979 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
980 /* ------------------------------- */
981 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
984 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
987 rex_prefix_p (gdb_byte pfx
)
989 return REX_PREFIX_P (pfx
);
992 /* Skip the legacy instruction prefixes in INSN.
993 We assume INSN is properly sentineled so we don't have to worry
994 about falling off the end of the buffer. */
997 amd64_skip_prefixes (gdb_byte
*insn
)
1003 case DATA_PREFIX_OPCODE
:
1004 case ADDR_PREFIX_OPCODE
:
1005 case CS_PREFIX_OPCODE
:
1006 case DS_PREFIX_OPCODE
:
1007 case ES_PREFIX_OPCODE
:
1008 case FS_PREFIX_OPCODE
:
1009 case GS_PREFIX_OPCODE
:
1010 case SS_PREFIX_OPCODE
:
1011 case LOCK_PREFIX_OPCODE
:
1012 case REPE_PREFIX_OPCODE
:
1013 case REPNE_PREFIX_OPCODE
:
1025 /* Return an integer register (other than RSP) that is unused as an input
1027 In order to not require adding a rex prefix if the insn doesn't already
1028 have one, the result is restricted to RAX ... RDI, sans RSP.
1029 The register numbering of the result follows architecture ordering,
1033 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1035 /* 1 bit for each reg */
1036 int used_regs_mask
= 0;
1038 /* There can be at most 3 int regs used as inputs in an insn, and we have
1039 7 to choose from (RAX ... RDI, sans RSP).
1040 This allows us to take a conservative approach and keep things simple.
1041 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1042 that implicitly specify RAX. */
1045 used_regs_mask
|= 1 << EAX_REG_NUM
;
1046 /* Similarily avoid RDX, implicit operand in divides. */
1047 used_regs_mask
|= 1 << EDX_REG_NUM
;
1049 used_regs_mask
|= 1 << ESP_REG_NUM
;
1051 /* If the opcode is one byte long and there's no ModRM byte,
1052 assume the opcode specifies a register. */
1053 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1054 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1056 /* Mark used regs in the modrm/sib bytes. */
1057 if (details
->modrm_offset
!= -1)
1059 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1060 int mod
= MODRM_MOD_FIELD (modrm
);
1061 int reg
= MODRM_REG_FIELD (modrm
);
1062 int rm
= MODRM_RM_FIELD (modrm
);
1063 int have_sib
= mod
!= 3 && rm
== 4;
1065 /* Assume the reg field of the modrm byte specifies a register. */
1066 used_regs_mask
|= 1 << reg
;
1070 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1071 int index
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1072 used_regs_mask
|= 1 << base
;
1073 used_regs_mask
|= 1 << index
;
1077 used_regs_mask
|= 1 << rm
;
1081 gdb_assert (used_regs_mask
< 256);
1082 gdb_assert (used_regs_mask
!= 255);
1084 /* Finally, find a free reg. */
1088 for (i
= 0; i
< 8; ++i
)
1090 if (! (used_regs_mask
& (1 << i
)))
1094 /* We shouldn't get here. */
1095 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1099 /* Extract the details of INSN that we need. */
1102 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1104 gdb_byte
*start
= insn
;
1107 details
->raw_insn
= insn
;
1109 details
->opcode_len
= -1;
1110 details
->rex_offset
= -1;
1111 details
->opcode_offset
= -1;
1112 details
->modrm_offset
= -1;
1114 /* Skip legacy instruction prefixes. */
1115 insn
= amd64_skip_prefixes (insn
);
1117 /* Skip REX instruction prefix. */
1118 if (rex_prefix_p (*insn
))
1120 details
->rex_offset
= insn
- start
;
1124 details
->opcode_offset
= insn
- start
;
1126 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1128 /* Two or three-byte opcode. */
1130 need_modrm
= twobyte_has_modrm
[*insn
];
1132 /* Check for three-byte opcode. */
1142 details
->opcode_len
= 3;
1145 details
->opcode_len
= 2;
1151 /* One-byte opcode. */
1152 need_modrm
= onebyte_has_modrm
[*insn
];
1153 details
->opcode_len
= 1;
1159 details
->modrm_offset
= insn
- start
;
1163 /* Update %rip-relative addressing in INSN.
1165 %rip-relative addressing only uses a 32-bit displacement.
1166 32 bits is not enough to be guaranteed to cover the distance between where
1167 the real instruction is and where its copy is.
1168 Convert the insn to use base+disp addressing.
1169 We set base = pc + insn_length so we can leave disp unchanged. */
1172 fixup_riprel (struct gdbarch
*gdbarch
, struct displaced_step_closure
*dsc
,
1173 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1175 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1176 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1177 int modrm_offset
= insn_details
->modrm_offset
;
1178 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1182 int arch_tmp_regno
, tmp_regno
;
1183 ULONGEST orig_value
;
1185 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1188 /* Compute the rip-relative address. */
1189 disp
= extract_signed_integer (insn
, sizeof (int32_t), byte_order
);
1190 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
,
1191 dsc
->max_len
, from
);
1192 rip_base
= from
+ insn_length
;
1194 /* We need a register to hold the address.
1195 Pick one not used in the insn.
1196 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1197 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1198 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1200 /* REX.B should be unset as we were using rip-relative addressing,
1201 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1202 if (insn_details
->rex_offset
!= -1)
1203 dsc
->insn_buf
[insn_details
->rex_offset
] &= ~REX_B
;
1205 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1206 dsc
->tmp_regno
= tmp_regno
;
1207 dsc
->tmp_save
= orig_value
;
1210 /* Convert the ModRM field to be base+disp. */
1211 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1212 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1214 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1216 if (debug_displaced
)
1217 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1218 "displaced: using temp reg %d, old value %s, new value %s\n",
1219 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1220 paddress (gdbarch
, rip_base
));
1224 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1225 struct displaced_step_closure
*dsc
,
1226 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1228 const struct amd64_insn
*details
= &dsc
->insn_details
;
1230 if (details
->modrm_offset
!= -1)
1232 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1234 if ((modrm
& 0xc7) == 0x05)
1236 /* The insn uses rip-relative addressing.
1238 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1243 struct displaced_step_closure
*
1244 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1245 CORE_ADDR from
, CORE_ADDR to
,
1246 struct regcache
*regs
)
1248 int len
= gdbarch_max_insn_length (gdbarch
);
1249 /* Extra space for sentinels so fixup_{riprel,displaced_copy don't have to
1250 continually watch for running off the end of the buffer. */
1251 int fixup_sentinel_space
= len
;
1252 struct displaced_step_closure
*dsc
=
1253 xmalloc (sizeof (*dsc
) + len
+ fixup_sentinel_space
);
1254 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1255 struct amd64_insn
*details
= &dsc
->insn_details
;
1258 dsc
->max_len
= len
+ fixup_sentinel_space
;
1260 read_memory (from
, buf
, len
);
1262 /* Set up the sentinel space so we don't have to worry about running
1263 off the end of the buffer. An excessive number of leading prefixes
1264 could otherwise cause this. */
1265 memset (buf
+ len
, 0, fixup_sentinel_space
);
1267 amd64_get_insn_details (buf
, details
);
1269 /* GDB may get control back after the insn after the syscall.
1270 Presumably this is a kernel bug.
1271 If this is a syscall, make sure there's a nop afterwards. */
1275 if (amd64_syscall_p (details
, &syscall_length
))
1276 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1279 /* Modify the insn to cope with the address where it will be executed from.
1280 In particular, handle any rip-relative addressing. */
1281 fixup_displaced_copy (gdbarch
, dsc
, from
, to
, regs
);
1283 write_memory (to
, buf
, len
);
1285 if (debug_displaced
)
1287 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1288 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1289 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1296 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1298 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1300 if (insn
[0] == 0xff)
1302 /* jump near, absolute indirect (/4) */
1303 if ((insn
[1] & 0x38) == 0x20)
1306 /* jump far, absolute indirect (/5) */
1307 if ((insn
[1] & 0x38) == 0x28)
1315 amd64_absolute_call_p (const struct amd64_insn
*details
)
1317 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1319 if (insn
[0] == 0xff)
1321 /* Call near, absolute indirect (/2) */
1322 if ((insn
[1] & 0x38) == 0x10)
1325 /* Call far, absolute indirect (/3) */
1326 if ((insn
[1] & 0x38) == 0x18)
1334 amd64_ret_p (const struct amd64_insn
*details
)
1336 /* NOTE: gcc can emit "repz ; ret". */
1337 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1341 case 0xc2: /* ret near, pop N bytes */
1342 case 0xc3: /* ret near */
1343 case 0xca: /* ret far, pop N bytes */
1344 case 0xcb: /* ret far */
1345 case 0xcf: /* iret */
1354 amd64_call_p (const struct amd64_insn
*details
)
1356 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1358 if (amd64_absolute_call_p (details
))
1361 /* call near, relative */
1362 if (insn
[0] == 0xe8)
1368 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1369 length in bytes. Otherwise, return zero. */
1372 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1374 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1376 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1385 /* Fix up the state of registers and memory after having single-stepped
1386 a displaced instruction. */
1389 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1390 struct displaced_step_closure
*dsc
,
1391 CORE_ADDR from
, CORE_ADDR to
,
1392 struct regcache
*regs
)
1394 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1395 /* The offset we applied to the instruction's address. */
1396 ULONGEST insn_offset
= to
- from
;
1397 gdb_byte
*insn
= dsc
->insn_buf
;
1398 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1400 if (debug_displaced
)
1401 fprintf_unfiltered (gdb_stdlog
,
1402 "displaced: fixup (%s, %s), "
1403 "insn = 0x%02x 0x%02x ...\n",
1404 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1407 /* If we used a tmp reg, restore it. */
1411 if (debug_displaced
)
1412 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1413 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1414 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1417 /* The list of issues to contend with here is taken from
1418 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1419 Yay for Free Software! */
1421 /* Relocate the %rip back to the program's instruction stream,
1424 /* Except in the case of absolute or indirect jump or call
1425 instructions, or a return instruction, the new rip is relative to
1426 the displaced instruction; make it relative to the original insn.
1427 Well, signal handler returns don't need relocation either, but we use the
1428 value of %rip to recognize those; see below. */
1429 if (! amd64_absolute_jmp_p (insn_details
)
1430 && ! amd64_absolute_call_p (insn_details
)
1431 && ! amd64_ret_p (insn_details
))
1436 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1438 /* A signal trampoline system call changes the %rip, resuming
1439 execution of the main program after the signal handler has
1440 returned. That makes them like 'return' instructions; we
1441 shouldn't relocate %rip.
1443 But most system calls don't, and we do need to relocate %rip.
1445 Our heuristic for distinguishing these cases: if stepping
1446 over the system call instruction left control directly after
1447 the instruction, the we relocate --- control almost certainly
1448 doesn't belong in the displaced copy. Otherwise, we assume
1449 the instruction has put control where it belongs, and leave
1450 it unrelocated. Goodness help us if there are PC-relative
1452 if (amd64_syscall_p (insn_details
, &insn_len
)
1453 && orig_rip
!= to
+ insn_len
1454 /* GDB can get control back after the insn after the syscall.
1455 Presumably this is a kernel bug.
1456 Fixup ensures its a nop, we add one to the length for it. */
1457 && orig_rip
!= to
+ insn_len
+ 1)
1459 if (debug_displaced
)
1460 fprintf_unfiltered (gdb_stdlog
,
1461 "displaced: syscall changed %%rip; "
1462 "not relocating\n");
1466 ULONGEST rip
= orig_rip
- insn_offset
;
1468 /* If we just stepped over a breakpoint insn, we don't backup
1469 the pc on purpose; this is to match behaviour without
1472 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1474 if (debug_displaced
)
1475 fprintf_unfiltered (gdb_stdlog
,
1477 "relocated %%rip from %s to %s\n",
1478 paddress (gdbarch
, orig_rip
),
1479 paddress (gdbarch
, rip
));
1483 /* If the instruction was PUSHFL, then the TF bit will be set in the
1484 pushed value, and should be cleared. We'll leave this for later,
1485 since GDB already messes up the TF flag when stepping over a
1488 /* If the instruction was a call, the return address now atop the
1489 stack is the address following the copied instruction. We need
1490 to make it the address following the original instruction. */
1491 if (amd64_call_p (insn_details
))
1495 const ULONGEST retaddr_len
= 8;
1497 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1498 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1499 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
1500 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1502 if (debug_displaced
)
1503 fprintf_unfiltered (gdb_stdlog
,
1504 "displaced: relocated return addr at %s "
1506 paddress (gdbarch
, rsp
),
1507 paddress (gdbarch
, retaddr
));
1511 /* The maximum number of saved registers. This should include %rip. */
1512 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1514 struct amd64_frame_cache
1518 CORE_ADDR sp_offset
;
1521 /* Saved registers. */
1522 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1526 /* Do we have a frame? */
1530 /* Initialize a frame cache. */
1533 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1539 cache
->sp_offset
= -8;
1542 /* Saved registers. We initialize these to -1 since zero is a valid
1543 offset (that's where %rbp is supposed to be stored).
1544 The values start out as being offsets, and are later converted to
1545 addresses (at which point -1 is interpreted as an address, still meaning
1547 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1548 cache
->saved_regs
[i
] = -1;
1549 cache
->saved_sp
= 0;
1550 cache
->saved_sp_reg
= -1;
1552 /* Frameless until proven otherwise. */
1553 cache
->frameless_p
= 1;
1556 /* Allocate and initialize a frame cache. */
1558 static struct amd64_frame_cache
*
1559 amd64_alloc_frame_cache (void)
1561 struct amd64_frame_cache
*cache
;
1563 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1564 amd64_init_frame_cache (cache
);
1568 /* GCC 4.4 and later, can put code in the prologue to realign the
1569 stack pointer. Check whether PC points to such code, and update
1570 CACHE accordingly. Return the first instruction after the code
1571 sequence or CURRENT_PC, whichever is smaller. If we don't
1572 recognize the code, return PC. */
1575 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1576 struct amd64_frame_cache
*cache
)
1578 /* There are 2 code sequences to re-align stack before the frame
1581 1. Use a caller-saved saved register:
1587 2. Use a callee-saved saved register:
1594 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1596 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1597 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1602 int offset
, offset_and
;
1604 if (target_read_memory (pc
, buf
, sizeof buf
))
1607 /* Check caller-saved saved register. The first instruction has
1608 to be "leaq 8(%rsp), %reg". */
1609 if ((buf
[0] & 0xfb) == 0x48
1614 /* MOD must be binary 10 and R/M must be binary 100. */
1615 if ((buf
[2] & 0xc7) != 0x44)
1618 /* REG has register number. */
1619 reg
= (buf
[2] >> 3) & 7;
1621 /* Check the REX.R bit. */
1629 /* Check callee-saved saved register. The first instruction
1630 has to be "pushq %reg". */
1632 if ((buf
[0] & 0xf8) == 0x50)
1634 else if ((buf
[0] & 0xf6) == 0x40
1635 && (buf
[1] & 0xf8) == 0x50)
1637 /* Check the REX.B bit. */
1638 if ((buf
[0] & 1) != 0)
1647 reg
+= buf
[offset
] & 0x7;
1651 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1652 if ((buf
[offset
] & 0xfb) != 0x48
1653 || buf
[offset
+ 1] != 0x8d
1654 || buf
[offset
+ 3] != 0x24
1655 || buf
[offset
+ 4] != 0x10)
1658 /* MOD must be binary 10 and R/M must be binary 100. */
1659 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
1662 /* REG has register number. */
1663 r
= (buf
[offset
+ 2] >> 3) & 7;
1665 /* Check the REX.R bit. */
1666 if (buf
[offset
] == 0x4c)
1669 /* Registers in pushq and leaq have to be the same. */
1676 /* Rigister can't be %rsp nor %rbp. */
1677 if (reg
== 4 || reg
== 5)
1680 /* The next instruction has to be "andq $-XXX, %rsp". */
1681 if (buf
[offset
] != 0x48
1682 || buf
[offset
+ 2] != 0xe4
1683 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
1686 offset_and
= offset
;
1687 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
1689 /* The next instruction has to be "pushq -8(%reg)". */
1691 if (buf
[offset
] == 0xff)
1693 else if ((buf
[offset
] & 0xf6) == 0x40
1694 && buf
[offset
+ 1] == 0xff)
1696 /* Check the REX.B bit. */
1697 if ((buf
[offset
] & 0x1) != 0)
1704 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
1706 if (buf
[offset
+ 1] != 0xf8
1707 || (buf
[offset
] & 0xf8) != 0x70)
1710 /* R/M has register. */
1711 r
+= buf
[offset
] & 7;
1713 /* Registers in leaq and pushq have to be the same. */
1717 if (current_pc
> pc
+ offset_and
)
1718 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
1720 return min (pc
+ offset
+ 2, current_pc
);
1723 /* Do a limited analysis of the prologue at PC and update CACHE
1724 accordingly. Bail out early if CURRENT_PC is reached. Return the
1725 address where the analysis stopped.
1727 We will handle only functions beginning with:
1730 movq %rsp, %rbp 0x48 0x89 0xe5
1732 Any function that doesn't start with this sequence will be assumed
1733 to have no prologue and thus no valid frame pointer in %rbp. */
1736 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
1737 CORE_ADDR pc
, CORE_ADDR current_pc
,
1738 struct amd64_frame_cache
*cache
)
1740 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1741 static gdb_byte proto
[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */
1745 if (current_pc
<= pc
)
1748 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
1750 op
= read_memory_unsigned_integer (pc
, 1, byte_order
);
1752 if (op
== 0x55) /* pushq %rbp */
1754 /* Take into account that we've executed the `pushq %rbp' that
1755 starts this instruction sequence. */
1756 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
1757 cache
->sp_offset
+= 8;
1759 /* If that's all, return now. */
1760 if (current_pc
<= pc
+ 1)
1763 /* Check for `movq %rsp, %rbp'. */
1764 read_memory (pc
+ 1, buf
, 3);
1765 if (memcmp (buf
, proto
, 3) != 0)
1768 /* OK, we actually have a frame. */
1769 cache
->frameless_p
= 0;
1776 /* Return PC of first real instruction. */
1779 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1781 struct amd64_frame_cache cache
;
1784 amd64_init_frame_cache (&cache
);
1785 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
1787 if (cache
.frameless_p
)
1794 /* Normal frames. */
1796 static struct amd64_frame_cache
*
1797 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1799 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1800 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1801 struct amd64_frame_cache
*cache
;
1808 cache
= amd64_alloc_frame_cache ();
1809 *this_cache
= cache
;
1811 cache
->pc
= get_frame_func (this_frame
);
1813 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1816 if (cache
->saved_sp_reg
!= -1)
1818 /* Stack pointer has been saved. */
1819 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1820 cache
->saved_sp
= extract_unsigned_integer(buf
, 8, byte_order
);
1823 if (cache
->frameless_p
)
1825 /* We didn't find a valid frame. If we're at the start of a
1826 function, or somewhere half-way its prologue, the function's
1827 frame probably hasn't been fully setup yet. Try to
1828 reconstruct the base address for the stack frame by looking
1829 at the stack pointer. For truly "frameless" functions this
1832 if (cache
->saved_sp_reg
!= -1)
1834 /* We're halfway aligning the stack. */
1835 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
1836 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
1838 /* This will be added back below. */
1839 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
1843 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
1844 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
1850 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
1851 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
1854 /* Now that we have the base address for the stack frame we can
1855 calculate the value of %rsp in the calling frame. */
1856 cache
->saved_sp
= cache
->base
+ 16;
1858 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
1859 frame we find it at the same offset from the reconstructed base
1860 address. If we're halfway aligning the stack, %rip is handled
1861 differently (see above). */
1862 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
1863 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
1865 /* Adjust all the saved registers such that they contain addresses
1866 instead of offsets. */
1867 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1868 if (cache
->saved_regs
[i
] != -1)
1869 cache
->saved_regs
[i
] += cache
->base
;
1875 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1876 struct frame_id
*this_id
)
1878 struct amd64_frame_cache
*cache
=
1879 amd64_frame_cache (this_frame
, this_cache
);
1881 /* This marks the outermost frame. */
1882 if (cache
->base
== 0)
1885 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
1888 static struct value
*
1889 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1892 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1893 struct amd64_frame_cache
*cache
=
1894 amd64_frame_cache (this_frame
, this_cache
);
1896 gdb_assert (regnum
>= 0);
1898 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
1899 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1901 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1902 return frame_unwind_got_memory (this_frame
, regnum
,
1903 cache
->saved_regs
[regnum
]);
1905 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1908 static const struct frame_unwind amd64_frame_unwind
=
1911 amd64_frame_this_id
,
1912 amd64_frame_prev_register
,
1914 default_frame_sniffer
1918 /* Signal trampolines. */
1920 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
1921 64-bit variants. This would require using identical frame caches
1922 on both platforms. */
1924 static struct amd64_frame_cache
*
1925 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1927 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1928 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1929 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1930 struct amd64_frame_cache
*cache
;
1938 cache
= amd64_alloc_frame_cache ();
1940 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
1941 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
1943 addr
= tdep
->sigcontext_addr (this_frame
);
1944 gdb_assert (tdep
->sc_reg_offset
);
1945 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
1946 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1947 if (tdep
->sc_reg_offset
[i
] != -1)
1948 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1950 *this_cache
= cache
;
1955 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
1956 void **this_cache
, struct frame_id
*this_id
)
1958 struct amd64_frame_cache
*cache
=
1959 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
1961 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
1964 static struct value
*
1965 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
1966 void **this_cache
, int regnum
)
1968 /* Make sure we've initialized the cache. */
1969 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
1971 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
1975 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
1976 struct frame_info
*this_frame
,
1979 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1981 /* We shouldn't even bother if we don't have a sigcontext_addr
1983 if (tdep
->sigcontext_addr
== NULL
)
1986 if (tdep
->sigtramp_p
!= NULL
)
1988 if (tdep
->sigtramp_p (this_frame
))
1992 if (tdep
->sigtramp_start
!= 0)
1994 CORE_ADDR pc
= get_frame_pc (this_frame
);
1996 gdb_assert (tdep
->sigtramp_end
!= 0);
1997 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2004 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2007 amd64_sigtramp_frame_this_id
,
2008 amd64_sigtramp_frame_prev_register
,
2010 amd64_sigtramp_frame_sniffer
2015 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2017 struct amd64_frame_cache
*cache
=
2018 amd64_frame_cache (this_frame
, this_cache
);
2023 static const struct frame_base amd64_frame_base
=
2025 &amd64_frame_unwind
,
2026 amd64_frame_base_address
,
2027 amd64_frame_base_address
,
2028 amd64_frame_base_address
2031 /* Normal frames, but in a function epilogue. */
2033 /* The epilogue is defined here as the 'ret' instruction, which will
2034 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2035 the function's stack frame. */
2038 amd64_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2042 if (target_read_memory (pc
, &insn
, 1))
2043 return 0; /* Can't read memory at pc. */
2045 if (insn
!= 0xc3) /* 'ret' instruction. */
2052 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2053 struct frame_info
*this_frame
,
2054 void **this_prologue_cache
)
2056 if (frame_relative_level (this_frame
) == 0)
2057 return amd64_in_function_epilogue_p (get_frame_arch (this_frame
),
2058 get_frame_pc (this_frame
));
2063 static struct amd64_frame_cache
*
2064 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2066 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2067 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2068 struct amd64_frame_cache
*cache
;
2074 cache
= amd64_alloc_frame_cache ();
2075 *this_cache
= cache
;
2077 /* Cache base will be %esp plus cache->sp_offset (-8). */
2078 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2079 cache
->base
= extract_unsigned_integer (buf
, 8,
2080 byte_order
) + cache
->sp_offset
;
2082 /* Cache pc will be the frame func. */
2083 cache
->pc
= get_frame_pc (this_frame
);
2085 /* The saved %esp will be at cache->base plus 16. */
2086 cache
->saved_sp
= cache
->base
+ 16;
2088 /* The saved %eip will be at cache->base plus 8. */
2089 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2095 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2097 struct frame_id
*this_id
)
2099 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2102 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2105 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2108 amd64_epilogue_frame_this_id
,
2109 amd64_frame_prev_register
,
2111 amd64_epilogue_frame_sniffer
2114 static struct frame_id
2115 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2119 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2121 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2124 /* 16 byte align the SP per frame requirements. */
2127 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2129 return sp
& -(CORE_ADDR
)16;
2133 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2134 in the floating-point register set REGSET to register cache
2135 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2138 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2139 int regnum
, const void *fpregs
, size_t len
)
2141 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2143 gdb_assert (len
== tdep
->sizeof_fpregset
);
2144 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
2147 /* Collect register REGNUM from the register cache REGCACHE and store
2148 it in the buffer specified by FPREGS and LEN as described by the
2149 floating-point register set REGSET. If REGNUM is -1, do this for
2150 all registers in REGSET. */
2153 amd64_collect_fpregset (const struct regset
*regset
,
2154 const struct regcache
*regcache
,
2155 int regnum
, void *fpregs
, size_t len
)
2157 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2159 gdb_assert (len
== tdep
->sizeof_fpregset
);
2160 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
2163 /* Similar to amd64_supply_fpregset, but use XSAVE extended state. */
2166 amd64_supply_xstateregset (const struct regset
*regset
,
2167 struct regcache
*regcache
, int regnum
,
2168 const void *xstateregs
, size_t len
)
2170 amd64_supply_xsave (regcache
, regnum
, xstateregs
);
2173 /* Similar to amd64_collect_fpregset, but use XSAVE extended state. */
2176 amd64_collect_xstateregset (const struct regset
*regset
,
2177 const struct regcache
*regcache
,
2178 int regnum
, void *xstateregs
, size_t len
)
2180 amd64_collect_xsave (regcache
, regnum
, xstateregs
, 1);
2183 /* Return the appropriate register set for the core section identified
2184 by SECT_NAME and SECT_SIZE. */
2186 static const struct regset
*
2187 amd64_regset_from_core_section (struct gdbarch
*gdbarch
,
2188 const char *sect_name
, size_t sect_size
)
2190 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2192 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2194 if (tdep
->fpregset
== NULL
)
2195 tdep
->fpregset
= regset_alloc (gdbarch
, amd64_supply_fpregset
,
2196 amd64_collect_fpregset
);
2198 return tdep
->fpregset
;
2201 if (strcmp (sect_name
, ".reg-xstate") == 0)
2203 if (tdep
->xstateregset
== NULL
)
2204 tdep
->xstateregset
= regset_alloc (gdbarch
,
2205 amd64_supply_xstateregset
,
2206 amd64_collect_xstateregset
);
2208 return tdep
->xstateregset
;
2211 return i386_regset_from_core_section (gdbarch
, sect_name
, sect_size
);
2215 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2216 %rdi. We expect its value to be a pointer to the jmp_buf structure
2217 from which we extract the address that we will land at. This
2218 address is copied into PC. This routine returns non-zero on
2222 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2226 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2227 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2228 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
2230 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2231 longjmp will land. */
2232 if (jb_pc_offset
== -1)
2235 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
2236 jb_addr
= extract_typed_address
2237 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
2238 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
2241 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
2246 static const int amd64_record_regmap
[] =
2248 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
2249 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
2250 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
2251 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
2252 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
2253 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
2257 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2259 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2260 const struct target_desc
*tdesc
= info
.target_desc
;
2262 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2263 floating-point registers. */
2264 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
2266 if (! tdesc_has_registers (tdesc
))
2267 tdesc
= tdesc_amd64
;
2268 tdep
->tdesc
= tdesc
;
2270 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
2271 tdep
->register_names
= amd64_register_names
;
2273 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
2275 tdep
->ymmh_register_names
= amd64_ymmh_names
;
2276 tdep
->num_ymm_regs
= 16;
2277 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
2280 tdep
->num_byte_regs
= 20;
2281 tdep
->num_word_regs
= 16;
2282 tdep
->num_dword_regs
= 16;
2283 /* Avoid wiring in the MMX registers for now. */
2284 tdep
->num_mmx_regs
= 0;
2286 set_gdbarch_pseudo_register_read (gdbarch
,
2287 amd64_pseudo_register_read
);
2288 set_gdbarch_pseudo_register_write (gdbarch
,
2289 amd64_pseudo_register_write
);
2291 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
2293 set_gdbarch_register_name (gdbarch
, amd64_register_name
);
2295 /* AMD64 has an FPU and 16 SSE registers. */
2296 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
2297 tdep
->num_xmm_regs
= 16;
2299 /* This is what all the fuss is about. */
2300 set_gdbarch_long_bit (gdbarch
, 64);
2301 set_gdbarch_long_long_bit (gdbarch
, 64);
2302 set_gdbarch_ptr_bit (gdbarch
, 64);
2304 /* In contrast to the i386, on AMD64 a `long double' actually takes
2305 up 128 bits, even though it's still based on the i387 extended
2306 floating-point format which has only 80 significant bits. */
2307 set_gdbarch_long_double_bit (gdbarch
, 128);
2309 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
2311 /* Register numbers of various important registers. */
2312 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
2313 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
2314 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
2315 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
2317 /* The "default" register numbering scheme for AMD64 is referred to
2318 as the "DWARF Register Number Mapping" in the System V psABI.
2319 The preferred debugging format for all known AMD64 targets is
2320 actually DWARF2, and GCC doesn't seem to support DWARF (that is
2321 DWARF-1), but we provide the same mapping just in case. This
2322 mapping is also used for stabs, which GCC does support. */
2323 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
2324 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
2326 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
2327 be in use on any of the supported AMD64 targets. */
2329 /* Call dummy code. */
2330 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
2331 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
2332 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
2333 tdep
->call_dummy_num_integer_regs
=
2334 ARRAY_SIZE (amd64_dummy_call_integer_regs
);
2335 tdep
->call_dummy_integer_regs
= amd64_dummy_call_integer_regs
;
2336 tdep
->classify
= amd64_classify
;
2338 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
2339 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
2340 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
2342 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
2344 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
2346 tdep
->record_regmap
= amd64_record_regmap
;
2348 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
2350 /* Hook the function epilogue frame unwinder. This unwinder is
2351 appended to the list first, so that it supercedes the other
2352 unwinders in function epilogues. */
2353 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
2355 /* Hook the prologue-based frame unwinders. */
2356 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
2357 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
2358 frame_base_set_default (gdbarch
, &amd64_frame_base
);
2360 /* If we have a register mapping, enable the generic core file support. */
2361 if (tdep
->gregset_reg_offset
)
2362 set_gdbarch_regset_from_core_section (gdbarch
,
2363 amd64_regset_from_core_section
);
2365 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
2368 /* Provide a prototype to silence -Wmissing-prototypes. */
2369 void _initialize_amd64_tdep (void);
2372 _initialize_amd64_tdep (void)
2374 initialize_tdesc_amd64 ();
2375 initialize_tdesc_amd64_avx ();
2379 /* The 64-bit FXSAVE format differs from the 32-bit format in the
2380 sense that the instruction pointer and data pointer are simply
2381 64-bit offsets into the code segment and the data segment instead
2382 of a selector offset pair. The functions below store the upper 32
2383 bits of these pointers (instead of just the 16-bits of the segment
2386 /* Fill register REGNUM in REGCACHE with the appropriate
2387 floating-point or SSE register value from *FXSAVE. If REGNUM is
2388 -1, do this for all registers. This function masks off any of the
2389 reserved bits in *FXSAVE. */
2392 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
2395 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2396 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2398 i387_supply_fxsave (regcache
, regnum
, fxsave
);
2400 if (fxsave
&& gdbarch_ptr_bit (gdbarch
) == 64)
2402 const gdb_byte
*regs
= fxsave
;
2404 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
2405 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
2406 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
2407 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
2411 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
2414 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
2417 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2418 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2420 i387_supply_xsave (regcache
, regnum
, xsave
);
2422 if (xsave
&& gdbarch_ptr_bit (gdbarch
) == 64)
2424 const gdb_byte
*regs
= xsave
;
2426 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
2427 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
),
2429 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
2430 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
),
2435 /* Fill register REGNUM (if it is a floating-point or SSE register) in
2436 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
2437 all registers. This function doesn't touch any of the reserved
2441 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
2444 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2445 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2446 gdb_byte
*regs
= fxsave
;
2448 i387_collect_fxsave (regcache
, regnum
, fxsave
);
2450 if (gdbarch_ptr_bit (gdbarch
) == 64)
2452 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
2453 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
2454 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
2455 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
2459 /* Similar to amd64_collect_fxsave, but but use XSAVE extended state. */
2462 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
2463 void *xsave
, int gcore
)
2465 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2466 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2467 gdb_byte
*regs
= xsave
;
2469 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
2471 if (gdbarch_ptr_bit (gdbarch
) == 64)
2473 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
2474 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
),
2476 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
2477 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
),