1 /* Target-dependent code for AMD64.
3 Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Jiri Smid, SuSE Labs.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "gdb_assert.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
43 /* Note that the AMD64 architecture was previously known as x86-64.
44 The latter is (forever) engraved into the canonical system name as
45 returned by config.guess, and used as the name for the AMD64 port
46 of GNU/Linux. The BSD's have renamed their ports to amd64; they
47 don't like to shout. For GDB we prefer the amd64_-prefix over the
48 x86_64_-prefix since it's so much easier to type. */
50 /* Register information. */
52 struct amd64_register_info
58 static struct amd64_register_info amd64_register_info
[] =
60 { "rax", &builtin_type_int64
},
61 { "rbx", &builtin_type_int64
},
62 { "rcx", &builtin_type_int64
},
63 { "rdx", &builtin_type_int64
},
64 { "rsi", &builtin_type_int64
},
65 { "rdi", &builtin_type_int64
},
66 { "rbp", &builtin_type_void_data_ptr
},
67 { "rsp", &builtin_type_void_data_ptr
},
69 /* %r8 is indeed register number 8. */
70 { "r8", &builtin_type_int64
},
71 { "r9", &builtin_type_int64
},
72 { "r10", &builtin_type_int64
},
73 { "r11", &builtin_type_int64
},
74 { "r12", &builtin_type_int64
},
75 { "r13", &builtin_type_int64
},
76 { "r14", &builtin_type_int64
},
77 { "r15", &builtin_type_int64
},
78 { "rip", &builtin_type_void_func_ptr
},
79 { "eflags", &builtin_type_int32
},
80 { "cs", &builtin_type_int32
},
81 { "ss", &builtin_type_int32
},
82 { "ds", &builtin_type_int32
},
83 { "es", &builtin_type_int32
},
84 { "fs", &builtin_type_int32
},
85 { "gs", &builtin_type_int32
},
87 /* %st0 is register number 24. */
88 { "st0", &builtin_type_i387_ext
},
89 { "st1", &builtin_type_i387_ext
},
90 { "st2", &builtin_type_i387_ext
},
91 { "st3", &builtin_type_i387_ext
},
92 { "st4", &builtin_type_i387_ext
},
93 { "st5", &builtin_type_i387_ext
},
94 { "st6", &builtin_type_i387_ext
},
95 { "st7", &builtin_type_i387_ext
},
96 { "fctrl", &builtin_type_int32
},
97 { "fstat", &builtin_type_int32
},
98 { "ftag", &builtin_type_int32
},
99 { "fiseg", &builtin_type_int32
},
100 { "fioff", &builtin_type_int32
},
101 { "foseg", &builtin_type_int32
},
102 { "fooff", &builtin_type_int32
},
103 { "fop", &builtin_type_int32
},
105 /* %xmm0 is register number 40. */
106 { "xmm0", &builtin_type_v4sf
},
107 { "xmm1", &builtin_type_v4sf
},
108 { "xmm2", &builtin_type_v4sf
},
109 { "xmm3", &builtin_type_v4sf
},
110 { "xmm4", &builtin_type_v4sf
},
111 { "xmm5", &builtin_type_v4sf
},
112 { "xmm6", &builtin_type_v4sf
},
113 { "xmm7", &builtin_type_v4sf
},
114 { "xmm8", &builtin_type_v4sf
},
115 { "xmm9", &builtin_type_v4sf
},
116 { "xmm10", &builtin_type_v4sf
},
117 { "xmm11", &builtin_type_v4sf
},
118 { "xmm12", &builtin_type_v4sf
},
119 { "xmm13", &builtin_type_v4sf
},
120 { "xmm14", &builtin_type_v4sf
},
121 { "xmm15", &builtin_type_v4sf
},
122 { "mxcsr", &builtin_type_int32
}
125 /* Total number of registers. */
126 #define AMD64_NUM_REGS \
127 (sizeof (amd64_register_info) / sizeof (amd64_register_info[0]))
129 /* Return the name of register REGNUM. */
132 amd64_register_name (int regnum
)
134 if (regnum
>= 0 && regnum
< AMD64_NUM_REGS
)
135 return amd64_register_info
[regnum
].name
;
140 /* Return the GDB type object for the "standard" data type of data in
144 amd64_register_type (struct gdbarch
*gdbarch
, int regnum
)
146 gdb_assert (regnum
>= 0 && regnum
< AMD64_NUM_REGS
);
148 return *amd64_register_info
[regnum
].type
;
151 /* DWARF Register Number Mapping as defined in the System V psABI,
154 static int amd64_dwarf_regmap
[] =
156 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
157 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
158 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
159 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
161 /* Frame Pointer Register RBP. */
164 /* Stack Pointer Register RSP. */
167 /* Extended Integer Registers 8 - 15. */
168 8, 9, 10, 11, 12, 13, 14, 15,
170 /* Return Address RA. Mapped to RIP. */
173 /* SSE Registers 0 - 7. */
174 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
175 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
176 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
177 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
179 /* Extended SSE Registers 8 - 15. */
180 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
181 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
182 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
183 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
185 /* Floating Point Registers 0-7. */
186 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
187 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
188 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
189 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7
192 static const int amd64_dwarf_regmap_len
=
193 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
195 /* Convert DWARF register number REG to the appropriate register
196 number used by GDB. */
199 amd64_dwarf_reg_to_regnum (int reg
)
203 if (reg
>= 0 || reg
< amd64_dwarf_regmap_len
)
204 regnum
= amd64_dwarf_regmap
[reg
];
207 warning ("Unmapped DWARF Register #%d encountered\n", reg
);
212 /* Return nonzero if a value of type TYPE stored in register REGNUM
213 needs any special handling. */
216 amd64_convert_register_p (int regnum
, struct type
*type
)
218 return i386_fp_regnum_p (regnum
);
222 /* Register classes as defined in the psABI. */
236 /* Return the union class of CLASS1 and CLASS2. See the psABI for
239 static enum amd64_reg_class
240 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
242 /* Rule (a): If both classes are equal, this is the resulting class. */
243 if (class1
== class2
)
246 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
247 is the other class. */
248 if (class1
== AMD64_NO_CLASS
)
250 if (class2
== AMD64_NO_CLASS
)
253 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
254 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
257 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
258 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
259 return AMD64_INTEGER
;
261 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
262 MEMORY is used as class. */
263 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
264 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
265 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
268 /* Rule (f): Otherwise class SSE is used. */
272 static void amd64_classify (struct type
*type
, enum amd64_reg_class
class[2]);
274 /* Return non-zero if TYPE is a non-POD structure or union type. */
277 amd64_non_pod_p (struct type
*type
)
279 /* ??? A class with a base class certainly isn't POD, but does this
280 catch all non-POD structure types? */
281 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
287 /* Classify TYPE according to the rules for aggregate (structures and
288 arrays) and union types, and store the result in CLASS. */
291 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class
class[2])
293 int len
= TYPE_LENGTH (type
);
295 /* 1. If the size of an object is larger than two eightbytes, or in
296 C++, is a non-POD structure or union type, or contains
297 unaligned fields, it has class memory. */
298 if (len
> 16 || amd64_non_pod_p (type
))
300 class[0] = class[1] = AMD64_MEMORY
;
304 /* 2. Both eightbytes get initialized to class NO_CLASS. */
305 class[0] = class[1] = AMD64_NO_CLASS
;
307 /* 3. Each field of an object is classified recursively so that
308 always two fields are considered. The resulting class is
309 calculated according to the classes of the fields in the
312 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
314 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
316 /* All fields in an array have the same type. */
317 amd64_classify (subtype
, class);
318 if (len
> 8 && class[1] == AMD64_NO_CLASS
)
325 /* Structure or union. */
326 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
327 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
329 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
331 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
332 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
333 enum amd64_reg_class subclass
[2];
335 /* Ignore static fields. */
336 if (TYPE_FIELD_STATIC (type
, i
))
339 gdb_assert (pos
== 0 || pos
== 1);
341 amd64_classify (subtype
, subclass
);
342 class[pos
] = amd64_merge_classes (class[pos
], subclass
[0]);
344 class[1] = amd64_merge_classes (class[1], subclass
[1]);
348 /* 4. Then a post merger cleanup is done: */
350 /* Rule (a): If one of the classes is MEMORY, the whole argument is
352 if (class[0] == AMD64_MEMORY
|| class[1] == AMD64_MEMORY
)
353 class[0] = class[1] = AMD64_MEMORY
;
355 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
357 if (class[0] == AMD64_SSEUP
)
358 class[0] = AMD64_SSE
;
359 if (class[1] == AMD64_SSEUP
&& class[0] != AMD64_SSE
)
360 class[1] = AMD64_SSE
;
363 /* Classify TYPE, and store the result in CLASS. */
366 amd64_classify (struct type
*type
, enum amd64_reg_class
class[2])
368 enum type_code code
= TYPE_CODE (type
);
369 int len
= TYPE_LENGTH (type
);
371 class[0] = class[1] = AMD64_NO_CLASS
;
373 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
374 long, long long, and pointers are in the INTEGER class. Similarly,
375 range types, used by languages such as Ada, are also in the INTEGER
377 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
378 || code
== TYPE_CODE_RANGE
379 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
380 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
381 class[0] = AMD64_INTEGER
;
383 /* Arguments of types float, double and __m64 are in class SSE. */
384 else if (code
== TYPE_CODE_FLT
&& (len
== 4 || len
== 8))
386 class[0] = AMD64_SSE
;
388 /* Arguments of types __float128 and __m128 are split into two
389 halves. The least significant ones belong to class SSE, the most
390 significant one to class SSEUP. */
391 /* FIXME: __float128, __m128. */
393 /* The 64-bit mantissa of arguments of type long double belongs to
394 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
396 else if (code
== TYPE_CODE_FLT
&& len
== 16)
397 /* Class X87 and X87UP. */
398 class[0] = AMD64_X87
, class[1] = AMD64_X87UP
;
401 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
402 || code
== TYPE_CODE_UNION
)
403 amd64_classify_aggregate (type
, class);
406 static enum return_value_convention
407 amd64_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
408 struct regcache
*regcache
,
409 void *readbuf
, const void *writebuf
)
411 enum amd64_reg_class
class[2];
412 int len
= TYPE_LENGTH (type
);
413 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
414 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
419 gdb_assert (!(readbuf
&& writebuf
));
421 /* 1. Classify the return type with the classification algorithm. */
422 amd64_classify (type
, class);
424 /* 2. If the type has class MEMORY, then the caller provides space
425 for the return value and passes the address of this storage in
426 %rdi as if it were the first argument to the function. In
427 effect, this address becomes a hidden first argument. */
428 if (class[0] == AMD64_MEMORY
)
429 return RETURN_VALUE_STRUCT_CONVENTION
;
431 gdb_assert (class[1] != AMD64_MEMORY
);
432 gdb_assert (len
<= 16);
434 for (i
= 0; len
> 0; i
++, len
-= 8)
442 /* 3. If the class is INTEGER, the next available register
443 of the sequence %rax, %rdx is used. */
444 regnum
= integer_regnum
[integer_reg
++];
448 /* 4. If the class is SSE, the next available SSE register
449 of the sequence %xmm0, %xmm1 is used. */
450 regnum
= sse_regnum
[sse_reg
++];
454 /* 5. If the class is SSEUP, the eightbyte is passed in the
455 upper half of the last used SSE register. */
456 gdb_assert (sse_reg
> 0);
457 regnum
= sse_regnum
[sse_reg
- 1];
462 /* 6. If the class is X87, the value is returned on the X87
463 stack in %st0 as 80-bit x87 number. */
464 regnum
= AMD64_ST0_REGNUM
;
466 i387_return_value (gdbarch
, regcache
);
470 /* 7. If the class is X87UP, the value is returned together
471 with the previous X87 value in %st0. */
472 gdb_assert (i
> 0 && class[0] == AMD64_X87
);
473 regnum
= AMD64_ST0_REGNUM
;
482 gdb_assert (!"Unexpected register class.");
485 gdb_assert (regnum
!= -1);
488 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
489 (char *) readbuf
+ i
* 8);
491 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
492 (const char *) writebuf
+ i
* 8);
495 return RETURN_VALUE_REGISTER_CONVENTION
;
500 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
501 struct value
**args
, CORE_ADDR sp
, int struct_return
)
503 static int integer_regnum
[] =
505 AMD64_RDI_REGNUM
, /* %rdi */
506 AMD64_RSI_REGNUM
, /* %rsi */
507 AMD64_RDX_REGNUM
, /* %rdx */
508 AMD64_RCX_REGNUM
, /* %rcx */
512 static int sse_regnum
[] =
514 /* %xmm0 ... %xmm7 */
515 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
516 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
517 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
518 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
520 struct value
**stack_args
= alloca (nargs
* sizeof (struct value
*));
521 int num_stack_args
= 0;
522 int num_elements
= 0;
528 /* Reserve a register for the "hidden" argument. */
532 for (i
= 0; i
< nargs
; i
++)
534 struct type
*type
= VALUE_TYPE (args
[i
]);
535 int len
= TYPE_LENGTH (type
);
536 enum amd64_reg_class
class[2];
537 int needed_integer_regs
= 0;
538 int needed_sse_regs
= 0;
541 /* Classify argument. */
542 amd64_classify (type
, class);
544 /* Calculate the number of integer and SSE registers needed for
546 for (j
= 0; j
< 2; j
++)
548 if (class[j
] == AMD64_INTEGER
)
549 needed_integer_regs
++;
550 else if (class[j
] == AMD64_SSE
)
554 /* Check whether enough registers are available, and if the
555 argument should be passed in registers at all. */
556 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
557 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
558 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
560 /* The argument will be passed on the stack. */
561 num_elements
+= ((len
+ 7) / 8);
562 stack_args
[num_stack_args
++] = args
[i
];
566 /* The argument will be passed in registers. */
567 char *valbuf
= VALUE_CONTENTS (args
[i
]);
570 gdb_assert (len
<= 16);
572 for (j
= 0; len
> 0; j
++, len
-= 8)
580 regnum
= integer_regnum
[integer_reg
++];
584 regnum
= sse_regnum
[sse_reg
++];
588 gdb_assert (sse_reg
> 0);
589 regnum
= sse_regnum
[sse_reg
- 1];
594 gdb_assert (!"Unexpected register class.");
597 gdb_assert (regnum
!= -1);
598 memset (buf
, 0, sizeof buf
);
599 memcpy (buf
, valbuf
+ j
* 8, min (len
, 8));
600 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
605 /* Allocate space for the arguments on the stack. */
606 sp
-= num_elements
* 8;
608 /* The psABI says that "The end of the input argument area shall be
609 aligned on a 16 byte boundary." */
612 /* Write out the arguments to the stack. */
613 for (i
= 0; i
< num_stack_args
; i
++)
615 struct type
*type
= VALUE_TYPE (stack_args
[i
]);
616 char *valbuf
= VALUE_CONTENTS (stack_args
[i
]);
617 int len
= TYPE_LENGTH (type
);
619 write_memory (sp
+ element
* 8, valbuf
, len
);
620 element
+= ((len
+ 7) / 8);
623 /* The psABI says that "For calls that may call functions that use
624 varargs or stdargs (prototype-less calls or calls to functions
625 containing ellipsis (...) in the declaration) %al is used as
626 hidden argument to specify the number of SSE registers used. */
627 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
632 amd64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
633 struct regcache
*regcache
, CORE_ADDR bp_addr
,
634 int nargs
, struct value
**args
, CORE_ADDR sp
,
635 int struct_return
, CORE_ADDR struct_addr
)
639 /* Pass arguments. */
640 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, struct_return
);
642 /* Pass "hidden" argument". */
645 store_unsigned_integer (buf
, 8, struct_addr
);
646 regcache_cooked_write (regcache
, AMD64_RDI_REGNUM
, buf
);
649 /* Store return address. */
651 store_unsigned_integer (buf
, 8, bp_addr
);
652 write_memory (sp
, buf
, 8);
654 /* Finally, update the stack pointer... */
655 store_unsigned_integer (buf
, 8, sp
);
656 regcache_cooked_write (regcache
, AMD64_RSP_REGNUM
, buf
);
658 /* ...and fake a frame pointer. */
659 regcache_cooked_write (regcache
, AMD64_RBP_REGNUM
, buf
);
665 /* The maximum number of saved registers. This should include %rip. */
666 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
668 struct amd64_frame_cache
675 /* Saved registers. */
676 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
679 /* Do we have a frame? */
683 /* Allocate and initialize a frame cache. */
685 static struct amd64_frame_cache
*
686 amd64_alloc_frame_cache (void)
688 struct amd64_frame_cache
*cache
;
691 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
695 cache
->sp_offset
= -8;
698 /* Saved registers. We initialize these to -1 since zero is a valid
699 offset (that's where %rbp is supposed to be stored). */
700 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
701 cache
->saved_regs
[i
] = -1;
704 /* Frameless until proven otherwise. */
705 cache
->frameless_p
= 1;
710 /* Do a limited analysis of the prologue at PC and update CACHE
711 accordingly. Bail out early if CURRENT_PC is reached. Return the
712 address where the analysis stopped.
714 We will handle only functions beginning with:
717 movq %rsp, %rbp 0x48 0x89 0xe5
719 Any function that doesn't start with this sequence will be assumed
720 to have no prologue and thus no valid frame pointer in %rbp. */
723 amd64_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
724 struct amd64_frame_cache
*cache
)
726 static unsigned char proto
[3] = { 0x48, 0x89, 0xe5 };
727 unsigned char buf
[3];
730 if (current_pc
<= pc
)
733 op
= read_memory_unsigned_integer (pc
, 1);
735 if (op
== 0x55) /* pushq %rbp */
737 /* Take into account that we've executed the `pushq %rbp' that
738 starts this instruction sequence. */
739 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
740 cache
->sp_offset
+= 8;
742 /* If that's all, return now. */
743 if (current_pc
<= pc
+ 1)
746 /* Check for `movq %rsp, %rbp'. */
747 read_memory (pc
+ 1, buf
, 3);
748 if (memcmp (buf
, proto
, 3) != 0)
751 /* OK, we actually have a frame. */
752 cache
->frameless_p
= 0;
759 /* Return PC of first real instruction. */
762 amd64_skip_prologue (CORE_ADDR start_pc
)
764 struct amd64_frame_cache cache
;
767 pc
= amd64_analyze_prologue (start_pc
, 0xffffffffffffffff, &cache
);
768 if (cache
.frameless_p
)
777 static struct amd64_frame_cache
*
778 amd64_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
780 struct amd64_frame_cache
*cache
;
787 cache
= amd64_alloc_frame_cache ();
790 cache
->pc
= frame_func_unwind (next_frame
);
792 amd64_analyze_prologue (cache
->pc
, frame_pc_unwind (next_frame
), cache
);
794 if (cache
->frameless_p
)
796 /* We didn't find a valid frame. If we're at the start of a
797 function, or somewhere half-way its prologue, the function's
798 frame probably hasn't been fully setup yet. Try to
799 reconstruct the base address for the stack frame by looking
800 at the stack pointer. For truly "frameless" functions this
803 frame_unwind_register (next_frame
, AMD64_RSP_REGNUM
, buf
);
804 cache
->base
= extract_unsigned_integer (buf
, 8) + cache
->sp_offset
;
808 frame_unwind_register (next_frame
, AMD64_RBP_REGNUM
, buf
);
809 cache
->base
= extract_unsigned_integer (buf
, 8);
812 /* Now that we have the base address for the stack frame we can
813 calculate the value of %rsp in the calling frame. */
814 cache
->saved_sp
= cache
->base
+ 16;
816 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
817 frame we find it at the same offset from the reconstructed base
819 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
821 /* Adjust all the saved registers such that they contain addresses
822 instead of offsets. */
823 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
824 if (cache
->saved_regs
[i
] != -1)
825 cache
->saved_regs
[i
] += cache
->base
;
831 amd64_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
832 struct frame_id
*this_id
)
834 struct amd64_frame_cache
*cache
=
835 amd64_frame_cache (next_frame
, this_cache
);
837 /* This marks the outermost frame. */
838 if (cache
->base
== 0)
841 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
845 amd64_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
846 int regnum
, int *optimizedp
,
847 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
848 int *realnump
, void *valuep
)
850 struct amd64_frame_cache
*cache
=
851 amd64_frame_cache (next_frame
, this_cache
);
853 gdb_assert (regnum
>= 0);
855 if (regnum
== SP_REGNUM
&& cache
->saved_sp
)
863 /* Store the value. */
864 store_unsigned_integer (valuep
, 8, cache
->saved_sp
);
869 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
872 *lvalp
= lval_memory
;
873 *addrp
= cache
->saved_regs
[regnum
];
877 /* Read the value in from memory. */
878 read_memory (*addrp
, valuep
,
879 register_size (current_gdbarch
, regnum
));
884 frame_register_unwind (next_frame
, regnum
,
885 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
888 static const struct frame_unwind amd64_frame_unwind
=
892 amd64_frame_prev_register
895 static const struct frame_unwind
*
896 amd64_frame_sniffer (struct frame_info
*next_frame
)
898 return &amd64_frame_unwind
;
902 /* Signal trampolines. */
904 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
905 64-bit variants. This would require using identical frame caches
906 on both platforms. */
908 static struct amd64_frame_cache
*
909 amd64_sigtramp_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
911 struct amd64_frame_cache
*cache
;
912 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
920 cache
= amd64_alloc_frame_cache ();
922 frame_unwind_register (next_frame
, AMD64_RSP_REGNUM
, buf
);
923 cache
->base
= extract_unsigned_integer (buf
, 8) - 8;
925 addr
= tdep
->sigcontext_addr (next_frame
);
926 gdb_assert (tdep
->sc_reg_offset
);
927 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
928 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
929 if (tdep
->sc_reg_offset
[i
] != -1)
930 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
937 amd64_sigtramp_frame_this_id (struct frame_info
*next_frame
,
938 void **this_cache
, struct frame_id
*this_id
)
940 struct amd64_frame_cache
*cache
=
941 amd64_sigtramp_frame_cache (next_frame
, this_cache
);
943 (*this_id
) = frame_id_build (cache
->base
+ 16, frame_pc_unwind (next_frame
));
947 amd64_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
949 int regnum
, int *optimizedp
,
950 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
951 int *realnump
, void *valuep
)
953 /* Make sure we've initialized the cache. */
954 amd64_sigtramp_frame_cache (next_frame
, this_cache
);
956 amd64_frame_prev_register (next_frame
, this_cache
, regnum
,
957 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
960 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
963 amd64_sigtramp_frame_this_id
,
964 amd64_sigtramp_frame_prev_register
967 static const struct frame_unwind
*
968 amd64_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
970 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (next_frame
));
972 /* We shouldn't even bother if we don't have a sigcontext_addr
974 if (tdep
->sigcontext_addr
== NULL
)
977 if (tdep
->sigtramp_p
!= NULL
)
979 if (tdep
->sigtramp_p (next_frame
))
980 return &amd64_sigtramp_frame_unwind
;
983 if (tdep
->sigtramp_start
!= 0)
985 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
987 gdb_assert (tdep
->sigtramp_end
!= 0);
988 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
989 return &amd64_sigtramp_frame_unwind
;
997 amd64_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
999 struct amd64_frame_cache
*cache
=
1000 amd64_frame_cache (next_frame
, this_cache
);
1005 static const struct frame_base amd64_frame_base
=
1007 &amd64_frame_unwind
,
1008 amd64_frame_base_address
,
1009 amd64_frame_base_address
,
1010 amd64_frame_base_address
1013 static struct frame_id
1014 amd64_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1019 frame_unwind_register (next_frame
, AMD64_RBP_REGNUM
, buf
);
1020 fp
= extract_unsigned_integer (buf
, 8);
1022 return frame_id_build (fp
+ 16, frame_pc_unwind (next_frame
));
1025 /* 16 byte align the SP per frame requirements. */
1028 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1030 return sp
& -(CORE_ADDR
)16;
1034 /* Supply register REGNUM from the floating-point register set REGSET
1035 to register cache REGCACHE. If REGNUM is -1, do this for all
1036 registers in REGSET. */
1039 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
1040 int regnum
, const void *fpregs
, size_t len
)
1042 const struct gdbarch_tdep
*tdep
= regset
->descr
;
1044 gdb_assert (len
== tdep
->sizeof_fpregset
);
1045 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
1048 /* Return the appropriate register set for the core section identified
1049 by SECT_NAME and SECT_SIZE. */
1051 static const struct regset
*
1052 amd64_regset_from_core_section (struct gdbarch
*gdbarch
,
1053 const char *sect_name
, size_t sect_size
)
1055 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1057 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
1059 if (tdep
->fpregset
== NULL
)
1061 tdep
->fpregset
= XMALLOC (struct regset
);
1062 tdep
->fpregset
->descr
= tdep
;
1063 tdep
->fpregset
->supply_regset
= amd64_supply_fpregset
;
1066 return tdep
->fpregset
;
1069 return i386_regset_from_core_section (gdbarch
, sect_name
, sect_size
);
1074 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
1076 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1078 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
1079 floating-point registers. */
1080 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
1082 /* AMD64 has an FPU and 16 SSE registers. */
1083 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
1084 tdep
->num_xmm_regs
= 16;
1086 /* This is what all the fuss is about. */
1087 set_gdbarch_long_bit (gdbarch
, 64);
1088 set_gdbarch_long_long_bit (gdbarch
, 64);
1089 set_gdbarch_ptr_bit (gdbarch
, 64);
1091 /* In contrast to the i386, on AMD64 a `long double' actually takes
1092 up 128 bits, even though it's still based on the i387 extended
1093 floating-point format which has only 80 significant bits. */
1094 set_gdbarch_long_double_bit (gdbarch
, 128);
1096 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
1097 set_gdbarch_register_name (gdbarch
, amd64_register_name
);
1098 set_gdbarch_register_type (gdbarch
, amd64_register_type
);
1100 /* Register numbers of various important registers. */
1101 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
1102 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
1103 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
1104 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
1106 /* The "default" register numbering scheme for AMD64 is referred to
1107 as the "DWARF Register Number Mapping" in the System V psABI.
1108 The preferred debugging format for all known AMD64 targets is
1109 actually DWARF2, and GCC doesn't seem to support DWARF (that is
1110 DWARF-1), but we provide the same mapping just in case. This
1111 mapping is also used for stabs, which GCC does support. */
1112 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
1113 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
1114 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
1116 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1117 be in use on any of the supported AMD64 targets. */
1119 /* Call dummy code. */
1120 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
1121 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
1122 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
1124 set_gdbarch_convert_register_p (gdbarch
, amd64_convert_register_p
);
1125 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
1126 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
1128 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
1130 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
1132 /* Avoid wiring in the MMX registers for now. */
1133 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
1134 tdep
->mm0_regnum
= -1;
1136 set_gdbarch_unwind_dummy_id (gdbarch
, amd64_unwind_dummy_id
);
1138 /* FIXME: kettenis/20021026: This is ELF-specific. Fine for now,
1139 since all supported AMD64 targets are ELF, but that might change
1141 set_gdbarch_in_solib_call_trampoline (gdbarch
, in_plt_section
);
1143 frame_unwind_append_sniffer (gdbarch
, amd64_sigtramp_frame_sniffer
);
1144 frame_unwind_append_sniffer (gdbarch
, amd64_frame_sniffer
);
1145 frame_base_set_default (gdbarch
, &amd64_frame_base
);
1147 /* If we have a register mapping, enable the generic core file support. */
1148 if (tdep
->gregset_reg_offset
)
1149 set_gdbarch_regset_from_core_section (gdbarch
,
1150 amd64_regset_from_core_section
);
1154 #define I387_ST0_REGNUM AMD64_ST0_REGNUM
1156 /* The 64-bit FXSAVE format differs from the 32-bit format in the
1157 sense that the instruction pointer and data pointer are simply
1158 64-bit offsets into the code segment and the data segment instead
1159 of a selector offset pair. The functions below store the upper 32
1160 bits of these pointers (instead of just the 16-bits of the segment
1163 /* Fill register REGNUM in REGCACHE with the appropriate
1164 floating-point or SSE register value from *FXSAVE. If REGNUM is
1165 -1, do this for all registers. This function masks off any of the
1166 reserved bits in *FXSAVE. */
1169 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
1172 i387_supply_fxsave (regcache
, regnum
, fxsave
);
1174 if (fxsave
&& gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1176 const char *regs
= fxsave
;
1178 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM
)
1179 regcache_raw_supply (regcache
, I387_FISEG_REGNUM
, regs
+ 12);
1180 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM
)
1181 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM
, regs
+ 20);
1185 /* Fill register REGNUM (if it is a floating-point or SSE register) in
1186 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
1187 all registers. This function doesn't touch any of the reserved
1191 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
1194 char *regs
= fxsave
;
1196 i387_collect_fxsave (regcache
, regnum
, fxsave
);
1198 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1200 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM
)
1201 regcache_raw_collect (regcache
, I387_FISEG_REGNUM
, regs
+ 12);
1202 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM
)
1203 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM
, regs
+ 20);