1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2020 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "gdbsupport/x86-xstate.h"
44 #include "target-descriptions.h"
45 #include "arch/amd64.h"
49 #include "gdbsupport/byte-vector.h"
52 #include "amd64-ravenscar-thread.h"
54 /* Note that the AMD64 architecture was previously known as x86-64.
55 The latter is (forever) engraved into the canonical system name as
56 returned by config.guess, and used as the name for the AMD64 port
57 of GNU/Linux. The BSD's have renamed their ports to amd64; they
58 don't like to shout. For GDB we prefer the amd64_-prefix over the
59 x86_64_-prefix since it's so much easier to type. */
61 /* Register information. */
63 static const char * const amd64_register_names
[] =
65 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
67 /* %r8 is indeed register number 8. */
68 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
69 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
71 /* %st0 is register number 24. */
72 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
75 /* %xmm0 is register number 40. */
76 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
77 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
81 static const char * const amd64_ymm_names
[] =
83 "ymm0", "ymm1", "ymm2", "ymm3",
84 "ymm4", "ymm5", "ymm6", "ymm7",
85 "ymm8", "ymm9", "ymm10", "ymm11",
86 "ymm12", "ymm13", "ymm14", "ymm15"
89 static const char * const amd64_ymm_avx512_names
[] =
91 "ymm16", "ymm17", "ymm18", "ymm19",
92 "ymm20", "ymm21", "ymm22", "ymm23",
93 "ymm24", "ymm25", "ymm26", "ymm27",
94 "ymm28", "ymm29", "ymm30", "ymm31"
97 static const char * const amd64_ymmh_names
[] =
99 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
100 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
101 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
102 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
105 static const char * const amd64_ymmh_avx512_names
[] =
107 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
108 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
109 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
110 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
113 static const char * const amd64_mpx_names
[] =
115 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
118 static const char * const amd64_k_names
[] =
120 "k0", "k1", "k2", "k3",
121 "k4", "k5", "k6", "k7"
124 static const char * const amd64_zmmh_names
[] =
126 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
127 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
128 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
129 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
130 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
131 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
132 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
133 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
136 static const char * const amd64_zmm_names
[] =
138 "zmm0", "zmm1", "zmm2", "zmm3",
139 "zmm4", "zmm5", "zmm6", "zmm7",
140 "zmm8", "zmm9", "zmm10", "zmm11",
141 "zmm12", "zmm13", "zmm14", "zmm15",
142 "zmm16", "zmm17", "zmm18", "zmm19",
143 "zmm20", "zmm21", "zmm22", "zmm23",
144 "zmm24", "zmm25", "zmm26", "zmm27",
145 "zmm28", "zmm29", "zmm30", "zmm31"
148 static const char * const amd64_xmm_avx512_names
[] = {
149 "xmm16", "xmm17", "xmm18", "xmm19",
150 "xmm20", "xmm21", "xmm22", "xmm23",
151 "xmm24", "xmm25", "xmm26", "xmm27",
152 "xmm28", "xmm29", "xmm30", "xmm31"
155 static const char * const amd64_pkeys_names
[] = {
159 /* DWARF Register Number Mapping as defined in the System V psABI,
162 static int amd64_dwarf_regmap
[] =
164 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
165 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
166 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
167 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
169 /* Frame Pointer Register RBP. */
172 /* Stack Pointer Register RSP. */
175 /* Extended Integer Registers 8 - 15. */
176 AMD64_R8_REGNUM
, /* %r8 */
177 AMD64_R9_REGNUM
, /* %r9 */
178 AMD64_R10_REGNUM
, /* %r10 */
179 AMD64_R11_REGNUM
, /* %r11 */
180 AMD64_R12_REGNUM
, /* %r12 */
181 AMD64_R13_REGNUM
, /* %r13 */
182 AMD64_R14_REGNUM
, /* %r14 */
183 AMD64_R15_REGNUM
, /* %r15 */
185 /* Return Address RA. Mapped to RIP. */
188 /* SSE Registers 0 - 7. */
189 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
190 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
191 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
192 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
194 /* Extended SSE Registers 8 - 15. */
195 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
196 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
197 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
198 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
200 /* Floating Point Registers 0-7. */
201 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
202 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
203 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
204 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
206 /* MMX Registers 0 - 7.
207 We have to handle those registers specifically, as their register
208 number within GDB depends on the target (or they may even not be
209 available at all). */
210 -1, -1, -1, -1, -1, -1, -1, -1,
212 /* Control and Status Flags Register. */
215 /* Selector Registers. */
225 /* Segment Base Address Registers. */
231 /* Special Selector Registers. */
235 /* Floating Point Control Registers. */
241 static const int amd64_dwarf_regmap_len
=
242 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
244 /* Convert DWARF register number REG to the appropriate register
245 number used by GDB. */
248 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
250 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
251 int ymm0_regnum
= tdep
->ymm0_regnum
;
254 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
255 regnum
= amd64_dwarf_regmap
[reg
];
258 && i386_xmm_regnum_p (gdbarch
, regnum
))
259 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
264 /* Map architectural register numbers to gdb register numbers. */
266 static const int amd64_arch_regmap
[16] =
268 AMD64_RAX_REGNUM
, /* %rax */
269 AMD64_RCX_REGNUM
, /* %rcx */
270 AMD64_RDX_REGNUM
, /* %rdx */
271 AMD64_RBX_REGNUM
, /* %rbx */
272 AMD64_RSP_REGNUM
, /* %rsp */
273 AMD64_RBP_REGNUM
, /* %rbp */
274 AMD64_RSI_REGNUM
, /* %rsi */
275 AMD64_RDI_REGNUM
, /* %rdi */
276 AMD64_R8_REGNUM
, /* %r8 */
277 AMD64_R9_REGNUM
, /* %r9 */
278 AMD64_R10_REGNUM
, /* %r10 */
279 AMD64_R11_REGNUM
, /* %r11 */
280 AMD64_R12_REGNUM
, /* %r12 */
281 AMD64_R13_REGNUM
, /* %r13 */
282 AMD64_R14_REGNUM
, /* %r14 */
283 AMD64_R15_REGNUM
/* %r15 */
286 static const int amd64_arch_regmap_len
=
287 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
289 /* Convert architectural register number REG to the appropriate register
290 number used by GDB. */
293 amd64_arch_reg_to_regnum (int reg
)
295 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
297 return amd64_arch_regmap
[reg
];
300 /* Register names for byte pseudo-registers. */
302 static const char * const amd64_byte_names
[] =
304 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
305 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
306 "ah", "bh", "ch", "dh"
309 /* Number of lower byte registers. */
310 #define AMD64_NUM_LOWER_BYTE_REGS 16
312 /* Register names for word pseudo-registers. */
314 static const char * const amd64_word_names
[] =
316 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
317 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
320 /* Register names for dword pseudo-registers. */
322 static const char * const amd64_dword_names
[] =
324 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
325 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
329 /* Return the name of register REGNUM. */
332 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
334 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
335 if (i386_byte_regnum_p (gdbarch
, regnum
))
336 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
337 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
338 return amd64_zmm_names
[regnum
- tdep
->zmm0_regnum
];
339 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
340 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
341 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
342 return amd64_ymm_avx512_names
[regnum
- tdep
->ymm16_regnum
];
343 else if (i386_word_regnum_p (gdbarch
, regnum
))
344 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
345 else if (i386_dword_regnum_p (gdbarch
, regnum
))
346 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
348 return i386_pseudo_register_name (gdbarch
, regnum
);
351 static struct value
*
352 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
353 readable_regcache
*regcache
,
356 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
358 value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
359 VALUE_LVAL (result_value
) = lval_register
;
360 VALUE_REGNUM (result_value
) = regnum
;
361 gdb_byte
*buf
= value_contents_raw (result_value
);
363 if (i386_byte_regnum_p (gdbarch
, regnum
))
365 int gpnum
= regnum
- tdep
->al_regnum
;
367 /* Extract (always little endian). */
368 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
370 gpnum
-= AMD64_NUM_LOWER_BYTE_REGS
;
371 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
373 /* Special handling for AH, BH, CH, DH. */
374 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
375 if (status
== REG_VALID
)
376 memcpy (buf
, raw_buf
+ 1, 1);
378 mark_value_bytes_unavailable (result_value
, 0,
379 TYPE_LENGTH (value_type (result_value
)));
383 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
384 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
385 if (status
== REG_VALID
)
386 memcpy (buf
, raw_buf
, 1);
388 mark_value_bytes_unavailable (result_value
, 0,
389 TYPE_LENGTH (value_type (result_value
)));
392 else if (i386_dword_regnum_p (gdbarch
, regnum
))
394 int gpnum
= regnum
- tdep
->eax_regnum
;
395 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
396 /* Extract (always little endian). */
397 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
398 if (status
== REG_VALID
)
399 memcpy (buf
, raw_buf
, 4);
401 mark_value_bytes_unavailable (result_value
, 0,
402 TYPE_LENGTH (value_type (result_value
)));
405 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
412 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
413 struct regcache
*regcache
,
414 int regnum
, const gdb_byte
*buf
)
416 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
418 if (i386_byte_regnum_p (gdbarch
, regnum
))
420 int gpnum
= regnum
- tdep
->al_regnum
;
422 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
424 gpnum
-= AMD64_NUM_LOWER_BYTE_REGS
;
425 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
427 /* Read ... AH, BH, CH, DH. */
428 regcache
->raw_read (gpnum
, raw_buf
);
429 /* ... Modify ... (always little endian). */
430 memcpy (raw_buf
+ 1, buf
, 1);
432 regcache
->raw_write (gpnum
, raw_buf
);
436 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
439 regcache
->raw_read (gpnum
, raw_buf
);
440 /* ... Modify ... (always little endian). */
441 memcpy (raw_buf
, buf
, 1);
443 regcache
->raw_write (gpnum
, raw_buf
);
446 else if (i386_dword_regnum_p (gdbarch
, regnum
))
448 int gpnum
= regnum
- tdep
->eax_regnum
;
449 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
452 regcache
->raw_read (gpnum
, raw_buf
);
453 /* ... Modify ... (always little endian). */
454 memcpy (raw_buf
, buf
, 4);
456 regcache
->raw_write (gpnum
, raw_buf
);
459 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
462 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
465 amd64_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
466 struct agent_expr
*ax
, int regnum
)
468 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
470 if (i386_byte_regnum_p (gdbarch
, regnum
))
472 int gpnum
= regnum
- tdep
->al_regnum
;
474 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
475 ax_reg_mask (ax
, gpnum
- AMD64_NUM_LOWER_BYTE_REGS
);
477 ax_reg_mask (ax
, gpnum
);
480 else if (i386_dword_regnum_p (gdbarch
, regnum
))
482 int gpnum
= regnum
- tdep
->eax_regnum
;
484 ax_reg_mask (ax
, gpnum
);
488 return i386_ax_pseudo_register_collect (gdbarch
, ax
, regnum
);
493 /* Register classes as defined in the psABI. */
507 /* Return the union class of CLASS1 and CLASS2. See the psABI for
510 static enum amd64_reg_class
511 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
513 /* Rule (a): If both classes are equal, this is the resulting class. */
514 if (class1
== class2
)
517 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
518 is the other class. */
519 if (class1
== AMD64_NO_CLASS
)
521 if (class2
== AMD64_NO_CLASS
)
524 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
525 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
528 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
529 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
530 return AMD64_INTEGER
;
532 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
533 MEMORY is used as class. */
534 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
535 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
536 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
539 /* Rule (f): Otherwise class SSE is used. */
543 static void amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2]);
545 /* Return true if TYPE is a structure or union with unaligned fields. */
548 amd64_has_unaligned_fields (struct type
*type
)
550 if (type
->code () == TYPE_CODE_STRUCT
551 || type
->code () == TYPE_CODE_UNION
)
553 for (int i
= 0; i
< type
->num_fields (); i
++)
555 struct type
*subtype
= check_typedef (type
->field (i
).type ());
556 int bitpos
= TYPE_FIELD_BITPOS (type
, i
);
557 int align
= type_align(subtype
);
559 /* Ignore static fields, empty fields (for example nested
560 empty structures), and bitfields (these are handled by
562 if (field_is_static (&type
->field (i
))
563 || (TYPE_FIELD_BITSIZE (type
, i
) == 0
564 && TYPE_LENGTH (subtype
) == 0)
565 || TYPE_FIELD_PACKED (type
, i
))
571 int bytepos
= bitpos
/ 8;
572 if (bytepos
% align
!= 0)
575 if (amd64_has_unaligned_fields (subtype
))
583 /* Classify field I of TYPE starting at BITOFFSET according to the rules for
584 structures and union types, and store the result in THECLASS. */
587 amd64_classify_aggregate_field (struct type
*type
, int i
,
588 enum amd64_reg_class theclass
[2],
589 unsigned int bitoffset
)
591 struct type
*subtype
= check_typedef (type
->field (i
).type ());
592 int bitpos
= bitoffset
+ TYPE_FIELD_BITPOS (type
, i
);
593 int pos
= bitpos
/ 64;
594 enum amd64_reg_class subclass
[2];
595 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
599 bitsize
= TYPE_LENGTH (subtype
) * 8;
600 endpos
= (bitpos
+ bitsize
- 1) / 64;
602 /* Ignore static fields, or empty fields, for example nested
604 if (field_is_static (&type
->field (i
)) || bitsize
== 0)
607 if (subtype
->code () == TYPE_CODE_STRUCT
608 || subtype
->code () == TYPE_CODE_UNION
)
610 /* Each field of an object is classified recursively. */
612 for (j
= 0; j
< subtype
->num_fields (); j
++)
613 amd64_classify_aggregate_field (subtype
, j
, theclass
, bitpos
);
617 gdb_assert (pos
== 0 || pos
== 1);
619 amd64_classify (subtype
, subclass
);
620 theclass
[pos
] = amd64_merge_classes (theclass
[pos
], subclass
[0]);
621 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
622 /* This is a bit of an odd case: We have a field that would
623 normally fit in one of the two eightbytes, except that
624 it is placed in a way that this field straddles them.
625 This has been seen with a structure containing an array.
627 The ABI is a bit unclear in this case, but we assume that
628 this field's class (stored in subclass[0]) must also be merged
629 into class[1]. In other words, our field has a piece stored
630 in the second eight-byte, and thus its class applies to
631 the second eight-byte as well.
633 In the case where the field length exceeds 8 bytes,
634 it should not be necessary to merge the field class
635 into class[1]. As LEN > 8, subclass[1] is necessarily
636 different from AMD64_NO_CLASS. If subclass[1] is equal
637 to subclass[0], then the normal class[1]/subclass[1]
638 merging will take care of everything. For subclass[1]
639 to be different from subclass[0], I can only see the case
640 where we have a SSE/SSEUP or X87/X87UP pair, which both
641 use up all 16 bytes of the aggregate, and are already
642 handled just fine (because each portion sits on its own
644 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[0]);
646 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[1]);
649 /* Classify TYPE according to the rules for aggregate (structures and
650 arrays) and union types, and store the result in CLASS. */
653 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class theclass
[2])
655 /* 1. If the size of an object is larger than two eightbytes, or it has
656 unaligned fields, it has class memory. */
657 if (TYPE_LENGTH (type
) > 16 || amd64_has_unaligned_fields (type
))
659 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
663 /* 2. Both eightbytes get initialized to class NO_CLASS. */
664 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
666 /* 3. Each field of an object is classified recursively so that
667 always two fields are considered. The resulting class is
668 calculated according to the classes of the fields in the
671 if (type
->code () == TYPE_CODE_ARRAY
)
673 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
675 /* All fields in an array have the same type. */
676 amd64_classify (subtype
, theclass
);
677 if (TYPE_LENGTH (type
) > 8 && theclass
[1] == AMD64_NO_CLASS
)
678 theclass
[1] = theclass
[0];
684 /* Structure or union. */
685 gdb_assert (type
->code () == TYPE_CODE_STRUCT
686 || type
->code () == TYPE_CODE_UNION
);
688 for (i
= 0; i
< type
->num_fields (); i
++)
689 amd64_classify_aggregate_field (type
, i
, theclass
, 0);
692 /* 4. Then a post merger cleanup is done: */
694 /* Rule (a): If one of the classes is MEMORY, the whole argument is
696 if (theclass
[0] == AMD64_MEMORY
|| theclass
[1] == AMD64_MEMORY
)
697 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
699 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
701 if (theclass
[0] == AMD64_SSEUP
)
702 theclass
[0] = AMD64_SSE
;
703 if (theclass
[1] == AMD64_SSEUP
&& theclass
[0] != AMD64_SSE
)
704 theclass
[1] = AMD64_SSE
;
707 /* Classify TYPE, and store the result in CLASS. */
710 amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2])
712 enum type_code code
= type
->code ();
713 int len
= TYPE_LENGTH (type
);
715 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
717 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
718 long, long long, and pointers are in the INTEGER class. Similarly,
719 range types, used by languages such as Ada, are also in the INTEGER
721 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
722 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
723 || code
== TYPE_CODE_CHAR
724 || code
== TYPE_CODE_PTR
|| TYPE_IS_REFERENCE (type
))
725 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
726 theclass
[0] = AMD64_INTEGER
;
728 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
730 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
731 && (len
== 4 || len
== 8))
733 theclass
[0] = AMD64_SSE
;
735 /* Arguments of types __float128, _Decimal128 and __m128 are split into
736 two halves. The least significant ones belong to class SSE, the most
737 significant one to class SSEUP. */
738 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
739 /* FIXME: __float128, __m128. */
740 theclass
[0] = AMD64_SSE
, theclass
[1] = AMD64_SSEUP
;
742 /* The 64-bit mantissa of arguments of type long double belongs to
743 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
745 else if (code
== TYPE_CODE_FLT
&& len
== 16)
746 /* Class X87 and X87UP. */
747 theclass
[0] = AMD64_X87
, theclass
[1] = AMD64_X87UP
;
749 /* Arguments of complex T where T is one of the types float or
750 double get treated as if they are implemented as:
758 else if (code
== TYPE_CODE_COMPLEX
&& len
== 8)
759 theclass
[0] = AMD64_SSE
;
760 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
761 theclass
[0] = theclass
[1] = AMD64_SSE
;
763 /* A variable of type complex long double is classified as type
765 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
766 theclass
[0] = AMD64_COMPLEX_X87
;
769 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
770 || code
== TYPE_CODE_UNION
)
771 amd64_classify_aggregate (type
, theclass
);
774 static enum return_value_convention
775 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
776 struct type
*type
, struct regcache
*regcache
,
777 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
779 enum amd64_reg_class theclass
[2];
780 int len
= TYPE_LENGTH (type
);
781 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
782 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
787 gdb_assert (!(readbuf
&& writebuf
));
789 /* 1. Classify the return type with the classification algorithm. */
790 amd64_classify (type
, theclass
);
792 /* 2. If the type has class MEMORY, then the caller provides space
793 for the return value and passes the address of this storage in
794 %rdi as if it were the first argument to the function. In effect,
795 this address becomes a hidden first argument.
797 On return %rax will contain the address that has been passed in
798 by the caller in %rdi. */
799 if (theclass
[0] == AMD64_MEMORY
)
801 /* As indicated by the comment above, the ABI guarantees that we
802 can always find the return value just after the function has
809 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
810 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
813 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
816 /* 8. If the class is COMPLEX_X87, the real part of the value is
817 returned in %st0 and the imaginary part in %st1. */
818 if (theclass
[0] == AMD64_COMPLEX_X87
)
822 regcache
->raw_read (AMD64_ST0_REGNUM
, readbuf
);
823 regcache
->raw_read (AMD64_ST1_REGNUM
, readbuf
+ 16);
828 i387_return_value (gdbarch
, regcache
);
829 regcache
->raw_write (AMD64_ST0_REGNUM
, writebuf
);
830 regcache
->raw_write (AMD64_ST1_REGNUM
, writebuf
+ 16);
832 /* Fix up the tag word such that both %st(0) and %st(1) are
834 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
837 return RETURN_VALUE_REGISTER_CONVENTION
;
840 gdb_assert (theclass
[1] != AMD64_MEMORY
);
841 gdb_assert (len
<= 16);
843 for (i
= 0; len
> 0; i
++, len
-= 8)
851 /* 3. If the class is INTEGER, the next available register
852 of the sequence %rax, %rdx is used. */
853 regnum
= integer_regnum
[integer_reg
++];
857 /* 4. If the class is SSE, the next available SSE register
858 of the sequence %xmm0, %xmm1 is used. */
859 regnum
= sse_regnum
[sse_reg
++];
863 /* 5. If the class is SSEUP, the eightbyte is passed in the
864 upper half of the last used SSE register. */
865 gdb_assert (sse_reg
> 0);
866 regnum
= sse_regnum
[sse_reg
- 1];
871 /* 6. If the class is X87, the value is returned on the X87
872 stack in %st0 as 80-bit x87 number. */
873 regnum
= AMD64_ST0_REGNUM
;
875 i387_return_value (gdbarch
, regcache
);
879 /* 7. If the class is X87UP, the value is returned together
880 with the previous X87 value in %st0. */
881 gdb_assert (i
> 0 && theclass
[0] == AMD64_X87
);
882 regnum
= AMD64_ST0_REGNUM
;
891 gdb_assert (!"Unexpected register class.");
894 gdb_assert (regnum
!= -1);
897 regcache
->raw_read_part (regnum
, offset
, std::min (len
, 8),
900 regcache
->raw_write_part (regnum
, offset
, std::min (len
, 8),
904 return RETURN_VALUE_REGISTER_CONVENTION
;
909 amd64_push_arguments (struct regcache
*regcache
, int nargs
, struct value
**args
,
910 CORE_ADDR sp
, function_call_return_method return_method
)
912 static int integer_regnum
[] =
914 AMD64_RDI_REGNUM
, /* %rdi */
915 AMD64_RSI_REGNUM
, /* %rsi */
916 AMD64_RDX_REGNUM
, /* %rdx */
917 AMD64_RCX_REGNUM
, /* %rcx */
918 AMD64_R8_REGNUM
, /* %r8 */
919 AMD64_R9_REGNUM
/* %r9 */
921 static int sse_regnum
[] =
923 /* %xmm0 ... %xmm7 */
924 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
925 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
926 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
927 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
929 struct value
**stack_args
= XALLOCAVEC (struct value
*, nargs
);
930 int num_stack_args
= 0;
931 int num_elements
= 0;
937 /* Reserve a register for the "hidden" argument. */
938 if (return_method
== return_method_struct
)
941 for (i
= 0; i
< nargs
; i
++)
943 struct type
*type
= value_type (args
[i
]);
944 int len
= TYPE_LENGTH (type
);
945 enum amd64_reg_class theclass
[2];
946 int needed_integer_regs
= 0;
947 int needed_sse_regs
= 0;
950 /* Classify argument. */
951 amd64_classify (type
, theclass
);
953 /* Calculate the number of integer and SSE registers needed for
955 for (j
= 0; j
< 2; j
++)
957 if (theclass
[j
] == AMD64_INTEGER
)
958 needed_integer_regs
++;
959 else if (theclass
[j
] == AMD64_SSE
)
963 /* Check whether enough registers are available, and if the
964 argument should be passed in registers at all. */
965 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
966 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
967 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
969 /* The argument will be passed on the stack. */
970 num_elements
+= ((len
+ 7) / 8);
971 stack_args
[num_stack_args
++] = args
[i
];
975 /* The argument will be passed in registers. */
976 const gdb_byte
*valbuf
= value_contents (args
[i
]);
979 gdb_assert (len
<= 16);
981 for (j
= 0; len
> 0; j
++, len
-= 8)
989 regnum
= integer_regnum
[integer_reg
++];
993 regnum
= sse_regnum
[sse_reg
++];
997 gdb_assert (sse_reg
> 0);
998 regnum
= sse_regnum
[sse_reg
- 1];
1002 case AMD64_NO_CLASS
:
1006 gdb_assert (!"Unexpected register class.");
1009 gdb_assert (regnum
!= -1);
1010 memset (buf
, 0, sizeof buf
);
1011 memcpy (buf
, valbuf
+ j
* 8, std::min (len
, 8));
1012 regcache
->raw_write_part (regnum
, offset
, 8, buf
);
1017 /* Allocate space for the arguments on the stack. */
1018 sp
-= num_elements
* 8;
1020 /* The psABI says that "The end of the input argument area shall be
1021 aligned on a 16 byte boundary." */
1024 /* Write out the arguments to the stack. */
1025 for (i
= 0; i
< num_stack_args
; i
++)
1027 struct type
*type
= value_type (stack_args
[i
]);
1028 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
1029 int len
= TYPE_LENGTH (type
);
1031 write_memory (sp
+ element
* 8, valbuf
, len
);
1032 element
+= ((len
+ 7) / 8);
1035 /* The psABI says that "For calls that may call functions that use
1036 varargs or stdargs (prototype-less calls or calls to functions
1037 containing ellipsis (...) in the declaration) %al is used as
1038 hidden argument to specify the number of SSE registers used. */
1039 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
1044 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1045 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1046 int nargs
, struct value
**args
, CORE_ADDR sp
,
1047 function_call_return_method return_method
,
1048 CORE_ADDR struct_addr
)
1050 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1053 /* BND registers can be in arbitrary values at the moment of the
1054 inferior call. This can cause boundary violations that are not
1055 due to a real bug or even desired by the user. The best to be done
1056 is set the BND registers to allow access to the whole memory, INIT
1057 state, before pushing the inferior call. */
1058 i387_reset_bnd_regs (gdbarch
, regcache
);
1060 /* Pass arguments. */
1061 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, return_method
);
1063 /* Pass "hidden" argument". */
1064 if (return_method
== return_method_struct
)
1066 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
1067 regcache
->cooked_write (AMD64_RDI_REGNUM
, buf
);
1070 /* Store return address. */
1072 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
1073 write_memory (sp
, buf
, 8);
1075 /* Finally, update the stack pointer... */
1076 store_unsigned_integer (buf
, 8, byte_order
, sp
);
1077 regcache
->cooked_write (AMD64_RSP_REGNUM
, buf
);
1079 /* ...and fake a frame pointer. */
1080 regcache
->cooked_write (AMD64_RBP_REGNUM
, buf
);
1085 /* Displaced instruction handling. */
1087 /* A partially decoded instruction.
1088 This contains enough details for displaced stepping purposes. */
1092 /* The number of opcode bytes. */
1094 /* The offset of the REX/VEX instruction encoding prefix or -1 if
1096 int enc_prefix_offset
;
1097 /* The offset to the first opcode byte. */
1099 /* The offset to the modrm byte or -1 if not present. */
1102 /* The raw instruction. */
1106 struct amd64_displaced_step_copy_insn_closure
1107 : public displaced_step_copy_insn_closure
1109 amd64_displaced_step_copy_insn_closure (int insn_buf_len
)
1110 : insn_buf (insn_buf_len
, 0)
1113 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1118 /* Details of the instruction. */
1119 struct amd64_insn insn_details
;
1121 /* The possibly modified insn. */
1122 gdb::byte_vector insn_buf
;
1125 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1126 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1127 at which point delete these in favor of libopcodes' versions). */
1129 static const unsigned char onebyte_has_modrm
[256] = {
1130 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1131 /* ------------------------------- */
1132 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1133 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1134 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1135 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1136 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1137 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1138 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1139 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1140 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1141 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1142 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1143 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1144 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1145 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1146 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1147 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1148 /* ------------------------------- */
1149 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1152 static const unsigned char twobyte_has_modrm
[256] = {
1153 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1154 /* ------------------------------- */
1155 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1156 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1157 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1158 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1159 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1160 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1161 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1162 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1163 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1164 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1165 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1166 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1167 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1168 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1169 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1170 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1171 /* ------------------------------- */
1172 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1175 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1178 rex_prefix_p (gdb_byte pfx
)
1180 return REX_PREFIX_P (pfx
);
1183 /* True if PFX is the start of the 2-byte VEX prefix. */
1186 vex2_prefix_p (gdb_byte pfx
)
1191 /* True if PFX is the start of the 3-byte VEX prefix. */
1194 vex3_prefix_p (gdb_byte pfx
)
1199 /* Skip the legacy instruction prefixes in INSN.
1200 We assume INSN is properly sentineled so we don't have to worry
1201 about falling off the end of the buffer. */
1204 amd64_skip_prefixes (gdb_byte
*insn
)
1210 case DATA_PREFIX_OPCODE
:
1211 case ADDR_PREFIX_OPCODE
:
1212 case CS_PREFIX_OPCODE
:
1213 case DS_PREFIX_OPCODE
:
1214 case ES_PREFIX_OPCODE
:
1215 case FS_PREFIX_OPCODE
:
1216 case GS_PREFIX_OPCODE
:
1217 case SS_PREFIX_OPCODE
:
1218 case LOCK_PREFIX_OPCODE
:
1219 case REPE_PREFIX_OPCODE
:
1220 case REPNE_PREFIX_OPCODE
:
1232 /* Return an integer register (other than RSP) that is unused as an input
1234 In order to not require adding a rex prefix if the insn doesn't already
1235 have one, the result is restricted to RAX ... RDI, sans RSP.
1236 The register numbering of the result follows architecture ordering,
1240 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1242 /* 1 bit for each reg */
1243 int used_regs_mask
= 0;
1245 /* There can be at most 3 int regs used as inputs in an insn, and we have
1246 7 to choose from (RAX ... RDI, sans RSP).
1247 This allows us to take a conservative approach and keep things simple.
1248 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1249 that implicitly specify RAX. */
1252 used_regs_mask
|= 1 << EAX_REG_NUM
;
1253 /* Similarily avoid RDX, implicit operand in divides. */
1254 used_regs_mask
|= 1 << EDX_REG_NUM
;
1256 used_regs_mask
|= 1 << ESP_REG_NUM
;
1258 /* If the opcode is one byte long and there's no ModRM byte,
1259 assume the opcode specifies a register. */
1260 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1261 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1263 /* Mark used regs in the modrm/sib bytes. */
1264 if (details
->modrm_offset
!= -1)
1266 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1267 int mod
= MODRM_MOD_FIELD (modrm
);
1268 int reg
= MODRM_REG_FIELD (modrm
);
1269 int rm
= MODRM_RM_FIELD (modrm
);
1270 int have_sib
= mod
!= 3 && rm
== 4;
1272 /* Assume the reg field of the modrm byte specifies a register. */
1273 used_regs_mask
|= 1 << reg
;
1277 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1278 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1279 used_regs_mask
|= 1 << base
;
1280 used_regs_mask
|= 1 << idx
;
1284 used_regs_mask
|= 1 << rm
;
1288 gdb_assert (used_regs_mask
< 256);
1289 gdb_assert (used_regs_mask
!= 255);
1291 /* Finally, find a free reg. */
1295 for (i
= 0; i
< 8; ++i
)
1297 if (! (used_regs_mask
& (1 << i
)))
1301 /* We shouldn't get here. */
1302 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1306 /* Extract the details of INSN that we need. */
1309 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1311 gdb_byte
*start
= insn
;
1314 details
->raw_insn
= insn
;
1316 details
->opcode_len
= -1;
1317 details
->enc_prefix_offset
= -1;
1318 details
->opcode_offset
= -1;
1319 details
->modrm_offset
= -1;
1321 /* Skip legacy instruction prefixes. */
1322 insn
= amd64_skip_prefixes (insn
);
1324 /* Skip REX/VEX instruction encoding prefixes. */
1325 if (rex_prefix_p (*insn
))
1327 details
->enc_prefix_offset
= insn
- start
;
1330 else if (vex2_prefix_p (*insn
))
1332 /* Don't record the offset in this case because this prefix has
1333 no REX.B equivalent. */
1336 else if (vex3_prefix_p (*insn
))
1338 details
->enc_prefix_offset
= insn
- start
;
1342 details
->opcode_offset
= insn
- start
;
1344 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1346 /* Two or three-byte opcode. */
1348 need_modrm
= twobyte_has_modrm
[*insn
];
1350 /* Check for three-byte opcode. */
1360 details
->opcode_len
= 3;
1363 details
->opcode_len
= 2;
1369 /* One-byte opcode. */
1370 need_modrm
= onebyte_has_modrm
[*insn
];
1371 details
->opcode_len
= 1;
1377 details
->modrm_offset
= insn
- start
;
1381 /* Update %rip-relative addressing in INSN.
1383 %rip-relative addressing only uses a 32-bit displacement.
1384 32 bits is not enough to be guaranteed to cover the distance between where
1385 the real instruction is and where its copy is.
1386 Convert the insn to use base+disp addressing.
1387 We set base = pc + insn_length so we can leave disp unchanged. */
1390 fixup_riprel (struct gdbarch
*gdbarch
,
1391 amd64_displaced_step_copy_insn_closure
*dsc
,
1392 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1394 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1395 int modrm_offset
= insn_details
->modrm_offset
;
1396 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1399 int arch_tmp_regno
, tmp_regno
;
1400 ULONGEST orig_value
;
1402 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1405 /* Compute the rip-relative address. */
1406 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
.data (),
1407 dsc
->insn_buf
.size (), from
);
1408 rip_base
= from
+ insn_length
;
1410 /* We need a register to hold the address.
1411 Pick one not used in the insn.
1412 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1413 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1414 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1416 /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
1417 static constexpr gdb_byte VEX3_NOT_B
= 0x20;
1419 /* REX.B should be unset (VEX.!B set) as we were using rip-relative
1420 addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
1422 if (insn_details
->enc_prefix_offset
!= -1)
1424 gdb_byte
*pfx
= &dsc
->insn_buf
[insn_details
->enc_prefix_offset
];
1425 if (rex_prefix_p (pfx
[0]))
1427 else if (vex3_prefix_p (pfx
[0]))
1428 pfx
[1] |= VEX3_NOT_B
;
1430 gdb_assert_not_reached ("unhandled prefix");
1433 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1434 dsc
->tmp_regno
= tmp_regno
;
1435 dsc
->tmp_save
= orig_value
;
1438 /* Convert the ModRM field to be base+disp. */
1439 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1440 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1442 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1444 displaced_debug_printf ("%%rip-relative addressing used.");
1445 displaced_debug_printf ("using temp reg %d, old value %s, new value %s",
1446 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1447 paddress (gdbarch
, rip_base
));
1451 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1452 amd64_displaced_step_copy_insn_closure
*dsc
,
1453 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1455 const struct amd64_insn
*details
= &dsc
->insn_details
;
1457 if (details
->modrm_offset
!= -1)
1459 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1461 if ((modrm
& 0xc7) == 0x05)
1463 /* The insn uses rip-relative addressing.
1465 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1470 displaced_step_copy_insn_closure_up
1471 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1472 CORE_ADDR from
, CORE_ADDR to
,
1473 struct regcache
*regs
)
1475 int len
= gdbarch_max_insn_length (gdbarch
);
1476 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1477 continually watch for running off the end of the buffer. */
1478 int fixup_sentinel_space
= len
;
1479 std::unique_ptr
<amd64_displaced_step_copy_insn_closure
> dsc
1480 (new amd64_displaced_step_copy_insn_closure (len
+ fixup_sentinel_space
));
1481 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1482 struct amd64_insn
*details
= &dsc
->insn_details
;
1484 read_memory (from
, buf
, len
);
1486 /* Set up the sentinel space so we don't have to worry about running
1487 off the end of the buffer. An excessive number of leading prefixes
1488 could otherwise cause this. */
1489 memset (buf
+ len
, 0, fixup_sentinel_space
);
1491 amd64_get_insn_details (buf
, details
);
1493 /* GDB may get control back after the insn after the syscall.
1494 Presumably this is a kernel bug.
1495 If this is a syscall, make sure there's a nop afterwards. */
1499 if (amd64_syscall_p (details
, &syscall_length
))
1500 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1503 /* Modify the insn to cope with the address where it will be executed from.
1504 In particular, handle any rip-relative addressing. */
1505 fixup_displaced_copy (gdbarch
, dsc
.get (), from
, to
, regs
);
1507 write_memory (to
, buf
, len
);
1509 displaced_debug_printf ("copy %s->%s: %s",
1510 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1511 displaced_step_dump_bytes (buf
, len
).c_str ());
1513 /* This is a work around for a problem with g++ 4.8. */
1514 return displaced_step_copy_insn_closure_up (dsc
.release ());
1518 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1520 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1522 if (insn
[0] == 0xff)
1524 /* jump near, absolute indirect (/4) */
1525 if ((insn
[1] & 0x38) == 0x20)
1528 /* jump far, absolute indirect (/5) */
1529 if ((insn
[1] & 0x38) == 0x28)
1536 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1539 amd64_jmp_p (const struct amd64_insn
*details
)
1541 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1543 /* jump short, relative. */
1544 if (insn
[0] == 0xeb)
1547 /* jump near, relative. */
1548 if (insn
[0] == 0xe9)
1551 return amd64_absolute_jmp_p (details
);
1555 amd64_absolute_call_p (const struct amd64_insn
*details
)
1557 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1559 if (insn
[0] == 0xff)
1561 /* Call near, absolute indirect (/2) */
1562 if ((insn
[1] & 0x38) == 0x10)
1565 /* Call far, absolute indirect (/3) */
1566 if ((insn
[1] & 0x38) == 0x18)
1574 amd64_ret_p (const struct amd64_insn
*details
)
1576 /* NOTE: gcc can emit "repz ; ret". */
1577 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1581 case 0xc2: /* ret near, pop N bytes */
1582 case 0xc3: /* ret near */
1583 case 0xca: /* ret far, pop N bytes */
1584 case 0xcb: /* ret far */
1585 case 0xcf: /* iret */
1594 amd64_call_p (const struct amd64_insn
*details
)
1596 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1598 if (amd64_absolute_call_p (details
))
1601 /* call near, relative */
1602 if (insn
[0] == 0xe8)
1608 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1609 length in bytes. Otherwise, return zero. */
1612 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1614 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1616 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1625 /* Classify the instruction at ADDR using PRED.
1626 Throw an error if the memory can't be read. */
1629 amd64_classify_insn_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1630 int (*pred
) (const struct amd64_insn
*))
1632 struct amd64_insn details
;
1634 int len
, classification
;
1636 len
= gdbarch_max_insn_length (gdbarch
);
1637 buf
= (gdb_byte
*) alloca (len
);
1639 read_code (addr
, buf
, len
);
1640 amd64_get_insn_details (buf
, &details
);
1642 classification
= pred (&details
);
1644 return classification
;
1647 /* The gdbarch insn_is_call method. */
1650 amd64_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1652 return amd64_classify_insn_at (gdbarch
, addr
, amd64_call_p
);
1655 /* The gdbarch insn_is_ret method. */
1658 amd64_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1660 return amd64_classify_insn_at (gdbarch
, addr
, amd64_ret_p
);
1663 /* The gdbarch insn_is_jump method. */
1666 amd64_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1668 return amd64_classify_insn_at (gdbarch
, addr
, amd64_jmp_p
);
1671 /* Fix up the state of registers and memory after having single-stepped
1672 a displaced instruction. */
1675 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1676 struct displaced_step_copy_insn_closure
*dsc_
,
1677 CORE_ADDR from
, CORE_ADDR to
,
1678 struct regcache
*regs
)
1680 amd64_displaced_step_copy_insn_closure
*dsc
1681 = (amd64_displaced_step_copy_insn_closure
*) dsc_
;
1682 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1683 /* The offset we applied to the instruction's address. */
1684 ULONGEST insn_offset
= to
- from
;
1685 gdb_byte
*insn
= dsc
->insn_buf
.data ();
1686 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1688 displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...",
1689 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1692 /* If we used a tmp reg, restore it. */
1696 displaced_debug_printf ("restoring reg %d to %s",
1697 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1698 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1701 /* The list of issues to contend with here is taken from
1702 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1703 Yay for Free Software! */
1705 /* Relocate the %rip back to the program's instruction stream,
1708 /* Except in the case of absolute or indirect jump or call
1709 instructions, or a return instruction, the new rip is relative to
1710 the displaced instruction; make it relative to the original insn.
1711 Well, signal handler returns don't need relocation either, but we use the
1712 value of %rip to recognize those; see below. */
1713 if (! amd64_absolute_jmp_p (insn_details
)
1714 && ! amd64_absolute_call_p (insn_details
)
1715 && ! amd64_ret_p (insn_details
))
1720 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1722 /* A signal trampoline system call changes the %rip, resuming
1723 execution of the main program after the signal handler has
1724 returned. That makes them like 'return' instructions; we
1725 shouldn't relocate %rip.
1727 But most system calls don't, and we do need to relocate %rip.
1729 Our heuristic for distinguishing these cases: if stepping
1730 over the system call instruction left control directly after
1731 the instruction, the we relocate --- control almost certainly
1732 doesn't belong in the displaced copy. Otherwise, we assume
1733 the instruction has put control where it belongs, and leave
1734 it unrelocated. Goodness help us if there are PC-relative
1736 if (amd64_syscall_p (insn_details
, &insn_len
)
1737 && orig_rip
!= to
+ insn_len
1738 /* GDB can get control back after the insn after the syscall.
1739 Presumably this is a kernel bug.
1740 Fixup ensures its a nop, we add one to the length for it. */
1741 && orig_rip
!= to
+ insn_len
+ 1)
1742 displaced_debug_printf ("syscall changed %%rip; not relocating");
1745 ULONGEST rip
= orig_rip
- insn_offset
;
1747 /* If we just stepped over a breakpoint insn, we don't backup
1748 the pc on purpose; this is to match behaviour without
1751 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1753 displaced_debug_printf ("relocated %%rip from %s to %s",
1754 paddress (gdbarch
, orig_rip
),
1755 paddress (gdbarch
, rip
));
1759 /* If the instruction was PUSHFL, then the TF bit will be set in the
1760 pushed value, and should be cleared. We'll leave this for later,
1761 since GDB already messes up the TF flag when stepping over a
1764 /* If the instruction was a call, the return address now atop the
1765 stack is the address following the copied instruction. We need
1766 to make it the address following the original instruction. */
1767 if (amd64_call_p (insn_details
))
1771 const ULONGEST retaddr_len
= 8;
1773 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1774 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1775 retaddr
= (retaddr
- insn_offset
) & 0xffffffffffffffffULL
;
1776 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1778 displaced_debug_printf ("relocated return addr at %s to %s",
1779 paddress (gdbarch
, rsp
),
1780 paddress (gdbarch
, retaddr
));
1784 /* If the instruction INSN uses RIP-relative addressing, return the
1785 offset into the raw INSN where the displacement to be adjusted is
1786 found. Returns 0 if the instruction doesn't use RIP-relative
1790 rip_relative_offset (struct amd64_insn
*insn
)
1792 if (insn
->modrm_offset
!= -1)
1794 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1796 if ((modrm
& 0xc7) == 0x05)
1798 /* The displacement is found right after the ModRM byte. */
1799 return insn
->modrm_offset
+ 1;
1807 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1809 target_write_memory (*to
, buf
, len
);
1814 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1815 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1817 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1818 int len
= gdbarch_max_insn_length (gdbarch
);
1819 /* Extra space for sentinels. */
1820 int fixup_sentinel_space
= len
;
1821 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
+ fixup_sentinel_space
);
1822 struct amd64_insn insn_details
;
1824 LONGEST rel32
, newrel
;
1828 read_memory (oldloc
, buf
, len
);
1830 /* Set up the sentinel space so we don't have to worry about running
1831 off the end of the buffer. An excessive number of leading prefixes
1832 could otherwise cause this. */
1833 memset (buf
+ len
, 0, fixup_sentinel_space
);
1836 amd64_get_insn_details (insn
, &insn_details
);
1838 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1840 /* Skip legacy instruction prefixes. */
1841 insn
= amd64_skip_prefixes (insn
);
1843 /* Adjust calls with 32-bit relative addresses as push/jump, with
1844 the address pushed being the location where the original call in
1845 the user program would return to. */
1846 if (insn
[0] == 0xe8)
1848 gdb_byte push_buf
[32];
1852 /* Where "ret" in the original code will return to. */
1853 ret_addr
= oldloc
+ insn_length
;
1855 /* If pushing an address higher than or equal to 0x80000000,
1856 avoid 'pushq', as that sign extends its 32-bit operand, which
1857 would be incorrect. */
1858 if (ret_addr
<= 0x7fffffff)
1860 push_buf
[0] = 0x68; /* pushq $... */
1861 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1866 push_buf
[i
++] = 0x48; /* sub $0x8,%rsp */
1867 push_buf
[i
++] = 0x83;
1868 push_buf
[i
++] = 0xec;
1869 push_buf
[i
++] = 0x08;
1871 push_buf
[i
++] = 0xc7; /* movl $imm,(%rsp) */
1872 push_buf
[i
++] = 0x04;
1873 push_buf
[i
++] = 0x24;
1874 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1875 ret_addr
& 0xffffffff);
1878 push_buf
[i
++] = 0xc7; /* movl $imm,4(%rsp) */
1879 push_buf
[i
++] = 0x44;
1880 push_buf
[i
++] = 0x24;
1881 push_buf
[i
++] = 0x04;
1882 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1886 gdb_assert (i
<= sizeof (push_buf
));
1887 /* Push the push. */
1888 append_insns (to
, i
, push_buf
);
1890 /* Convert the relative call to a relative jump. */
1893 /* Adjust the destination offset. */
1894 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1895 newrel
= (oldloc
- *to
) + rel32
;
1896 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1898 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1899 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1900 hex_string (newrel
), paddress (gdbarch
, *to
));
1902 /* Write the adjusted jump into its displaced location. */
1903 append_insns (to
, 5, insn
);
1907 offset
= rip_relative_offset (&insn_details
);
1910 /* Adjust jumps with 32-bit relative addresses. Calls are
1911 already handled above. */
1912 if (insn
[0] == 0xe9)
1914 /* Adjust conditional jumps. */
1915 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1921 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1922 newrel
= (oldloc
- *to
) + rel32
;
1923 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1924 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1925 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1926 hex_string (newrel
), paddress (gdbarch
, *to
));
1929 /* Write the adjusted instruction into its displaced location. */
1930 append_insns (to
, insn_length
, buf
);
1934 /* The maximum number of saved registers. This should include %rip. */
1935 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1937 struct amd64_frame_cache
1942 CORE_ADDR sp_offset
;
1945 /* Saved registers. */
1946 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1950 /* Do we have a frame? */
1954 /* Initialize a frame cache. */
1957 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1964 cache
->sp_offset
= -8;
1967 /* Saved registers. We initialize these to -1 since zero is a valid
1968 offset (that's where %rbp is supposed to be stored).
1969 The values start out as being offsets, and are later converted to
1970 addresses (at which point -1 is interpreted as an address, still meaning
1972 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1973 cache
->saved_regs
[i
] = -1;
1974 cache
->saved_sp
= 0;
1975 cache
->saved_sp_reg
= -1;
1977 /* Frameless until proven otherwise. */
1978 cache
->frameless_p
= 1;
1981 /* Allocate and initialize a frame cache. */
1983 static struct amd64_frame_cache
*
1984 amd64_alloc_frame_cache (void)
1986 struct amd64_frame_cache
*cache
;
1988 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1989 amd64_init_frame_cache (cache
);
1993 /* GCC 4.4 and later, can put code in the prologue to realign the
1994 stack pointer. Check whether PC points to such code, and update
1995 CACHE accordingly. Return the first instruction after the code
1996 sequence or CURRENT_PC, whichever is smaller. If we don't
1997 recognize the code, return PC. */
2000 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2001 struct amd64_frame_cache
*cache
)
2003 /* There are 2 code sequences to re-align stack before the frame
2006 1. Use a caller-saved saved register:
2012 2. Use a callee-saved saved register:
2019 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2021 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2022 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2027 int offset
, offset_and
;
2029 if (target_read_code (pc
, buf
, sizeof buf
))
2032 /* Check caller-saved saved register. The first instruction has
2033 to be "leaq 8(%rsp), %reg". */
2034 if ((buf
[0] & 0xfb) == 0x48
2039 /* MOD must be binary 10 and R/M must be binary 100. */
2040 if ((buf
[2] & 0xc7) != 0x44)
2043 /* REG has register number. */
2044 reg
= (buf
[2] >> 3) & 7;
2046 /* Check the REX.R bit. */
2054 /* Check callee-saved saved register. The first instruction
2055 has to be "pushq %reg". */
2057 if ((buf
[0] & 0xf8) == 0x50)
2059 else if ((buf
[0] & 0xf6) == 0x40
2060 && (buf
[1] & 0xf8) == 0x50)
2062 /* Check the REX.B bit. */
2063 if ((buf
[0] & 1) != 0)
2072 reg
+= buf
[offset
] & 0x7;
2076 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2077 if ((buf
[offset
] & 0xfb) != 0x48
2078 || buf
[offset
+ 1] != 0x8d
2079 || buf
[offset
+ 3] != 0x24
2080 || buf
[offset
+ 4] != 0x10)
2083 /* MOD must be binary 10 and R/M must be binary 100. */
2084 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2087 /* REG has register number. */
2088 r
= (buf
[offset
+ 2] >> 3) & 7;
2090 /* Check the REX.R bit. */
2091 if (buf
[offset
] == 0x4c)
2094 /* Registers in pushq and leaq have to be the same. */
2101 /* Rigister can't be %rsp nor %rbp. */
2102 if (reg
== 4 || reg
== 5)
2105 /* The next instruction has to be "andq $-XXX, %rsp". */
2106 if (buf
[offset
] != 0x48
2107 || buf
[offset
+ 2] != 0xe4
2108 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2111 offset_and
= offset
;
2112 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2114 /* The next instruction has to be "pushq -8(%reg)". */
2116 if (buf
[offset
] == 0xff)
2118 else if ((buf
[offset
] & 0xf6) == 0x40
2119 && buf
[offset
+ 1] == 0xff)
2121 /* Check the REX.B bit. */
2122 if ((buf
[offset
] & 0x1) != 0)
2129 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2131 if (buf
[offset
+ 1] != 0xf8
2132 || (buf
[offset
] & 0xf8) != 0x70)
2135 /* R/M has register. */
2136 r
+= buf
[offset
] & 7;
2138 /* Registers in leaq and pushq have to be the same. */
2142 if (current_pc
> pc
+ offset_and
)
2143 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2145 return std::min (pc
+ offset
+ 2, current_pc
);
2148 /* Similar to amd64_analyze_stack_align for x32. */
2151 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2152 struct amd64_frame_cache
*cache
)
2154 /* There are 2 code sequences to re-align stack before the frame
2157 1. Use a caller-saved saved register:
2165 [addr32] leal 8(%rsp), %reg
2167 [addr32] pushq -8(%reg)
2169 2. Use a callee-saved saved register:
2179 [addr32] leal 16(%rsp), %reg
2181 [addr32] pushq -8(%reg)
2183 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2185 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2186 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2188 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2190 0x83 0xe4 0xf0 andl $-16, %esp
2191 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2196 int offset
, offset_and
;
2198 if (target_read_memory (pc
, buf
, sizeof buf
))
2201 /* Skip optional addr32 prefix. */
2202 offset
= buf
[0] == 0x67 ? 1 : 0;
2204 /* Check caller-saved saved register. The first instruction has
2205 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2206 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
2207 && buf
[offset
+ 1] == 0x8d
2208 && buf
[offset
+ 3] == 0x24
2209 && buf
[offset
+ 4] == 0x8)
2211 /* MOD must be binary 10 and R/M must be binary 100. */
2212 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2215 /* REG has register number. */
2216 reg
= (buf
[offset
+ 2] >> 3) & 7;
2218 /* Check the REX.R bit. */
2219 if ((buf
[offset
] & 0x4) != 0)
2226 /* Check callee-saved saved register. The first instruction
2227 has to be "pushq %reg". */
2229 if ((buf
[offset
] & 0xf6) == 0x40
2230 && (buf
[offset
+ 1] & 0xf8) == 0x50)
2232 /* Check the REX.B bit. */
2233 if ((buf
[offset
] & 1) != 0)
2238 else if ((buf
[offset
] & 0xf8) != 0x50)
2242 reg
+= buf
[offset
] & 0x7;
2246 /* Skip optional addr32 prefix. */
2247 if (buf
[offset
] == 0x67)
2250 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2251 "leal 16(%rsp), %reg". */
2252 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
2253 || buf
[offset
+ 1] != 0x8d
2254 || buf
[offset
+ 3] != 0x24
2255 || buf
[offset
+ 4] != 0x10)
2258 /* MOD must be binary 10 and R/M must be binary 100. */
2259 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2262 /* REG has register number. */
2263 r
= (buf
[offset
+ 2] >> 3) & 7;
2265 /* Check the REX.R bit. */
2266 if ((buf
[offset
] & 0x4) != 0)
2269 /* Registers in pushq and leaq have to be the same. */
2276 /* Rigister can't be %rsp nor %rbp. */
2277 if (reg
== 4 || reg
== 5)
2280 /* The next instruction may be "andq $-XXX, %rsp" or
2281 "andl $-XXX, %esp". */
2282 if (buf
[offset
] != 0x48)
2285 if (buf
[offset
+ 2] != 0xe4
2286 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2289 offset_and
= offset
;
2290 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2292 /* Skip optional addr32 prefix. */
2293 if (buf
[offset
] == 0x67)
2296 /* The next instruction has to be "pushq -8(%reg)". */
2298 if (buf
[offset
] == 0xff)
2300 else if ((buf
[offset
] & 0xf6) == 0x40
2301 && buf
[offset
+ 1] == 0xff)
2303 /* Check the REX.B bit. */
2304 if ((buf
[offset
] & 0x1) != 0)
2311 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2313 if (buf
[offset
+ 1] != 0xf8
2314 || (buf
[offset
] & 0xf8) != 0x70)
2317 /* R/M has register. */
2318 r
+= buf
[offset
] & 7;
2320 /* Registers in leaq and pushq have to be the same. */
2324 if (current_pc
> pc
+ offset_and
)
2325 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2327 return std::min (pc
+ offset
+ 2, current_pc
);
2330 /* Do a limited analysis of the prologue at PC and update CACHE
2331 accordingly. Bail out early if CURRENT_PC is reached. Return the
2332 address where the analysis stopped.
2334 We will handle only functions beginning with:
2337 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2339 or (for the X32 ABI):
2342 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2344 The `endbr64` instruction can be found before these sequences, and will be
2347 Any function that doesn't start with one of these sequences will be
2348 assumed to have no prologue and thus no valid frame pointer in
2352 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2353 CORE_ADDR pc
, CORE_ADDR current_pc
,
2354 struct amd64_frame_cache
*cache
)
2356 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2357 /* The `endbr64` instruction. */
2358 static const gdb_byte endbr64
[4] = { 0xf3, 0x0f, 0x1e, 0xfa };
2359 /* There are two variations of movq %rsp, %rbp. */
2360 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2361 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2362 /* Ditto for movl %esp, %ebp. */
2363 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2364 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2369 if (current_pc
<= pc
)
2372 if (gdbarch_ptr_bit (gdbarch
) == 32)
2373 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2375 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2377 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2379 /* Check for the `endbr64` instruction, skip it if found. */
2380 if (op
== endbr64
[0])
2382 read_code (pc
+ 1, buf
, 3);
2384 if (memcmp (buf
, &endbr64
[1], 3) == 0)
2387 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2390 if (current_pc
<= pc
)
2393 if (op
== 0x55) /* pushq %rbp */
2395 /* Take into account that we've executed the `pushq %rbp' that
2396 starts this instruction sequence. */
2397 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2398 cache
->sp_offset
+= 8;
2400 /* If that's all, return now. */
2401 if (current_pc
<= pc
+ 1)
2404 read_code (pc
+ 1, buf
, 3);
2406 /* Check for `movq %rsp, %rbp'. */
2407 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2408 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2410 /* OK, we actually have a frame. */
2411 cache
->frameless_p
= 0;
2415 /* For X32, also check for `movl %esp, %ebp'. */
2416 if (gdbarch_ptr_bit (gdbarch
) == 32)
2418 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2419 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2421 /* OK, we actually have a frame. */
2422 cache
->frameless_p
= 0;
2433 /* Work around false termination of prologue - GCC PR debug/48827.
2435 START_PC is the first instruction of a function, PC is its minimal already
2436 determined advanced address. Function returns PC if it has nothing to do.
2440 <-- here is 0 lines advance - the false prologue end marker.
2441 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2442 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2443 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2444 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2445 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2446 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2447 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2448 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2452 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2454 struct symtab_and_line start_pc_sal
, next_sal
;
2455 gdb_byte buf
[4 + 8 * 7];
2461 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2462 if (start_pc_sal
.symtab
== NULL
2463 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2464 (SYMTAB_COMPUNIT (start_pc_sal
.symtab
))) < 6
2465 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2468 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2469 if (next_sal
.line
!= start_pc_sal
.line
)
2472 /* START_PC can be from overlayed memory, ignored here. */
2473 if (target_read_code (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2477 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2484 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2486 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2487 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2488 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2492 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2494 /* 8-bit displacement. */
2498 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2500 /* 32-bit displacement. */
2508 if (offset
- 4 != buf
[3])
2511 return next_sal
.end
;
2514 /* Return PC of first real instruction. */
2517 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2519 struct amd64_frame_cache cache
;
2521 CORE_ADDR func_addr
;
2523 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2525 CORE_ADDR post_prologue_pc
2526 = skip_prologue_using_sal (gdbarch
, func_addr
);
2527 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
2529 /* LLVM backend (Clang/Flang) always emits a line note before the
2530 prologue and another one after. We trust clang to emit usable
2532 if (post_prologue_pc
2534 && COMPUNIT_PRODUCER (cust
) != NULL
2535 && producer_is_llvm (COMPUNIT_PRODUCER (cust
))))
2536 return std::max (start_pc
, post_prologue_pc
);
2539 amd64_init_frame_cache (&cache
);
2540 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2542 if (cache
.frameless_p
)
2545 return amd64_skip_xmm_prologue (pc
, start_pc
);
2549 /* Normal frames. */
2552 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2553 struct amd64_frame_cache
*cache
)
2555 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2556 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2560 cache
->pc
= get_frame_func (this_frame
);
2562 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2565 if (cache
->frameless_p
)
2567 /* We didn't find a valid frame. If we're at the start of a
2568 function, or somewhere half-way its prologue, the function's
2569 frame probably hasn't been fully setup yet. Try to
2570 reconstruct the base address for the stack frame by looking
2571 at the stack pointer. For truly "frameless" functions this
2574 if (cache
->saved_sp_reg
!= -1)
2576 /* Stack pointer has been saved. */
2577 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2578 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2580 /* We're halfway aligning the stack. */
2581 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2582 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2584 /* This will be added back below. */
2585 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2589 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2590 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2596 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2597 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2600 /* Now that we have the base address for the stack frame we can
2601 calculate the value of %rsp in the calling frame. */
2602 cache
->saved_sp
= cache
->base
+ 16;
2604 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2605 frame we find it at the same offset from the reconstructed base
2606 address. If we're halfway aligning the stack, %rip is handled
2607 differently (see above). */
2608 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2609 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2611 /* Adjust all the saved registers such that they contain addresses
2612 instead of offsets. */
2613 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2614 if (cache
->saved_regs
[i
] != -1)
2615 cache
->saved_regs
[i
] += cache
->base
;
2620 static struct amd64_frame_cache
*
2621 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2623 struct amd64_frame_cache
*cache
;
2626 return (struct amd64_frame_cache
*) *this_cache
;
2628 cache
= amd64_alloc_frame_cache ();
2629 *this_cache
= cache
;
2633 amd64_frame_cache_1 (this_frame
, cache
);
2635 catch (const gdb_exception_error
&ex
)
2637 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2644 static enum unwind_stop_reason
2645 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2648 struct amd64_frame_cache
*cache
=
2649 amd64_frame_cache (this_frame
, this_cache
);
2652 return UNWIND_UNAVAILABLE
;
2654 /* This marks the outermost frame. */
2655 if (cache
->base
== 0)
2656 return UNWIND_OUTERMOST
;
2658 return UNWIND_NO_REASON
;
2662 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2663 struct frame_id
*this_id
)
2665 struct amd64_frame_cache
*cache
=
2666 amd64_frame_cache (this_frame
, this_cache
);
2669 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2670 else if (cache
->base
== 0)
2672 /* This marks the outermost frame. */
2676 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2679 static struct value
*
2680 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2683 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2684 struct amd64_frame_cache
*cache
=
2685 amd64_frame_cache (this_frame
, this_cache
);
2687 gdb_assert (regnum
>= 0);
2689 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2690 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2692 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2693 return frame_unwind_got_memory (this_frame
, regnum
,
2694 cache
->saved_regs
[regnum
]);
2696 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2699 static const struct frame_unwind amd64_frame_unwind
=
2702 amd64_frame_unwind_stop_reason
,
2703 amd64_frame_this_id
,
2704 amd64_frame_prev_register
,
2706 default_frame_sniffer
2709 /* Generate a bytecode expression to get the value of the saved PC. */
2712 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2713 struct agent_expr
*ax
, struct axs_value
*value
,
2716 /* The following sequence assumes the traditional use of the base
2718 ax_reg (ax
, AMD64_RBP_REGNUM
);
2720 ax_simple (ax
, aop_add
);
2721 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2722 value
->kind
= axs_lvalue_memory
;
2726 /* Signal trampolines. */
2728 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2729 64-bit variants. This would require using identical frame caches
2730 on both platforms. */
2732 static struct amd64_frame_cache
*
2733 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2735 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2736 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2737 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2738 struct amd64_frame_cache
*cache
;
2744 return (struct amd64_frame_cache
*) *this_cache
;
2746 cache
= amd64_alloc_frame_cache ();
2750 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2751 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2753 addr
= tdep
->sigcontext_addr (this_frame
);
2754 gdb_assert (tdep
->sc_reg_offset
);
2755 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2756 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2757 if (tdep
->sc_reg_offset
[i
] != -1)
2758 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2762 catch (const gdb_exception_error
&ex
)
2764 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2768 *this_cache
= cache
;
2772 static enum unwind_stop_reason
2773 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2776 struct amd64_frame_cache
*cache
=
2777 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2780 return UNWIND_UNAVAILABLE
;
2782 return UNWIND_NO_REASON
;
2786 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2787 void **this_cache
, struct frame_id
*this_id
)
2789 struct amd64_frame_cache
*cache
=
2790 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2793 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2794 else if (cache
->base
== 0)
2796 /* This marks the outermost frame. */
2800 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2803 static struct value
*
2804 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2805 void **this_cache
, int regnum
)
2807 /* Make sure we've initialized the cache. */
2808 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2810 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2814 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2815 struct frame_info
*this_frame
,
2818 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2820 /* We shouldn't even bother if we don't have a sigcontext_addr
2822 if (tdep
->sigcontext_addr
== NULL
)
2825 if (tdep
->sigtramp_p
!= NULL
)
2827 if (tdep
->sigtramp_p (this_frame
))
2831 if (tdep
->sigtramp_start
!= 0)
2833 CORE_ADDR pc
= get_frame_pc (this_frame
);
2835 gdb_assert (tdep
->sigtramp_end
!= 0);
2836 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2843 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2846 amd64_sigtramp_frame_unwind_stop_reason
,
2847 amd64_sigtramp_frame_this_id
,
2848 amd64_sigtramp_frame_prev_register
,
2850 amd64_sigtramp_frame_sniffer
2855 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2857 struct amd64_frame_cache
*cache
=
2858 amd64_frame_cache (this_frame
, this_cache
);
2863 static const struct frame_base amd64_frame_base
=
2865 &amd64_frame_unwind
,
2866 amd64_frame_base_address
,
2867 amd64_frame_base_address
,
2868 amd64_frame_base_address
2871 /* Normal frames, but in a function epilogue. */
2873 /* Implement the stack_frame_destroyed_p gdbarch method.
2875 The epilogue is defined here as the 'ret' instruction, which will
2876 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2877 the function's stack frame. */
2880 amd64_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2883 struct compunit_symtab
*cust
;
2885 cust
= find_pc_compunit_symtab (pc
);
2886 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2889 if (target_read_memory (pc
, &insn
, 1))
2890 return 0; /* Can't read memory at pc. */
2892 if (insn
!= 0xc3) /* 'ret' instruction. */
2899 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2900 struct frame_info
*this_frame
,
2901 void **this_prologue_cache
)
2903 if (frame_relative_level (this_frame
) == 0)
2904 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2905 get_frame_pc (this_frame
));
2910 static struct amd64_frame_cache
*
2911 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2913 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2914 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2915 struct amd64_frame_cache
*cache
;
2919 return (struct amd64_frame_cache
*) *this_cache
;
2921 cache
= amd64_alloc_frame_cache ();
2922 *this_cache
= cache
;
2926 /* Cache base will be %esp plus cache->sp_offset (-8). */
2927 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2928 cache
->base
= extract_unsigned_integer (buf
, 8,
2929 byte_order
) + cache
->sp_offset
;
2931 /* Cache pc will be the frame func. */
2932 cache
->pc
= get_frame_pc (this_frame
);
2934 /* The saved %esp will be at cache->base plus 16. */
2935 cache
->saved_sp
= cache
->base
+ 16;
2937 /* The saved %eip will be at cache->base plus 8. */
2938 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2942 catch (const gdb_exception_error
&ex
)
2944 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2951 static enum unwind_stop_reason
2952 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2955 struct amd64_frame_cache
*cache
2956 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2959 return UNWIND_UNAVAILABLE
;
2961 return UNWIND_NO_REASON
;
2965 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2967 struct frame_id
*this_id
)
2969 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2973 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2975 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2978 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2981 amd64_epilogue_frame_unwind_stop_reason
,
2982 amd64_epilogue_frame_this_id
,
2983 amd64_frame_prev_register
,
2985 amd64_epilogue_frame_sniffer
2988 static struct frame_id
2989 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2993 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2995 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2998 /* 16 byte align the SP per frame requirements. */
3001 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3003 return sp
& -(CORE_ADDR
)16;
3007 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3008 in the floating-point register set REGSET to register cache
3009 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3012 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3013 int regnum
, const void *fpregs
, size_t len
)
3015 struct gdbarch
*gdbarch
= regcache
->arch ();
3016 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3018 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3019 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
3022 /* Collect register REGNUM from the register cache REGCACHE and store
3023 it in the buffer specified by FPREGS and LEN as described by the
3024 floating-point register set REGSET. If REGNUM is -1, do this for
3025 all registers in REGSET. */
3028 amd64_collect_fpregset (const struct regset
*regset
,
3029 const struct regcache
*regcache
,
3030 int regnum
, void *fpregs
, size_t len
)
3032 struct gdbarch
*gdbarch
= regcache
->arch ();
3033 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3035 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3036 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
3039 const struct regset amd64_fpregset
=
3041 NULL
, amd64_supply_fpregset
, amd64_collect_fpregset
3045 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
3046 %rdi. We expect its value to be a pointer to the jmp_buf structure
3047 from which we extract the address that we will land at. This
3048 address is copied into PC. This routine returns non-zero on
3052 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
3056 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3057 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
3058 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
3060 /* If JB_PC_OFFSET is -1, we have no way to find out where the
3061 longjmp will land. */
3062 if (jb_pc_offset
== -1)
3065 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
3066 jb_addr
= extract_typed_address
3067 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
3068 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
3071 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
3076 static const int amd64_record_regmap
[] =
3078 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
3079 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
3080 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
3081 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
3082 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
3083 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
3086 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
3089 amd64_in_indirect_branch_thunk (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3091 return x86_in_indirect_branch_thunk (pc
, amd64_register_names
,
3097 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3098 const target_desc
*default_tdesc
)
3100 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3101 const struct target_desc
*tdesc
= info
.target_desc
;
3102 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
3103 static const char *const stap_register_prefixes
[] = { "%", NULL
};
3104 static const char *const stap_register_indirection_prefixes
[] = { "(",
3106 static const char *const stap_register_indirection_suffixes
[] = { ")",
3109 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3110 floating-point registers. */
3111 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
3112 tdep
->fpregset
= &amd64_fpregset
;
3114 if (! tdesc_has_registers (tdesc
))
3115 tdesc
= default_tdesc
;
3116 tdep
->tdesc
= tdesc
;
3118 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
3119 tdep
->register_names
= amd64_register_names
;
3121 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512") != NULL
)
3123 tdep
->zmmh_register_names
= amd64_zmmh_names
;
3124 tdep
->k_register_names
= amd64_k_names
;
3125 tdep
->xmm_avx512_register_names
= amd64_xmm_avx512_names
;
3126 tdep
->ymm16h_register_names
= amd64_ymmh_avx512_names
;
3128 tdep
->num_zmm_regs
= 32;
3129 tdep
->num_xmm_avx512_regs
= 16;
3130 tdep
->num_ymm_avx512_regs
= 16;
3132 tdep
->zmm0h_regnum
= AMD64_ZMM0H_REGNUM
;
3133 tdep
->k0_regnum
= AMD64_K0_REGNUM
;
3134 tdep
->xmm16_regnum
= AMD64_XMM16_REGNUM
;
3135 tdep
->ymm16h_regnum
= AMD64_YMM16H_REGNUM
;
3138 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
3140 tdep
->ymmh_register_names
= amd64_ymmh_names
;
3141 tdep
->num_ymm_regs
= 16;
3142 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
3145 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
)
3147 tdep
->mpx_register_names
= amd64_mpx_names
;
3148 tdep
->bndcfgu_regnum
= AMD64_BNDCFGU_REGNUM
;
3149 tdep
->bnd0r_regnum
= AMD64_BND0R_REGNUM
;
3152 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments") != NULL
)
3154 tdep
->fsbase_regnum
= AMD64_FSBASE_REGNUM
;
3157 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys") != NULL
)
3159 tdep
->pkeys_register_names
= amd64_pkeys_names
;
3160 tdep
->pkru_regnum
= AMD64_PKRU_REGNUM
;
3161 tdep
->num_pkeys_regs
= 1;
3164 tdep
->num_byte_regs
= 20;
3165 tdep
->num_word_regs
= 16;
3166 tdep
->num_dword_regs
= 16;
3167 /* Avoid wiring in the MMX registers for now. */
3168 tdep
->num_mmx_regs
= 0;
3170 set_gdbarch_pseudo_register_read_value (gdbarch
,
3171 amd64_pseudo_register_read_value
);
3172 set_gdbarch_pseudo_register_write (gdbarch
,
3173 amd64_pseudo_register_write
);
3174 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
3175 amd64_ax_pseudo_register_collect
);
3177 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
3179 /* AMD64 has an FPU and 16 SSE registers. */
3180 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
3181 tdep
->num_xmm_regs
= 16;
3183 /* This is what all the fuss is about. */
3184 set_gdbarch_long_bit (gdbarch
, 64);
3185 set_gdbarch_long_long_bit (gdbarch
, 64);
3186 set_gdbarch_ptr_bit (gdbarch
, 64);
3188 /* In contrast to the i386, on AMD64 a `long double' actually takes
3189 up 128 bits, even though it's still based on the i387 extended
3190 floating-point format which has only 80 significant bits. */
3191 set_gdbarch_long_double_bit (gdbarch
, 128);
3193 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
3195 /* Register numbers of various important registers. */
3196 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
3197 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
3198 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
3199 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
3201 /* The "default" register numbering scheme for AMD64 is referred to
3202 as the "DWARF Register Number Mapping" in the System V psABI.
3203 The preferred debugging format for all known AMD64 targets is
3204 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3205 DWARF-1), but we provide the same mapping just in case. This
3206 mapping is also used for stabs, which GCC does support. */
3207 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3208 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3210 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3211 be in use on any of the supported AMD64 targets. */
3213 /* Call dummy code. */
3214 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
3215 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
3216 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
3218 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
3219 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
3220 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
3222 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
3224 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
3226 tdep
->record_regmap
= amd64_record_regmap
;
3228 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
3230 /* Hook the function epilogue frame unwinder. This unwinder is
3231 appended to the list first, so that it supercedes the other
3232 unwinders in function epilogues. */
3233 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
3235 /* Hook the prologue-based frame unwinders. */
3236 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
3237 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
3238 frame_base_set_default (gdbarch
, &amd64_frame_base
);
3240 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
3242 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
3244 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
3246 /* SystemTap variables and functions. */
3247 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
3248 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
3249 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
3250 stap_register_indirection_prefixes
);
3251 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
3252 stap_register_indirection_suffixes
);
3253 set_gdbarch_stap_is_single_operand (gdbarch
,
3254 i386_stap_is_single_operand
);
3255 set_gdbarch_stap_parse_special_token (gdbarch
,
3256 i386_stap_parse_special_token
);
3257 set_gdbarch_insn_is_call (gdbarch
, amd64_insn_is_call
);
3258 set_gdbarch_insn_is_ret (gdbarch
, amd64_insn_is_ret
);
3259 set_gdbarch_insn_is_jump (gdbarch
, amd64_insn_is_jump
);
3261 set_gdbarch_in_indirect_branch_thunk (gdbarch
,
3262 amd64_in_indirect_branch_thunk
);
3264 register_amd64_ravenscar_ops (gdbarch
);
3267 /* Initialize ARCH for x86-64, no osabi. */
3270 amd64_none_init_abi (gdbarch_info info
, gdbarch
*arch
)
3272 amd64_init_abi (info
, arch
, amd64_target_description (X86_XSTATE_SSE_MASK
,
3276 static struct type
*
3277 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3279 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3281 switch (regnum
- tdep
->eax_regnum
)
3283 case AMD64_RBP_REGNUM
: /* %ebp */
3284 case AMD64_RSP_REGNUM
: /* %esp */
3285 return builtin_type (gdbarch
)->builtin_data_ptr
;
3286 case AMD64_RIP_REGNUM
: /* %eip */
3287 return builtin_type (gdbarch
)->builtin_func_ptr
;
3290 return i386_pseudo_register_type (gdbarch
, regnum
);
3294 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3295 const target_desc
*default_tdesc
)
3297 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3299 amd64_init_abi (info
, gdbarch
, default_tdesc
);
3301 tdep
->num_dword_regs
= 17;
3302 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
3304 set_gdbarch_long_bit (gdbarch
, 32);
3305 set_gdbarch_ptr_bit (gdbarch
, 32);
3308 /* Initialize ARCH for x64-32, no osabi. */
3311 amd64_x32_none_init_abi (gdbarch_info info
, gdbarch
*arch
)
3313 amd64_x32_init_abi (info
, arch
,
3314 amd64_target_description (X86_XSTATE_SSE_MASK
, true));
3317 /* Return the target description for a specified XSAVE feature mask. */
3319 const struct target_desc
*
3320 amd64_target_description (uint64_t xcr0
, bool segments
)
3322 static target_desc
*amd64_tdescs \
3323 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
3324 target_desc
**tdesc
;
3326 tdesc
= &amd64_tdescs
[(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
3327 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
3328 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
3329 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0]
3333 *tdesc
= amd64_create_target_description (xcr0
, false, false,
3339 void _initialize_amd64_tdep ();
3341 _initialize_amd64_tdep ()
3343 gdbarch_register_osabi (bfd_arch_i386
, bfd_mach_x86_64
, GDB_OSABI_NONE
,
3344 amd64_none_init_abi
);
3345 gdbarch_register_osabi (bfd_arch_i386
, bfd_mach_x64_32
, GDB_OSABI_NONE
,
3346 amd64_x32_none_init_abi
);
3350 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3351 sense that the instruction pointer and data pointer are simply
3352 64-bit offsets into the code segment and the data segment instead
3353 of a selector offset pair. The functions below store the upper 32
3354 bits of these pointers (instead of just the 16-bits of the segment
3357 /* Fill register REGNUM in REGCACHE with the appropriate
3358 floating-point or SSE register value from *FXSAVE. If REGNUM is
3359 -1, do this for all registers. This function masks off any of the
3360 reserved bits in *FXSAVE. */
3363 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3366 struct gdbarch
*gdbarch
= regcache
->arch ();
3367 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3369 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3372 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3374 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
3376 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3377 regcache
->raw_supply (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3378 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3379 regcache
->raw_supply (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3383 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3386 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3389 struct gdbarch
*gdbarch
= regcache
->arch ();
3390 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3392 i387_supply_xsave (regcache
, regnum
, xsave
);
3395 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3397 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
3400 clear_bv
= i387_xsave_get_clear_bv (gdbarch
, xsave
);
3402 /* If the FISEG and FOSEG registers have not been initialised yet
3403 (their CLEAR_BV bit is set) then their default values of zero will
3404 have already been setup by I387_SUPPLY_XSAVE. */
3405 if (!(clear_bv
& X86_XSTATE_X87
))
3407 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3408 regcache
->raw_supply (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3409 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3410 regcache
->raw_supply (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3415 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3416 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3417 all registers. This function doesn't touch any of the reserved
3421 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3424 struct gdbarch
*gdbarch
= regcache
->arch ();
3425 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3426 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
3428 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3430 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3432 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3433 regcache
->raw_collect (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3434 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3435 regcache
->raw_collect (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3439 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3442 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3443 void *xsave
, int gcore
)
3445 struct gdbarch
*gdbarch
= regcache
->arch ();
3446 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3447 gdb_byte
*regs
= (gdb_byte
*) xsave
;
3449 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3451 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3453 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3454 regcache
->raw_collect (I387_FISEG_REGNUM (tdep
),
3456 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3457 regcache
->raw_collect (I387_FOSEG_REGNUM (tdep
),