1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2012 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
39 #include "gdb_assert.h"
40 #include "exceptions.h"
41 #include "amd64-tdep.h"
42 #include "i387-tdep.h"
44 #include "features/i386/amd64.c"
45 #include "features/i386/amd64-avx.c"
46 #include "features/i386/x32.c"
47 #include "features/i386/x32-avx.c"
52 /* Note that the AMD64 architecture was previously known as x86-64.
53 The latter is (forever) engraved into the canonical system name as
54 returned by config.guess, and used as the name for the AMD64 port
55 of GNU/Linux. The BSD's have renamed their ports to amd64; they
56 don't like to shout. For GDB we prefer the amd64_-prefix over the
57 x86_64_-prefix since it's so much easier to type. */
59 /* Register information. */
61 static const char *amd64_register_names
[] =
63 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
65 /* %r8 is indeed register number 8. */
66 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
67 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
69 /* %st0 is register number 24. */
70 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
71 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
73 /* %xmm0 is register number 40. */
74 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
75 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
79 static const char *amd64_ymm_names
[] =
81 "ymm0", "ymm1", "ymm2", "ymm3",
82 "ymm4", "ymm5", "ymm6", "ymm7",
83 "ymm8", "ymm9", "ymm10", "ymm11",
84 "ymm12", "ymm13", "ymm14", "ymm15"
87 static const char *amd64_ymmh_names
[] =
89 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
90 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
91 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
92 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
95 /* The registers used to pass integer arguments during a function call. */
96 static int amd64_dummy_call_integer_regs
[] =
98 AMD64_RDI_REGNUM
, /* %rdi */
99 AMD64_RSI_REGNUM
, /* %rsi */
100 AMD64_RDX_REGNUM
, /* %rdx */
101 AMD64_RCX_REGNUM
, /* %rcx */
106 /* DWARF Register Number Mapping as defined in the System V psABI,
109 static int amd64_dwarf_regmap
[] =
111 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
112 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
113 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
114 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
116 /* Frame Pointer Register RBP. */
119 /* Stack Pointer Register RSP. */
122 /* Extended Integer Registers 8 - 15. */
123 8, 9, 10, 11, 12, 13, 14, 15,
125 /* Return Address RA. Mapped to RIP. */
128 /* SSE Registers 0 - 7. */
129 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
130 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
131 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
132 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
134 /* Extended SSE Registers 8 - 15. */
135 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
136 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
137 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
138 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
140 /* Floating Point Registers 0-7. */
141 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
142 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
143 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
144 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
146 /* Control and Status Flags Register. */
149 /* Selector Registers. */
159 /* Segment Base Address Registers. */
165 /* Special Selector Registers. */
169 /* Floating Point Control Registers. */
175 static const int amd64_dwarf_regmap_len
=
176 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
178 /* Convert DWARF register number REG to the appropriate register
179 number used by GDB. */
182 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
184 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
185 int ymm0_regnum
= tdep
->ymm0_regnum
;
188 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
189 regnum
= amd64_dwarf_regmap
[reg
];
192 warning (_("Unmapped DWARF Register #%d encountered."), reg
);
193 else if (ymm0_regnum
>= 0
194 && i386_xmm_regnum_p (gdbarch
, regnum
))
195 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
200 /* Map architectural register numbers to gdb register numbers. */
202 static const int amd64_arch_regmap
[16] =
204 AMD64_RAX_REGNUM
, /* %rax */
205 AMD64_RCX_REGNUM
, /* %rcx */
206 AMD64_RDX_REGNUM
, /* %rdx */
207 AMD64_RBX_REGNUM
, /* %rbx */
208 AMD64_RSP_REGNUM
, /* %rsp */
209 AMD64_RBP_REGNUM
, /* %rbp */
210 AMD64_RSI_REGNUM
, /* %rsi */
211 AMD64_RDI_REGNUM
, /* %rdi */
212 AMD64_R8_REGNUM
, /* %r8 */
213 AMD64_R9_REGNUM
, /* %r9 */
214 AMD64_R10_REGNUM
, /* %r10 */
215 AMD64_R11_REGNUM
, /* %r11 */
216 AMD64_R12_REGNUM
, /* %r12 */
217 AMD64_R13_REGNUM
, /* %r13 */
218 AMD64_R14_REGNUM
, /* %r14 */
219 AMD64_R15_REGNUM
/* %r15 */
222 static const int amd64_arch_regmap_len
=
223 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
225 /* Convert architectural register number REG to the appropriate register
226 number used by GDB. */
229 amd64_arch_reg_to_regnum (int reg
)
231 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
233 return amd64_arch_regmap
[reg
];
236 /* Register names for byte pseudo-registers. */
238 static const char *amd64_byte_names
[] =
240 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
241 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
242 "ah", "bh", "ch", "dh"
245 /* Number of lower byte registers. */
246 #define AMD64_NUM_LOWER_BYTE_REGS 16
248 /* Register names for word pseudo-registers. */
250 static const char *amd64_word_names
[] =
252 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
253 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
256 /* Register names for dword pseudo-registers. */
258 static const char *amd64_dword_names
[] =
260 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
261 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
264 /* Return the name of register REGNUM. */
267 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
269 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
270 if (i386_byte_regnum_p (gdbarch
, regnum
))
271 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
272 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
273 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
274 else if (i386_word_regnum_p (gdbarch
, regnum
))
275 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
276 else if (i386_dword_regnum_p (gdbarch
, regnum
))
277 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
279 return i386_pseudo_register_name (gdbarch
, regnum
);
282 static struct value
*
283 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
284 struct regcache
*regcache
,
287 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
288 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
289 enum register_status status
;
290 struct value
*result_value
;
293 result_value
= allocate_value (register_type (gdbarch
, regnum
));
294 VALUE_LVAL (result_value
) = lval_register
;
295 VALUE_REGNUM (result_value
) = regnum
;
296 buf
= value_contents_raw (result_value
);
298 if (i386_byte_regnum_p (gdbarch
, regnum
))
300 int gpnum
= regnum
- tdep
->al_regnum
;
302 /* Extract (always little endian). */
303 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
305 /* Special handling for AH, BH, CH, DH. */
306 status
= regcache_raw_read (regcache
,
307 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
,
309 if (status
== REG_VALID
)
310 memcpy (buf
, raw_buf
+ 1, 1);
312 mark_value_bytes_unavailable (result_value
, 0,
313 TYPE_LENGTH (value_type (result_value
)));
317 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
318 if (status
== REG_VALID
)
319 memcpy (buf
, raw_buf
, 1);
321 mark_value_bytes_unavailable (result_value
, 0,
322 TYPE_LENGTH (value_type (result_value
)));
325 else if (i386_dword_regnum_p (gdbarch
, regnum
))
327 int gpnum
= regnum
- tdep
->eax_regnum
;
328 /* Extract (always little endian). */
329 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
330 if (status
== REG_VALID
)
331 memcpy (buf
, raw_buf
, 4);
333 mark_value_bytes_unavailable (result_value
, 0,
334 TYPE_LENGTH (value_type (result_value
)));
337 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
344 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
345 struct regcache
*regcache
,
346 int regnum
, const gdb_byte
*buf
)
348 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
349 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
351 if (i386_byte_regnum_p (gdbarch
, regnum
))
353 int gpnum
= regnum
- tdep
->al_regnum
;
355 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
357 /* Read ... AH, BH, CH, DH. */
358 regcache_raw_read (regcache
,
359 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
360 /* ... Modify ... (always little endian). */
361 memcpy (raw_buf
+ 1, buf
, 1);
363 regcache_raw_write (regcache
,
364 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
369 regcache_raw_read (regcache
, gpnum
, raw_buf
);
370 /* ... Modify ... (always little endian). */
371 memcpy (raw_buf
, buf
, 1);
373 regcache_raw_write (regcache
, gpnum
, raw_buf
);
376 else if (i386_dword_regnum_p (gdbarch
, regnum
))
378 int gpnum
= regnum
- tdep
->eax_regnum
;
381 regcache_raw_read (regcache
, gpnum
, raw_buf
);
382 /* ... Modify ... (always little endian). */
383 memcpy (raw_buf
, buf
, 4);
385 regcache_raw_write (regcache
, gpnum
, raw_buf
);
388 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
393 /* Return the union class of CLASS1 and CLASS2. See the psABI for
396 static enum amd64_reg_class
397 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
399 /* Rule (a): If both classes are equal, this is the resulting class. */
400 if (class1
== class2
)
403 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
404 is the other class. */
405 if (class1
== AMD64_NO_CLASS
)
407 if (class2
== AMD64_NO_CLASS
)
410 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
411 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
414 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
415 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
416 return AMD64_INTEGER
;
418 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
419 MEMORY is used as class. */
420 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
421 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
422 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
425 /* Rule (f): Otherwise class SSE is used. */
429 /* Return non-zero if TYPE is a non-POD structure or union type. */
432 amd64_non_pod_p (struct type
*type
)
434 /* ??? A class with a base class certainly isn't POD, but does this
435 catch all non-POD structure types? */
436 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
442 /* Classify TYPE according to the rules for aggregate (structures and
443 arrays) and union types, and store the result in CLASS. */
446 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class
class[2])
448 int len
= TYPE_LENGTH (type
);
450 /* 1. If the size of an object is larger than two eightbytes, or in
451 C++, is a non-POD structure or union type, or contains
452 unaligned fields, it has class memory. */
453 if (len
> 16 || amd64_non_pod_p (type
))
455 class[0] = class[1] = AMD64_MEMORY
;
459 /* 2. Both eightbytes get initialized to class NO_CLASS. */
460 class[0] = class[1] = AMD64_NO_CLASS
;
462 /* 3. Each field of an object is classified recursively so that
463 always two fields are considered. The resulting class is
464 calculated according to the classes of the fields in the
467 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
469 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
471 /* All fields in an array have the same type. */
472 amd64_classify (subtype
, class);
473 if (len
> 8 && class[1] == AMD64_NO_CLASS
)
480 /* Structure or union. */
481 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
482 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
484 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
486 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
487 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
488 enum amd64_reg_class subclass
[2];
489 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
493 bitsize
= TYPE_LENGTH (subtype
) * 8;
494 endpos
= (TYPE_FIELD_BITPOS (type
, i
) + bitsize
- 1) / 64;
496 /* Ignore static fields. */
497 if (field_is_static (&TYPE_FIELD (type
, i
)))
500 gdb_assert (pos
== 0 || pos
== 1);
502 amd64_classify (subtype
, subclass
);
503 class[pos
] = amd64_merge_classes (class[pos
], subclass
[0]);
504 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
505 /* This is a bit of an odd case: We have a field that would
506 normally fit in one of the two eightbytes, except that
507 it is placed in a way that this field straddles them.
508 This has been seen with a structure containing an array.
510 The ABI is a bit unclear in this case, but we assume that
511 this field's class (stored in subclass[0]) must also be merged
512 into class[1]. In other words, our field has a piece stored
513 in the second eight-byte, and thus its class applies to
514 the second eight-byte as well.
516 In the case where the field length exceeds 8 bytes,
517 it should not be necessary to merge the field class
518 into class[1]. As LEN > 8, subclass[1] is necessarily
519 different from AMD64_NO_CLASS. If subclass[1] is equal
520 to subclass[0], then the normal class[1]/subclass[1]
521 merging will take care of everything. For subclass[1]
522 to be different from subclass[0], I can only see the case
523 where we have a SSE/SSEUP or X87/X87UP pair, which both
524 use up all 16 bytes of the aggregate, and are already
525 handled just fine (because each portion sits on its own
527 class[1] = amd64_merge_classes (class[1], subclass
[0]);
529 class[1] = amd64_merge_classes (class[1], subclass
[1]);
533 /* 4. Then a post merger cleanup is done: */
535 /* Rule (a): If one of the classes is MEMORY, the whole argument is
537 if (class[0] == AMD64_MEMORY
|| class[1] == AMD64_MEMORY
)
538 class[0] = class[1] = AMD64_MEMORY
;
540 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
542 if (class[0] == AMD64_SSEUP
)
543 class[0] = AMD64_SSE
;
544 if (class[1] == AMD64_SSEUP
&& class[0] != AMD64_SSE
)
545 class[1] = AMD64_SSE
;
548 /* Classify TYPE, and store the result in CLASS. */
551 amd64_classify (struct type
*type
, enum amd64_reg_class
class[2])
553 enum type_code code
= TYPE_CODE (type
);
554 int len
= TYPE_LENGTH (type
);
556 class[0] = class[1] = AMD64_NO_CLASS
;
558 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
559 long, long long, and pointers are in the INTEGER class. Similarly,
560 range types, used by languages such as Ada, are also in the INTEGER
562 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
563 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
564 || code
== TYPE_CODE_CHAR
565 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
566 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
567 class[0] = AMD64_INTEGER
;
569 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
571 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
572 && (len
== 4 || len
== 8))
574 class[0] = AMD64_SSE
;
576 /* Arguments of types __float128, _Decimal128 and __m128 are split into
577 two halves. The least significant ones belong to class SSE, the most
578 significant one to class SSEUP. */
579 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
580 /* FIXME: __float128, __m128. */
581 class[0] = AMD64_SSE
, class[1] = AMD64_SSEUP
;
583 /* The 64-bit mantissa of arguments of type long double belongs to
584 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
586 else if (code
== TYPE_CODE_FLT
&& len
== 16)
587 /* Class X87 and X87UP. */
588 class[0] = AMD64_X87
, class[1] = AMD64_X87UP
;
591 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
592 || code
== TYPE_CODE_UNION
)
593 amd64_classify_aggregate (type
, class);
596 static enum return_value_convention
597 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
598 struct type
*type
, struct regcache
*regcache
,
599 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
601 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
602 enum amd64_reg_class
class[2];
603 int len
= TYPE_LENGTH (type
);
604 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
605 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
610 gdb_assert (!(readbuf
&& writebuf
));
611 gdb_assert (tdep
->classify
);
613 /* 1. Classify the return type with the classification algorithm. */
614 tdep
->classify (type
, class);
616 /* 2. If the type has class MEMORY, then the caller provides space
617 for the return value and passes the address of this storage in
618 %rdi as if it were the first argument to the function. In effect,
619 this address becomes a hidden first argument.
621 On return %rax will contain the address that has been passed in
622 by the caller in %rdi. */
623 if (class[0] == AMD64_MEMORY
)
625 /* As indicated by the comment above, the ABI guarantees that we
626 can always find the return value just after the function has
633 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
634 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
637 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
640 gdb_assert (class[1] != AMD64_MEMORY
);
641 gdb_assert (len
<= 16);
643 for (i
= 0; len
> 0; i
++, len
-= 8)
651 /* 3. If the class is INTEGER, the next available register
652 of the sequence %rax, %rdx is used. */
653 regnum
= integer_regnum
[integer_reg
++];
657 /* 4. If the class is SSE, the next available SSE register
658 of the sequence %xmm0, %xmm1 is used. */
659 regnum
= sse_regnum
[sse_reg
++];
663 /* 5. If the class is SSEUP, the eightbyte is passed in the
664 upper half of the last used SSE register. */
665 gdb_assert (sse_reg
> 0);
666 regnum
= sse_regnum
[sse_reg
- 1];
671 /* 6. If the class is X87, the value is returned on the X87
672 stack in %st0 as 80-bit x87 number. */
673 regnum
= AMD64_ST0_REGNUM
;
675 i387_return_value (gdbarch
, regcache
);
679 /* 7. If the class is X87UP, the value is returned together
680 with the previous X87 value in %st0. */
681 gdb_assert (i
> 0 && class[0] == AMD64_X87
);
682 regnum
= AMD64_ST0_REGNUM
;
691 gdb_assert (!"Unexpected register class.");
694 gdb_assert (regnum
!= -1);
697 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
700 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
704 return RETURN_VALUE_REGISTER_CONVENTION
;
709 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
710 struct value
**args
, CORE_ADDR sp
, int struct_return
)
712 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
713 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
714 int *integer_regs
= tdep
->call_dummy_integer_regs
;
715 int num_integer_regs
= tdep
->call_dummy_num_integer_regs
;
717 static int sse_regnum
[] =
719 /* %xmm0 ... %xmm7 */
720 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
721 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
722 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
723 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
725 struct value
**stack_args
= alloca (nargs
* sizeof (struct value
*));
726 /* An array that mirrors the stack_args array. For all arguments
727 that are passed by MEMORY, if that argument's address also needs
728 to be stored in a register, the ARG_ADDR_REGNO array will contain
729 that register number (or a negative value otherwise). */
730 int *arg_addr_regno
= alloca (nargs
* sizeof (int));
731 int num_stack_args
= 0;
732 int num_elements
= 0;
738 gdb_assert (tdep
->classify
);
740 /* Reserve a register for the "hidden" argument. */
744 for (i
= 0; i
< nargs
; i
++)
746 struct type
*type
= value_type (args
[i
]);
747 int len
= TYPE_LENGTH (type
);
748 enum amd64_reg_class
class[2];
749 int needed_integer_regs
= 0;
750 int needed_sse_regs
= 0;
753 /* Classify argument. */
754 tdep
->classify (type
, class);
756 /* Calculate the number of integer and SSE registers needed for
758 for (j
= 0; j
< 2; j
++)
760 if (class[j
] == AMD64_INTEGER
)
761 needed_integer_regs
++;
762 else if (class[j
] == AMD64_SSE
)
766 /* Check whether enough registers are available, and if the
767 argument should be passed in registers at all. */
768 if (integer_reg
+ needed_integer_regs
> num_integer_regs
769 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
770 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
772 /* The argument will be passed on the stack. */
773 num_elements
+= ((len
+ 7) / 8);
774 stack_args
[num_stack_args
] = args
[i
];
775 /* If this is an AMD64_MEMORY argument whose address must also
776 be passed in one of the integer registers, reserve that
777 register and associate this value to that register so that
778 we can store the argument address as soon as we know it. */
779 if (class[0] == AMD64_MEMORY
780 && tdep
->memory_args_by_pointer
781 && integer_reg
< tdep
->call_dummy_num_integer_regs
)
782 arg_addr_regno
[num_stack_args
] =
783 tdep
->call_dummy_integer_regs
[integer_reg
++];
785 arg_addr_regno
[num_stack_args
] = -1;
790 /* The argument will be passed in registers. */
791 const gdb_byte
*valbuf
= value_contents (args
[i
]);
794 gdb_assert (len
<= 16);
796 for (j
= 0; len
> 0; j
++, len
-= 8)
804 regnum
= integer_regs
[integer_reg
++];
808 regnum
= sse_regnum
[sse_reg
++];
812 gdb_assert (sse_reg
> 0);
813 regnum
= sse_regnum
[sse_reg
- 1];
818 gdb_assert (!"Unexpected register class.");
821 gdb_assert (regnum
!= -1);
822 memset (buf
, 0, sizeof buf
);
823 memcpy (buf
, valbuf
+ j
* 8, min (len
, 8));
824 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
829 /* Allocate space for the arguments on the stack. */
830 sp
-= num_elements
* 8;
832 /* The psABI says that "The end of the input argument area shall be
833 aligned on a 16 byte boundary." */
836 /* Write out the arguments to the stack. */
837 for (i
= 0; i
< num_stack_args
; i
++)
839 struct type
*type
= value_type (stack_args
[i
]);
840 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
841 int len
= TYPE_LENGTH (type
);
842 CORE_ADDR arg_addr
= sp
+ element
* 8;
844 write_memory (arg_addr
, valbuf
, len
);
845 if (arg_addr_regno
[i
] >= 0)
847 /* We also need to store the address of that argument in
848 the given register. */
850 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
852 store_unsigned_integer (buf
, 8, byte_order
, arg_addr
);
853 regcache_cooked_write (regcache
, arg_addr_regno
[i
], buf
);
855 element
+= ((len
+ 7) / 8);
858 /* The psABI says that "For calls that may call functions that use
859 varargs or stdargs (prototype-less calls or calls to functions
860 containing ellipsis (...) in the declaration) %al is used as
861 hidden argument to specify the number of SSE registers used. */
862 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
867 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
868 struct regcache
*regcache
, CORE_ADDR bp_addr
,
869 int nargs
, struct value
**args
, CORE_ADDR sp
,
870 int struct_return
, CORE_ADDR struct_addr
)
872 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
873 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
876 /* Pass arguments. */
877 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, struct_return
);
879 /* Pass "hidden" argument". */
882 /* The "hidden" argument is passed throught the first argument
884 const int arg_regnum
= tdep
->call_dummy_integer_regs
[0];
886 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
887 regcache_cooked_write (regcache
, arg_regnum
, buf
);
890 /* Reserve some memory on the stack for the integer-parameter registers,
891 if required by the ABI. */
892 if (tdep
->integer_param_regs_saved_in_caller_frame
)
893 sp
-= tdep
->call_dummy_num_integer_regs
* 8;
895 /* Store return address. */
897 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
898 write_memory (sp
, buf
, 8);
900 /* Finally, update the stack pointer... */
901 store_unsigned_integer (buf
, 8, byte_order
, sp
);
902 regcache_cooked_write (regcache
, AMD64_RSP_REGNUM
, buf
);
904 /* ...and fake a frame pointer. */
905 regcache_cooked_write (regcache
, AMD64_RBP_REGNUM
, buf
);
910 /* Displaced instruction handling. */
912 /* A partially decoded instruction.
913 This contains enough details for displaced stepping purposes. */
917 /* The number of opcode bytes. */
919 /* The offset of the rex prefix or -1 if not present. */
921 /* The offset to the first opcode byte. */
923 /* The offset to the modrm byte or -1 if not present. */
926 /* The raw instruction. */
930 struct displaced_step_closure
932 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
937 /* Details of the instruction. */
938 struct amd64_insn insn_details
;
940 /* Amount of space allocated to insn_buf. */
943 /* The possibly modified insn.
944 This is a variable-length field. */
945 gdb_byte insn_buf
[1];
948 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
949 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
950 at which point delete these in favor of libopcodes' versions). */
952 static const unsigned char onebyte_has_modrm
[256] = {
953 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
954 /* ------------------------------- */
955 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
956 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
957 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
958 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
959 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
960 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
961 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
962 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
963 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
964 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
965 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
966 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
967 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
968 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
969 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
970 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
971 /* ------------------------------- */
972 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
975 static const unsigned char twobyte_has_modrm
[256] = {
976 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
977 /* ------------------------------- */
978 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
979 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
980 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
981 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
982 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
983 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
984 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
985 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
986 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
987 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
988 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
989 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
990 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
991 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
992 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
993 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
994 /* ------------------------------- */
995 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
998 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1001 rex_prefix_p (gdb_byte pfx
)
1003 return REX_PREFIX_P (pfx
);
1006 /* Skip the legacy instruction prefixes in INSN.
1007 We assume INSN is properly sentineled so we don't have to worry
1008 about falling off the end of the buffer. */
1011 amd64_skip_prefixes (gdb_byte
*insn
)
1017 case DATA_PREFIX_OPCODE
:
1018 case ADDR_PREFIX_OPCODE
:
1019 case CS_PREFIX_OPCODE
:
1020 case DS_PREFIX_OPCODE
:
1021 case ES_PREFIX_OPCODE
:
1022 case FS_PREFIX_OPCODE
:
1023 case GS_PREFIX_OPCODE
:
1024 case SS_PREFIX_OPCODE
:
1025 case LOCK_PREFIX_OPCODE
:
1026 case REPE_PREFIX_OPCODE
:
1027 case REPNE_PREFIX_OPCODE
:
1039 /* Return an integer register (other than RSP) that is unused as an input
1041 In order to not require adding a rex prefix if the insn doesn't already
1042 have one, the result is restricted to RAX ... RDI, sans RSP.
1043 The register numbering of the result follows architecture ordering,
1047 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1049 /* 1 bit for each reg */
1050 int used_regs_mask
= 0;
1052 /* There can be at most 3 int regs used as inputs in an insn, and we have
1053 7 to choose from (RAX ... RDI, sans RSP).
1054 This allows us to take a conservative approach and keep things simple.
1055 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1056 that implicitly specify RAX. */
1059 used_regs_mask
|= 1 << EAX_REG_NUM
;
1060 /* Similarily avoid RDX, implicit operand in divides. */
1061 used_regs_mask
|= 1 << EDX_REG_NUM
;
1063 used_regs_mask
|= 1 << ESP_REG_NUM
;
1065 /* If the opcode is one byte long and there's no ModRM byte,
1066 assume the opcode specifies a register. */
1067 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1068 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1070 /* Mark used regs in the modrm/sib bytes. */
1071 if (details
->modrm_offset
!= -1)
1073 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1074 int mod
= MODRM_MOD_FIELD (modrm
);
1075 int reg
= MODRM_REG_FIELD (modrm
);
1076 int rm
= MODRM_RM_FIELD (modrm
);
1077 int have_sib
= mod
!= 3 && rm
== 4;
1079 /* Assume the reg field of the modrm byte specifies a register. */
1080 used_regs_mask
|= 1 << reg
;
1084 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1085 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1086 used_regs_mask
|= 1 << base
;
1087 used_regs_mask
|= 1 << idx
;
1091 used_regs_mask
|= 1 << rm
;
1095 gdb_assert (used_regs_mask
< 256);
1096 gdb_assert (used_regs_mask
!= 255);
1098 /* Finally, find a free reg. */
1102 for (i
= 0; i
< 8; ++i
)
1104 if (! (used_regs_mask
& (1 << i
)))
1108 /* We shouldn't get here. */
1109 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1113 /* Extract the details of INSN that we need. */
1116 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1118 gdb_byte
*start
= insn
;
1121 details
->raw_insn
= insn
;
1123 details
->opcode_len
= -1;
1124 details
->rex_offset
= -1;
1125 details
->opcode_offset
= -1;
1126 details
->modrm_offset
= -1;
1128 /* Skip legacy instruction prefixes. */
1129 insn
= amd64_skip_prefixes (insn
);
1131 /* Skip REX instruction prefix. */
1132 if (rex_prefix_p (*insn
))
1134 details
->rex_offset
= insn
- start
;
1138 details
->opcode_offset
= insn
- start
;
1140 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1142 /* Two or three-byte opcode. */
1144 need_modrm
= twobyte_has_modrm
[*insn
];
1146 /* Check for three-byte opcode. */
1156 details
->opcode_len
= 3;
1159 details
->opcode_len
= 2;
1165 /* One-byte opcode. */
1166 need_modrm
= onebyte_has_modrm
[*insn
];
1167 details
->opcode_len
= 1;
1173 details
->modrm_offset
= insn
- start
;
1177 /* Update %rip-relative addressing in INSN.
1179 %rip-relative addressing only uses a 32-bit displacement.
1180 32 bits is not enough to be guaranteed to cover the distance between where
1181 the real instruction is and where its copy is.
1182 Convert the insn to use base+disp addressing.
1183 We set base = pc + insn_length so we can leave disp unchanged. */
1186 fixup_riprel (struct gdbarch
*gdbarch
, struct displaced_step_closure
*dsc
,
1187 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1189 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1190 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1191 int modrm_offset
= insn_details
->modrm_offset
;
1192 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1196 int arch_tmp_regno
, tmp_regno
;
1197 ULONGEST orig_value
;
1199 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1202 /* Compute the rip-relative address. */
1203 disp
= extract_signed_integer (insn
, sizeof (int32_t), byte_order
);
1204 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
,
1205 dsc
->max_len
, from
);
1206 rip_base
= from
+ insn_length
;
1208 /* We need a register to hold the address.
1209 Pick one not used in the insn.
1210 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1211 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1212 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1214 /* REX.B should be unset as we were using rip-relative addressing,
1215 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1216 if (insn_details
->rex_offset
!= -1)
1217 dsc
->insn_buf
[insn_details
->rex_offset
] &= ~REX_B
;
1219 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1220 dsc
->tmp_regno
= tmp_regno
;
1221 dsc
->tmp_save
= orig_value
;
1224 /* Convert the ModRM field to be base+disp. */
1225 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1226 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1228 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1230 if (debug_displaced
)
1231 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1232 "displaced: using temp reg %d, old value %s, new value %s\n",
1233 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1234 paddress (gdbarch
, rip_base
));
1238 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1239 struct displaced_step_closure
*dsc
,
1240 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1242 const struct amd64_insn
*details
= &dsc
->insn_details
;
1244 if (details
->modrm_offset
!= -1)
1246 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1248 if ((modrm
& 0xc7) == 0x05)
1250 /* The insn uses rip-relative addressing.
1252 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1257 struct displaced_step_closure
*
1258 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1259 CORE_ADDR from
, CORE_ADDR to
,
1260 struct regcache
*regs
)
1262 int len
= gdbarch_max_insn_length (gdbarch
);
1263 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1264 continually watch for running off the end of the buffer. */
1265 int fixup_sentinel_space
= len
;
1266 struct displaced_step_closure
*dsc
=
1267 xmalloc (sizeof (*dsc
) + len
+ fixup_sentinel_space
);
1268 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1269 struct amd64_insn
*details
= &dsc
->insn_details
;
1272 dsc
->max_len
= len
+ fixup_sentinel_space
;
1274 read_memory (from
, buf
, len
);
1276 /* Set up the sentinel space so we don't have to worry about running
1277 off the end of the buffer. An excessive number of leading prefixes
1278 could otherwise cause this. */
1279 memset (buf
+ len
, 0, fixup_sentinel_space
);
1281 amd64_get_insn_details (buf
, details
);
1283 /* GDB may get control back after the insn after the syscall.
1284 Presumably this is a kernel bug.
1285 If this is a syscall, make sure there's a nop afterwards. */
1289 if (amd64_syscall_p (details
, &syscall_length
))
1290 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1293 /* Modify the insn to cope with the address where it will be executed from.
1294 In particular, handle any rip-relative addressing. */
1295 fixup_displaced_copy (gdbarch
, dsc
, from
, to
, regs
);
1297 write_memory (to
, buf
, len
);
1299 if (debug_displaced
)
1301 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1302 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1303 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1310 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1312 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1314 if (insn
[0] == 0xff)
1316 /* jump near, absolute indirect (/4) */
1317 if ((insn
[1] & 0x38) == 0x20)
1320 /* jump far, absolute indirect (/5) */
1321 if ((insn
[1] & 0x38) == 0x28)
1329 amd64_absolute_call_p (const struct amd64_insn
*details
)
1331 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1333 if (insn
[0] == 0xff)
1335 /* Call near, absolute indirect (/2) */
1336 if ((insn
[1] & 0x38) == 0x10)
1339 /* Call far, absolute indirect (/3) */
1340 if ((insn
[1] & 0x38) == 0x18)
1348 amd64_ret_p (const struct amd64_insn
*details
)
1350 /* NOTE: gcc can emit "repz ; ret". */
1351 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1355 case 0xc2: /* ret near, pop N bytes */
1356 case 0xc3: /* ret near */
1357 case 0xca: /* ret far, pop N bytes */
1358 case 0xcb: /* ret far */
1359 case 0xcf: /* iret */
1368 amd64_call_p (const struct amd64_insn
*details
)
1370 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1372 if (amd64_absolute_call_p (details
))
1375 /* call near, relative */
1376 if (insn
[0] == 0xe8)
1382 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1383 length in bytes. Otherwise, return zero. */
1386 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1388 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1390 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1399 /* Fix up the state of registers and memory after having single-stepped
1400 a displaced instruction. */
1403 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1404 struct displaced_step_closure
*dsc
,
1405 CORE_ADDR from
, CORE_ADDR to
,
1406 struct regcache
*regs
)
1408 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1409 /* The offset we applied to the instruction's address. */
1410 ULONGEST insn_offset
= to
- from
;
1411 gdb_byte
*insn
= dsc
->insn_buf
;
1412 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1414 if (debug_displaced
)
1415 fprintf_unfiltered (gdb_stdlog
,
1416 "displaced: fixup (%s, %s), "
1417 "insn = 0x%02x 0x%02x ...\n",
1418 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1421 /* If we used a tmp reg, restore it. */
1425 if (debug_displaced
)
1426 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1427 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1428 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1431 /* The list of issues to contend with here is taken from
1432 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1433 Yay for Free Software! */
1435 /* Relocate the %rip back to the program's instruction stream,
1438 /* Except in the case of absolute or indirect jump or call
1439 instructions, or a return instruction, the new rip is relative to
1440 the displaced instruction; make it relative to the original insn.
1441 Well, signal handler returns don't need relocation either, but we use the
1442 value of %rip to recognize those; see below. */
1443 if (! amd64_absolute_jmp_p (insn_details
)
1444 && ! amd64_absolute_call_p (insn_details
)
1445 && ! amd64_ret_p (insn_details
))
1450 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1452 /* A signal trampoline system call changes the %rip, resuming
1453 execution of the main program after the signal handler has
1454 returned. That makes them like 'return' instructions; we
1455 shouldn't relocate %rip.
1457 But most system calls don't, and we do need to relocate %rip.
1459 Our heuristic for distinguishing these cases: if stepping
1460 over the system call instruction left control directly after
1461 the instruction, the we relocate --- control almost certainly
1462 doesn't belong in the displaced copy. Otherwise, we assume
1463 the instruction has put control where it belongs, and leave
1464 it unrelocated. Goodness help us if there are PC-relative
1466 if (amd64_syscall_p (insn_details
, &insn_len
)
1467 && orig_rip
!= to
+ insn_len
1468 /* GDB can get control back after the insn after the syscall.
1469 Presumably this is a kernel bug.
1470 Fixup ensures its a nop, we add one to the length for it. */
1471 && orig_rip
!= to
+ insn_len
+ 1)
1473 if (debug_displaced
)
1474 fprintf_unfiltered (gdb_stdlog
,
1475 "displaced: syscall changed %%rip; "
1476 "not relocating\n");
1480 ULONGEST rip
= orig_rip
- insn_offset
;
1482 /* If we just stepped over a breakpoint insn, we don't backup
1483 the pc on purpose; this is to match behaviour without
1486 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1488 if (debug_displaced
)
1489 fprintf_unfiltered (gdb_stdlog
,
1491 "relocated %%rip from %s to %s\n",
1492 paddress (gdbarch
, orig_rip
),
1493 paddress (gdbarch
, rip
));
1497 /* If the instruction was PUSHFL, then the TF bit will be set in the
1498 pushed value, and should be cleared. We'll leave this for later,
1499 since GDB already messes up the TF flag when stepping over a
1502 /* If the instruction was a call, the return address now atop the
1503 stack is the address following the copied instruction. We need
1504 to make it the address following the original instruction. */
1505 if (amd64_call_p (insn_details
))
1509 const ULONGEST retaddr_len
= 8;
1511 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1512 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1513 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
1514 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1516 if (debug_displaced
)
1517 fprintf_unfiltered (gdb_stdlog
,
1518 "displaced: relocated return addr at %s "
1520 paddress (gdbarch
, rsp
),
1521 paddress (gdbarch
, retaddr
));
1525 /* If the instruction INSN uses RIP-relative addressing, return the
1526 offset into the raw INSN where the displacement to be adjusted is
1527 found. Returns 0 if the instruction doesn't use RIP-relative
1531 rip_relative_offset (struct amd64_insn
*insn
)
1533 if (insn
->modrm_offset
!= -1)
1535 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1537 if ((modrm
& 0xc7) == 0x05)
1539 /* The displacement is found right after the ModRM byte. */
1540 return insn
->modrm_offset
+ 1;
1548 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1550 target_write_memory (*to
, buf
, len
);
1555 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1556 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1558 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1559 int len
= gdbarch_max_insn_length (gdbarch
);
1560 /* Extra space for sentinels. */
1561 int fixup_sentinel_space
= len
;
1562 gdb_byte
*buf
= xmalloc (len
+ fixup_sentinel_space
);
1563 struct amd64_insn insn_details
;
1565 LONGEST rel32
, newrel
;
1569 read_memory (oldloc
, buf
, len
);
1571 /* Set up the sentinel space so we don't have to worry about running
1572 off the end of the buffer. An excessive number of leading prefixes
1573 could otherwise cause this. */
1574 memset (buf
+ len
, 0, fixup_sentinel_space
);
1577 amd64_get_insn_details (insn
, &insn_details
);
1579 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1581 /* Skip legacy instruction prefixes. */
1582 insn
= amd64_skip_prefixes (insn
);
1584 /* Adjust calls with 32-bit relative addresses as push/jump, with
1585 the address pushed being the location where the original call in
1586 the user program would return to. */
1587 if (insn
[0] == 0xe8)
1589 gdb_byte push_buf
[16];
1590 unsigned int ret_addr
;
1592 /* Where "ret" in the original code will return to. */
1593 ret_addr
= oldloc
+ insn_length
;
1594 push_buf
[0] = 0x68; /* pushq $... */
1595 memcpy (&push_buf
[1], &ret_addr
, 4);
1596 /* Push the push. */
1597 append_insns (to
, 5, push_buf
);
1599 /* Convert the relative call to a relative jump. */
1602 /* Adjust the destination offset. */
1603 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1604 newrel
= (oldloc
- *to
) + rel32
;
1605 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1607 if (debug_displaced
)
1608 fprintf_unfiltered (gdb_stdlog
,
1609 "Adjusted insn rel32=%s at %s to"
1610 " rel32=%s at %s\n",
1611 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1612 hex_string (newrel
), paddress (gdbarch
, *to
));
1614 /* Write the adjusted jump into its displaced location. */
1615 append_insns (to
, 5, insn
);
1619 offset
= rip_relative_offset (&insn_details
);
1622 /* Adjust jumps with 32-bit relative addresses. Calls are
1623 already handled above. */
1624 if (insn
[0] == 0xe9)
1626 /* Adjust conditional jumps. */
1627 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1633 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1634 newrel
= (oldloc
- *to
) + rel32
;
1635 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1636 if (debug_displaced
)
1637 fprintf_unfiltered (gdb_stdlog
,
1638 "Adjusted insn rel32=%s at %s to"
1639 " rel32=%s at %s\n",
1640 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1641 hex_string (newrel
), paddress (gdbarch
, *to
));
1644 /* Write the adjusted instruction into its displaced location. */
1645 append_insns (to
, insn_length
, buf
);
1649 /* The maximum number of saved registers. This should include %rip. */
1650 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1652 struct amd64_frame_cache
1657 CORE_ADDR sp_offset
;
1660 /* Saved registers. */
1661 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1665 /* Do we have a frame? */
1669 /* Initialize a frame cache. */
1672 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1679 cache
->sp_offset
= -8;
1682 /* Saved registers. We initialize these to -1 since zero is a valid
1683 offset (that's where %rbp is supposed to be stored).
1684 The values start out as being offsets, and are later converted to
1685 addresses (at which point -1 is interpreted as an address, still meaning
1687 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1688 cache
->saved_regs
[i
] = -1;
1689 cache
->saved_sp
= 0;
1690 cache
->saved_sp_reg
= -1;
1692 /* Frameless until proven otherwise. */
1693 cache
->frameless_p
= 1;
1696 /* Allocate and initialize a frame cache. */
1698 static struct amd64_frame_cache
*
1699 amd64_alloc_frame_cache (void)
1701 struct amd64_frame_cache
*cache
;
1703 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1704 amd64_init_frame_cache (cache
);
1708 /* GCC 4.4 and later, can put code in the prologue to realign the
1709 stack pointer. Check whether PC points to such code, and update
1710 CACHE accordingly. Return the first instruction after the code
1711 sequence or CURRENT_PC, whichever is smaller. If we don't
1712 recognize the code, return PC. */
1715 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1716 struct amd64_frame_cache
*cache
)
1718 /* There are 2 code sequences to re-align stack before the frame
1721 1. Use a caller-saved saved register:
1727 2. Use a callee-saved saved register:
1734 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1736 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1737 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1742 int offset
, offset_and
;
1744 if (target_read_memory (pc
, buf
, sizeof buf
))
1747 /* Check caller-saved saved register. The first instruction has
1748 to be "leaq 8(%rsp), %reg". */
1749 if ((buf
[0] & 0xfb) == 0x48
1754 /* MOD must be binary 10 and R/M must be binary 100. */
1755 if ((buf
[2] & 0xc7) != 0x44)
1758 /* REG has register number. */
1759 reg
= (buf
[2] >> 3) & 7;
1761 /* Check the REX.R bit. */
1769 /* Check callee-saved saved register. The first instruction
1770 has to be "pushq %reg". */
1772 if ((buf
[0] & 0xf8) == 0x50)
1774 else if ((buf
[0] & 0xf6) == 0x40
1775 && (buf
[1] & 0xf8) == 0x50)
1777 /* Check the REX.B bit. */
1778 if ((buf
[0] & 1) != 0)
1787 reg
+= buf
[offset
] & 0x7;
1791 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1792 if ((buf
[offset
] & 0xfb) != 0x48
1793 || buf
[offset
+ 1] != 0x8d
1794 || buf
[offset
+ 3] != 0x24
1795 || buf
[offset
+ 4] != 0x10)
1798 /* MOD must be binary 10 and R/M must be binary 100. */
1799 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
1802 /* REG has register number. */
1803 r
= (buf
[offset
+ 2] >> 3) & 7;
1805 /* Check the REX.R bit. */
1806 if (buf
[offset
] == 0x4c)
1809 /* Registers in pushq and leaq have to be the same. */
1816 /* Rigister can't be %rsp nor %rbp. */
1817 if (reg
== 4 || reg
== 5)
1820 /* The next instruction has to be "andq $-XXX, %rsp". */
1821 if (buf
[offset
] != 0x48
1822 || buf
[offset
+ 2] != 0xe4
1823 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
1826 offset_and
= offset
;
1827 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
1829 /* The next instruction has to be "pushq -8(%reg)". */
1831 if (buf
[offset
] == 0xff)
1833 else if ((buf
[offset
] & 0xf6) == 0x40
1834 && buf
[offset
+ 1] == 0xff)
1836 /* Check the REX.B bit. */
1837 if ((buf
[offset
] & 0x1) != 0)
1844 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
1846 if (buf
[offset
+ 1] != 0xf8
1847 || (buf
[offset
] & 0xf8) != 0x70)
1850 /* R/M has register. */
1851 r
+= buf
[offset
] & 7;
1853 /* Registers in leaq and pushq have to be the same. */
1857 if (current_pc
> pc
+ offset_and
)
1858 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
1860 return min (pc
+ offset
+ 2, current_pc
);
1863 /* Do a limited analysis of the prologue at PC and update CACHE
1864 accordingly. Bail out early if CURRENT_PC is reached. Return the
1865 address where the analysis stopped.
1867 We will handle only functions beginning with:
1870 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
1872 or (for the X32 ABI):
1875 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
1877 Any function that doesn't start with one of these sequences will be
1878 assumed to have no prologue and thus no valid frame pointer in
1882 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
1883 CORE_ADDR pc
, CORE_ADDR current_pc
,
1884 struct amd64_frame_cache
*cache
)
1886 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1887 /* There are two variations of movq %rsp, %rbp. */
1888 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
1889 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
1890 /* Ditto for movl %esp, %ebp. */
1891 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
1892 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
1897 if (current_pc
<= pc
)
1900 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
1902 op
= read_memory_unsigned_integer (pc
, 1, byte_order
);
1904 if (op
== 0x55) /* pushq %rbp */
1906 /* Take into account that we've executed the `pushq %rbp' that
1907 starts this instruction sequence. */
1908 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
1909 cache
->sp_offset
+= 8;
1911 /* If that's all, return now. */
1912 if (current_pc
<= pc
+ 1)
1915 read_memory (pc
+ 1, buf
, 3);
1917 /* Check for `movq %rsp, %rbp'. */
1918 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
1919 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
1921 /* OK, we actually have a frame. */
1922 cache
->frameless_p
= 0;
1926 /* For X32, also check for `movq %esp, %ebp'. */
1927 if (gdbarch_ptr_bit (gdbarch
) == 32)
1929 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
1930 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
1932 /* OK, we actually have a frame. */
1933 cache
->frameless_p
= 0;
1944 /* Work around false termination of prologue - GCC PR debug/48827.
1946 START_PC is the first instruction of a function, PC is its minimal already
1947 determined advanced address. Function returns PC if it has nothing to do.
1951 <-- here is 0 lines advance - the false prologue end marker.
1952 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
1953 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
1954 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
1955 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
1956 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
1957 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
1958 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
1959 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
1963 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
1965 struct symtab_and_line start_pc_sal
, next_sal
;
1966 gdb_byte buf
[4 + 8 * 7];
1972 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
1973 if (start_pc_sal
.symtab
== NULL
1974 || producer_is_gcc_ge_4 (start_pc_sal
.symtab
->producer
) < 6
1975 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
1978 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
1979 if (next_sal
.line
!= start_pc_sal
.line
)
1982 /* START_PC can be from overlayed memory, ignored here. */
1983 if (target_read_memory (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
1987 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
1994 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
1996 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
1997 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
1998 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2002 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2004 /* 8-bit displacement. */
2008 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2010 /* 32-bit displacement. */
2018 if (offset
- 4 != buf
[3])
2021 return next_sal
.end
;
2024 /* Return PC of first real instruction. */
2027 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2029 struct amd64_frame_cache cache
;
2032 amd64_init_frame_cache (&cache
);
2033 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2035 if (cache
.frameless_p
)
2038 return amd64_skip_xmm_prologue (pc
, start_pc
);
2042 /* Normal frames. */
2045 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2046 struct amd64_frame_cache
*cache
)
2048 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2049 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2053 cache
->pc
= get_frame_func (this_frame
);
2055 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2058 if (cache
->frameless_p
)
2060 /* We didn't find a valid frame. If we're at the start of a
2061 function, or somewhere half-way its prologue, the function's
2062 frame probably hasn't been fully setup yet. Try to
2063 reconstruct the base address for the stack frame by looking
2064 at the stack pointer. For truly "frameless" functions this
2067 if (cache
->saved_sp_reg
!= -1)
2069 /* Stack pointer has been saved. */
2070 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2071 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2073 /* We're halfway aligning the stack. */
2074 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2075 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2077 /* This will be added back below. */
2078 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2082 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2083 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2089 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2090 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2093 /* Now that we have the base address for the stack frame we can
2094 calculate the value of %rsp in the calling frame. */
2095 cache
->saved_sp
= cache
->base
+ 16;
2097 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2098 frame we find it at the same offset from the reconstructed base
2099 address. If we're halfway aligning the stack, %rip is handled
2100 differently (see above). */
2101 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2102 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2104 /* Adjust all the saved registers such that they contain addresses
2105 instead of offsets. */
2106 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2107 if (cache
->saved_regs
[i
] != -1)
2108 cache
->saved_regs
[i
] += cache
->base
;
2113 static struct amd64_frame_cache
*
2114 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2116 volatile struct gdb_exception ex
;
2117 struct amd64_frame_cache
*cache
;
2122 cache
= amd64_alloc_frame_cache ();
2123 *this_cache
= cache
;
2125 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2127 amd64_frame_cache_1 (this_frame
, cache
);
2129 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2130 throw_exception (ex
);
2135 static enum unwind_stop_reason
2136 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2139 struct amd64_frame_cache
*cache
=
2140 amd64_frame_cache (this_frame
, this_cache
);
2143 return UNWIND_UNAVAILABLE
;
2145 /* This marks the outermost frame. */
2146 if (cache
->base
== 0)
2147 return UNWIND_OUTERMOST
;
2149 return UNWIND_NO_REASON
;
2153 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2154 struct frame_id
*this_id
)
2156 struct amd64_frame_cache
*cache
=
2157 amd64_frame_cache (this_frame
, this_cache
);
2162 /* This marks the outermost frame. */
2163 if (cache
->base
== 0)
2166 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2169 static struct value
*
2170 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2173 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2174 struct amd64_frame_cache
*cache
=
2175 amd64_frame_cache (this_frame
, this_cache
);
2177 gdb_assert (regnum
>= 0);
2179 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2180 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2182 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2183 return frame_unwind_got_memory (this_frame
, regnum
,
2184 cache
->saved_regs
[regnum
]);
2186 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2189 static const struct frame_unwind amd64_frame_unwind
=
2192 amd64_frame_unwind_stop_reason
,
2193 amd64_frame_this_id
,
2194 amd64_frame_prev_register
,
2196 default_frame_sniffer
2199 /* Generate a bytecode expression to get the value of the saved PC. */
2202 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2203 struct agent_expr
*ax
, struct axs_value
*value
,
2206 /* The following sequence assumes the traditional use of the base
2208 ax_reg (ax
, AMD64_RBP_REGNUM
);
2210 ax_simple (ax
, aop_add
);
2211 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2212 value
->kind
= axs_lvalue_memory
;
2216 /* Signal trampolines. */
2218 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2219 64-bit variants. This would require using identical frame caches
2220 on both platforms. */
2222 static struct amd64_frame_cache
*
2223 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2225 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2226 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2227 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2228 volatile struct gdb_exception ex
;
2229 struct amd64_frame_cache
*cache
;
2237 cache
= amd64_alloc_frame_cache ();
2239 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2241 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2242 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2244 addr
= tdep
->sigcontext_addr (this_frame
);
2245 gdb_assert (tdep
->sc_reg_offset
);
2246 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2247 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2248 if (tdep
->sc_reg_offset
[i
] != -1)
2249 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2253 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2254 throw_exception (ex
);
2256 *this_cache
= cache
;
2260 static enum unwind_stop_reason
2261 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2264 struct amd64_frame_cache
*cache
=
2265 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2268 return UNWIND_UNAVAILABLE
;
2270 return UNWIND_NO_REASON
;
2274 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2275 void **this_cache
, struct frame_id
*this_id
)
2277 struct amd64_frame_cache
*cache
=
2278 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2283 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2286 static struct value
*
2287 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2288 void **this_cache
, int regnum
)
2290 /* Make sure we've initialized the cache. */
2291 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2293 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2297 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2298 struct frame_info
*this_frame
,
2301 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2303 /* We shouldn't even bother if we don't have a sigcontext_addr
2305 if (tdep
->sigcontext_addr
== NULL
)
2308 if (tdep
->sigtramp_p
!= NULL
)
2310 if (tdep
->sigtramp_p (this_frame
))
2314 if (tdep
->sigtramp_start
!= 0)
2316 CORE_ADDR pc
= get_frame_pc (this_frame
);
2318 gdb_assert (tdep
->sigtramp_end
!= 0);
2319 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2326 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2329 amd64_sigtramp_frame_unwind_stop_reason
,
2330 amd64_sigtramp_frame_this_id
,
2331 amd64_sigtramp_frame_prev_register
,
2333 amd64_sigtramp_frame_sniffer
2338 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2340 struct amd64_frame_cache
*cache
=
2341 amd64_frame_cache (this_frame
, this_cache
);
2346 static const struct frame_base amd64_frame_base
=
2348 &amd64_frame_unwind
,
2349 amd64_frame_base_address
,
2350 amd64_frame_base_address
,
2351 amd64_frame_base_address
2354 /* Normal frames, but in a function epilogue. */
2356 /* The epilogue is defined here as the 'ret' instruction, which will
2357 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2358 the function's stack frame. */
2361 amd64_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2364 struct symtab
*symtab
;
2366 symtab
= find_pc_symtab (pc
);
2367 if (symtab
&& symtab
->epilogue_unwind_valid
)
2370 if (target_read_memory (pc
, &insn
, 1))
2371 return 0; /* Can't read memory at pc. */
2373 if (insn
!= 0xc3) /* 'ret' instruction. */
2380 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2381 struct frame_info
*this_frame
,
2382 void **this_prologue_cache
)
2384 if (frame_relative_level (this_frame
) == 0)
2385 return amd64_in_function_epilogue_p (get_frame_arch (this_frame
),
2386 get_frame_pc (this_frame
));
2391 static struct amd64_frame_cache
*
2392 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2394 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2395 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2396 volatile struct gdb_exception ex
;
2397 struct amd64_frame_cache
*cache
;
2403 cache
= amd64_alloc_frame_cache ();
2404 *this_cache
= cache
;
2406 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2408 /* Cache base will be %esp plus cache->sp_offset (-8). */
2409 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2410 cache
->base
= extract_unsigned_integer (buf
, 8,
2411 byte_order
) + cache
->sp_offset
;
2413 /* Cache pc will be the frame func. */
2414 cache
->pc
= get_frame_pc (this_frame
);
2416 /* The saved %esp will be at cache->base plus 16. */
2417 cache
->saved_sp
= cache
->base
+ 16;
2419 /* The saved %eip will be at cache->base plus 8. */
2420 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2424 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2425 throw_exception (ex
);
2430 static enum unwind_stop_reason
2431 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2434 struct amd64_frame_cache
*cache
2435 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2438 return UNWIND_UNAVAILABLE
;
2440 return UNWIND_NO_REASON
;
2444 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2446 struct frame_id
*this_id
)
2448 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2454 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2457 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2460 amd64_epilogue_frame_unwind_stop_reason
,
2461 amd64_epilogue_frame_this_id
,
2462 amd64_frame_prev_register
,
2464 amd64_epilogue_frame_sniffer
2467 static struct frame_id
2468 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2472 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2474 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2477 /* 16 byte align the SP per frame requirements. */
2480 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2482 return sp
& -(CORE_ADDR
)16;
2486 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2487 in the floating-point register set REGSET to register cache
2488 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2491 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2492 int regnum
, const void *fpregs
, size_t len
)
2494 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2496 gdb_assert (len
== tdep
->sizeof_fpregset
);
2497 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
2500 /* Collect register REGNUM from the register cache REGCACHE and store
2501 it in the buffer specified by FPREGS and LEN as described by the
2502 floating-point register set REGSET. If REGNUM is -1, do this for
2503 all registers in REGSET. */
2506 amd64_collect_fpregset (const struct regset
*regset
,
2507 const struct regcache
*regcache
,
2508 int regnum
, void *fpregs
, size_t len
)
2510 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2512 gdb_assert (len
== tdep
->sizeof_fpregset
);
2513 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
2516 /* Similar to amd64_supply_fpregset, but use XSAVE extended state. */
2519 amd64_supply_xstateregset (const struct regset
*regset
,
2520 struct regcache
*regcache
, int regnum
,
2521 const void *xstateregs
, size_t len
)
2523 amd64_supply_xsave (regcache
, regnum
, xstateregs
);
2526 /* Similar to amd64_collect_fpregset, but use XSAVE extended state. */
2529 amd64_collect_xstateregset (const struct regset
*regset
,
2530 const struct regcache
*regcache
,
2531 int regnum
, void *xstateregs
, size_t len
)
2533 amd64_collect_xsave (regcache
, regnum
, xstateregs
, 1);
2536 /* Return the appropriate register set for the core section identified
2537 by SECT_NAME and SECT_SIZE. */
2539 static const struct regset
*
2540 amd64_regset_from_core_section (struct gdbarch
*gdbarch
,
2541 const char *sect_name
, size_t sect_size
)
2543 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2545 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2547 if (tdep
->fpregset
== NULL
)
2548 tdep
->fpregset
= regset_alloc (gdbarch
, amd64_supply_fpregset
,
2549 amd64_collect_fpregset
);
2551 return tdep
->fpregset
;
2554 if (strcmp (sect_name
, ".reg-xstate") == 0)
2556 if (tdep
->xstateregset
== NULL
)
2557 tdep
->xstateregset
= regset_alloc (gdbarch
,
2558 amd64_supply_xstateregset
,
2559 amd64_collect_xstateregset
);
2561 return tdep
->xstateregset
;
2564 return i386_regset_from_core_section (gdbarch
, sect_name
, sect_size
);
2568 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2569 %rdi. We expect its value to be a pointer to the jmp_buf structure
2570 from which we extract the address that we will land at. This
2571 address is copied into PC. This routine returns non-zero on
2575 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2579 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2580 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2581 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
2583 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2584 longjmp will land. */
2585 if (jb_pc_offset
== -1)
2588 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
2589 jb_addr
= extract_typed_address
2590 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
2591 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
2594 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
2599 static const int amd64_record_regmap
[] =
2601 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
2602 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
2603 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
2604 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
2605 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
2606 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
2610 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2612 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2613 const struct target_desc
*tdesc
= info
.target_desc
;
2615 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2616 floating-point registers. */
2617 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
2619 if (! tdesc_has_registers (tdesc
))
2620 tdesc
= tdesc_amd64
;
2621 tdep
->tdesc
= tdesc
;
2623 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
2624 tdep
->register_names
= amd64_register_names
;
2626 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
2628 tdep
->ymmh_register_names
= amd64_ymmh_names
;
2629 tdep
->num_ymm_regs
= 16;
2630 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
2633 tdep
->num_byte_regs
= 20;
2634 tdep
->num_word_regs
= 16;
2635 tdep
->num_dword_regs
= 16;
2636 /* Avoid wiring in the MMX registers for now. */
2637 tdep
->num_mmx_regs
= 0;
2639 set_gdbarch_pseudo_register_read_value (gdbarch
,
2640 amd64_pseudo_register_read_value
);
2641 set_gdbarch_pseudo_register_write (gdbarch
,
2642 amd64_pseudo_register_write
);
2644 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
2646 /* AMD64 has an FPU and 16 SSE registers. */
2647 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
2648 tdep
->num_xmm_regs
= 16;
2650 /* This is what all the fuss is about. */
2651 set_gdbarch_long_bit (gdbarch
, 64);
2652 set_gdbarch_long_long_bit (gdbarch
, 64);
2653 set_gdbarch_ptr_bit (gdbarch
, 64);
2655 /* In contrast to the i386, on AMD64 a `long double' actually takes
2656 up 128 bits, even though it's still based on the i387 extended
2657 floating-point format which has only 80 significant bits. */
2658 set_gdbarch_long_double_bit (gdbarch
, 128);
2660 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
2662 /* Register numbers of various important registers. */
2663 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
2664 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
2665 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
2666 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
2668 /* The "default" register numbering scheme for AMD64 is referred to
2669 as the "DWARF Register Number Mapping" in the System V psABI.
2670 The preferred debugging format for all known AMD64 targets is
2671 actually DWARF2, and GCC doesn't seem to support DWARF (that is
2672 DWARF-1), but we provide the same mapping just in case. This
2673 mapping is also used for stabs, which GCC does support. */
2674 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
2675 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
2677 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
2678 be in use on any of the supported AMD64 targets. */
2680 /* Call dummy code. */
2681 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
2682 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
2683 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
2684 tdep
->call_dummy_num_integer_regs
=
2685 ARRAY_SIZE (amd64_dummy_call_integer_regs
);
2686 tdep
->call_dummy_integer_regs
= amd64_dummy_call_integer_regs
;
2687 tdep
->classify
= amd64_classify
;
2689 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
2690 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
2691 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
2693 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
2695 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
2697 tdep
->record_regmap
= amd64_record_regmap
;
2699 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
2701 /* Hook the function epilogue frame unwinder. This unwinder is
2702 appended to the list first, so that it supercedes the other
2703 unwinders in function epilogues. */
2704 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
2706 /* Hook the prologue-based frame unwinders. */
2707 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
2708 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
2709 frame_base_set_default (gdbarch
, &amd64_frame_base
);
2711 /* If we have a register mapping, enable the generic core file support. */
2712 if (tdep
->gregset_reg_offset
)
2713 set_gdbarch_regset_from_core_section (gdbarch
,
2714 amd64_regset_from_core_section
);
2716 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
2718 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
2720 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
2722 /* SystemTap variables and functions. */
2723 set_gdbarch_stap_integer_prefix (gdbarch
, "$");
2724 set_gdbarch_stap_register_prefix (gdbarch
, "%");
2725 set_gdbarch_stap_register_indirection_prefix (gdbarch
, "(");
2726 set_gdbarch_stap_register_indirection_suffix (gdbarch
, ")");
2727 set_gdbarch_stap_is_single_operand (gdbarch
,
2728 i386_stap_is_single_operand
);
2729 set_gdbarch_stap_parse_special_token (gdbarch
,
2730 i386_stap_parse_special_token
);
2733 /* Provide a prototype to silence -Wmissing-prototypes. */
2734 void _initialize_amd64_tdep (void);
2737 _initialize_amd64_tdep (void)
2739 initialize_tdesc_amd64 ();
2740 initialize_tdesc_amd64_avx ();
2741 initialize_tdesc_x32 ();
2742 initialize_tdesc_x32_avx ();
2746 /* The 64-bit FXSAVE format differs from the 32-bit format in the
2747 sense that the instruction pointer and data pointer are simply
2748 64-bit offsets into the code segment and the data segment instead
2749 of a selector offset pair. The functions below store the upper 32
2750 bits of these pointers (instead of just the 16-bits of the segment
2753 /* Fill register REGNUM in REGCACHE with the appropriate
2754 floating-point or SSE register value from *FXSAVE. If REGNUM is
2755 -1, do this for all registers. This function masks off any of the
2756 reserved bits in *FXSAVE. */
2759 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
2762 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2763 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2765 i387_supply_fxsave (regcache
, regnum
, fxsave
);
2767 if (fxsave
&& gdbarch_ptr_bit (gdbarch
) == 64)
2769 const gdb_byte
*regs
= fxsave
;
2771 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
2772 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
2773 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
2774 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
2778 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
2781 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
2784 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2785 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2787 i387_supply_xsave (regcache
, regnum
, xsave
);
2789 if (xsave
&& gdbarch_ptr_bit (gdbarch
) == 64)
2791 const gdb_byte
*regs
= xsave
;
2793 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
2794 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
),
2796 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
2797 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
),
2802 /* Fill register REGNUM (if it is a floating-point or SSE register) in
2803 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
2804 all registers. This function doesn't touch any of the reserved
2808 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
2811 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2812 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2813 gdb_byte
*regs
= fxsave
;
2815 i387_collect_fxsave (regcache
, regnum
, fxsave
);
2817 if (gdbarch_ptr_bit (gdbarch
) == 64)
2819 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
2820 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
2821 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
2822 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
2826 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
2829 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
2830 void *xsave
, int gcore
)
2832 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2833 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2834 gdb_byte
*regs
= xsave
;
2836 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
2838 if (gdbarch_ptr_bit (gdbarch
) == 64)
2840 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
2841 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
),
2843 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
2844 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
),