1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2017 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "x86-xstate.h"
44 #include "target-descriptions.h"
45 #include "arch/amd64.h"
50 /* Note that the AMD64 architecture was previously known as x86-64.
51 The latter is (forever) engraved into the canonical system name as
52 returned by config.guess, and used as the name for the AMD64 port
53 of GNU/Linux. The BSD's have renamed their ports to amd64; they
54 don't like to shout. For GDB we prefer the amd64_-prefix over the
55 x86_64_-prefix since it's so much easier to type. */
57 /* Register information. */
59 static const char *amd64_register_names
[] =
61 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
63 /* %r8 is indeed register number 8. */
64 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
65 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
67 /* %st0 is register number 24. */
68 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
69 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
71 /* %xmm0 is register number 40. */
72 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
73 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
77 static const char *amd64_ymm_names
[] =
79 "ymm0", "ymm1", "ymm2", "ymm3",
80 "ymm4", "ymm5", "ymm6", "ymm7",
81 "ymm8", "ymm9", "ymm10", "ymm11",
82 "ymm12", "ymm13", "ymm14", "ymm15"
85 static const char *amd64_ymm_avx512_names
[] =
87 "ymm16", "ymm17", "ymm18", "ymm19",
88 "ymm20", "ymm21", "ymm22", "ymm23",
89 "ymm24", "ymm25", "ymm26", "ymm27",
90 "ymm28", "ymm29", "ymm30", "ymm31"
93 static const char *amd64_ymmh_names
[] =
95 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
96 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
97 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
98 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
101 static const char *amd64_ymmh_avx512_names
[] =
103 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
104 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
105 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
106 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
109 static const char *amd64_mpx_names
[] =
111 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
114 static const char *amd64_k_names
[] =
116 "k0", "k1", "k2", "k3",
117 "k4", "k5", "k6", "k7"
120 static const char *amd64_zmmh_names
[] =
122 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
123 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
124 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
125 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
126 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
127 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
128 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
129 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
132 static const char *amd64_zmm_names
[] =
134 "zmm0", "zmm1", "zmm2", "zmm3",
135 "zmm4", "zmm5", "zmm6", "zmm7",
136 "zmm8", "zmm9", "zmm10", "zmm11",
137 "zmm12", "zmm13", "zmm14", "zmm15",
138 "zmm16", "zmm17", "zmm18", "zmm19",
139 "zmm20", "zmm21", "zmm22", "zmm23",
140 "zmm24", "zmm25", "zmm26", "zmm27",
141 "zmm28", "zmm29", "zmm30", "zmm31"
144 static const char *amd64_xmm_avx512_names
[] = {
145 "xmm16", "xmm17", "xmm18", "xmm19",
146 "xmm20", "xmm21", "xmm22", "xmm23",
147 "xmm24", "xmm25", "xmm26", "xmm27",
148 "xmm28", "xmm29", "xmm30", "xmm31"
151 static const char *amd64_pkeys_names
[] = {
155 /* DWARF Register Number Mapping as defined in the System V psABI,
158 static int amd64_dwarf_regmap
[] =
160 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
161 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
162 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
163 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
165 /* Frame Pointer Register RBP. */
168 /* Stack Pointer Register RSP. */
171 /* Extended Integer Registers 8 - 15. */
172 AMD64_R8_REGNUM
, /* %r8 */
173 AMD64_R9_REGNUM
, /* %r9 */
174 AMD64_R10_REGNUM
, /* %r10 */
175 AMD64_R11_REGNUM
, /* %r11 */
176 AMD64_R12_REGNUM
, /* %r12 */
177 AMD64_R13_REGNUM
, /* %r13 */
178 AMD64_R14_REGNUM
, /* %r14 */
179 AMD64_R15_REGNUM
, /* %r15 */
181 /* Return Address RA. Mapped to RIP. */
184 /* SSE Registers 0 - 7. */
185 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
186 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
187 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
188 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
190 /* Extended SSE Registers 8 - 15. */
191 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
192 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
193 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
194 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
196 /* Floating Point Registers 0-7. */
197 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
198 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
199 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
200 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
202 /* MMX Registers 0 - 7.
203 We have to handle those registers specifically, as their register
204 number within GDB depends on the target (or they may even not be
205 available at all). */
206 -1, -1, -1, -1, -1, -1, -1, -1,
208 /* Control and Status Flags Register. */
211 /* Selector Registers. */
221 /* Segment Base Address Registers. */
227 /* Special Selector Registers. */
231 /* Floating Point Control Registers. */
237 static const int amd64_dwarf_regmap_len
=
238 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
240 /* Convert DWARF register number REG to the appropriate register
241 number used by GDB. */
244 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
246 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
247 int ymm0_regnum
= tdep
->ymm0_regnum
;
250 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
251 regnum
= amd64_dwarf_regmap
[reg
];
254 && i386_xmm_regnum_p (gdbarch
, regnum
))
255 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
260 /* Map architectural register numbers to gdb register numbers. */
262 static const int amd64_arch_regmap
[16] =
264 AMD64_RAX_REGNUM
, /* %rax */
265 AMD64_RCX_REGNUM
, /* %rcx */
266 AMD64_RDX_REGNUM
, /* %rdx */
267 AMD64_RBX_REGNUM
, /* %rbx */
268 AMD64_RSP_REGNUM
, /* %rsp */
269 AMD64_RBP_REGNUM
, /* %rbp */
270 AMD64_RSI_REGNUM
, /* %rsi */
271 AMD64_RDI_REGNUM
, /* %rdi */
272 AMD64_R8_REGNUM
, /* %r8 */
273 AMD64_R9_REGNUM
, /* %r9 */
274 AMD64_R10_REGNUM
, /* %r10 */
275 AMD64_R11_REGNUM
, /* %r11 */
276 AMD64_R12_REGNUM
, /* %r12 */
277 AMD64_R13_REGNUM
, /* %r13 */
278 AMD64_R14_REGNUM
, /* %r14 */
279 AMD64_R15_REGNUM
/* %r15 */
282 static const int amd64_arch_regmap_len
=
283 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
285 /* Convert architectural register number REG to the appropriate register
286 number used by GDB. */
289 amd64_arch_reg_to_regnum (int reg
)
291 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
293 return amd64_arch_regmap
[reg
];
296 /* Register names for byte pseudo-registers. */
298 static const char *amd64_byte_names
[] =
300 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
301 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
302 "ah", "bh", "ch", "dh"
305 /* Number of lower byte registers. */
306 #define AMD64_NUM_LOWER_BYTE_REGS 16
308 /* Register names for word pseudo-registers. */
310 static const char *amd64_word_names
[] =
312 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
313 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
316 /* Register names for dword pseudo-registers. */
318 static const char *amd64_dword_names
[] =
320 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
321 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
325 /* Return the name of register REGNUM. */
328 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
330 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
331 if (i386_byte_regnum_p (gdbarch
, regnum
))
332 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
333 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
334 return amd64_zmm_names
[regnum
- tdep
->zmm0_regnum
];
335 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
336 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
337 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
338 return amd64_ymm_avx512_names
[regnum
- tdep
->ymm16_regnum
];
339 else if (i386_word_regnum_p (gdbarch
, regnum
))
340 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
341 else if (i386_dword_regnum_p (gdbarch
, regnum
))
342 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
344 return i386_pseudo_register_name (gdbarch
, regnum
);
347 static struct value
*
348 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
349 struct regcache
*regcache
,
352 gdb_byte
*raw_buf
= (gdb_byte
*) alloca (register_size (gdbarch
, regnum
));
353 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
354 enum register_status status
;
355 struct value
*result_value
;
358 result_value
= allocate_value (register_type (gdbarch
, regnum
));
359 VALUE_LVAL (result_value
) = lval_register
;
360 VALUE_REGNUM (result_value
) = regnum
;
361 buf
= value_contents_raw (result_value
);
363 if (i386_byte_regnum_p (gdbarch
, regnum
))
365 int gpnum
= regnum
- tdep
->al_regnum
;
367 /* Extract (always little endian). */
368 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
370 /* Special handling for AH, BH, CH, DH. */
371 status
= regcache_raw_read (regcache
,
372 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
,
374 if (status
== REG_VALID
)
375 memcpy (buf
, raw_buf
+ 1, 1);
377 mark_value_bytes_unavailable (result_value
, 0,
378 TYPE_LENGTH (value_type (result_value
)));
382 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
383 if (status
== REG_VALID
)
384 memcpy (buf
, raw_buf
, 1);
386 mark_value_bytes_unavailable (result_value
, 0,
387 TYPE_LENGTH (value_type (result_value
)));
390 else if (i386_dword_regnum_p (gdbarch
, regnum
))
392 int gpnum
= regnum
- tdep
->eax_regnum
;
393 /* Extract (always little endian). */
394 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
395 if (status
== REG_VALID
)
396 memcpy (buf
, raw_buf
, 4);
398 mark_value_bytes_unavailable (result_value
, 0,
399 TYPE_LENGTH (value_type (result_value
)));
402 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
409 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
410 struct regcache
*regcache
,
411 int regnum
, const gdb_byte
*buf
)
413 gdb_byte
*raw_buf
= (gdb_byte
*) alloca (register_size (gdbarch
, regnum
));
414 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
416 if (i386_byte_regnum_p (gdbarch
, regnum
))
418 int gpnum
= regnum
- tdep
->al_regnum
;
420 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
422 /* Read ... AH, BH, CH, DH. */
423 regcache_raw_read (regcache
,
424 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
425 /* ... Modify ... (always little endian). */
426 memcpy (raw_buf
+ 1, buf
, 1);
428 regcache_raw_write (regcache
,
429 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
434 regcache_raw_read (regcache
, gpnum
, raw_buf
);
435 /* ... Modify ... (always little endian). */
436 memcpy (raw_buf
, buf
, 1);
438 regcache_raw_write (regcache
, gpnum
, raw_buf
);
441 else if (i386_dword_regnum_p (gdbarch
, regnum
))
443 int gpnum
= regnum
- tdep
->eax_regnum
;
446 regcache_raw_read (regcache
, gpnum
, raw_buf
);
447 /* ... Modify ... (always little endian). */
448 memcpy (raw_buf
, buf
, 4);
450 regcache_raw_write (regcache
, gpnum
, raw_buf
);
453 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
456 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
459 amd64_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
460 struct agent_expr
*ax
, int regnum
)
462 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
464 if (i386_byte_regnum_p (gdbarch
, regnum
))
466 int gpnum
= regnum
- tdep
->al_regnum
;
468 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
469 ax_reg_mask (ax
, gpnum
- AMD64_NUM_LOWER_BYTE_REGS
);
471 ax_reg_mask (ax
, gpnum
);
474 else if (i386_dword_regnum_p (gdbarch
, regnum
))
476 int gpnum
= regnum
- tdep
->eax_regnum
;
478 ax_reg_mask (ax
, gpnum
);
482 return i386_ax_pseudo_register_collect (gdbarch
, ax
, regnum
);
487 /* Register classes as defined in the psABI. */
501 /* Return the union class of CLASS1 and CLASS2. See the psABI for
504 static enum amd64_reg_class
505 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
507 /* Rule (a): If both classes are equal, this is the resulting class. */
508 if (class1
== class2
)
511 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
512 is the other class. */
513 if (class1
== AMD64_NO_CLASS
)
515 if (class2
== AMD64_NO_CLASS
)
518 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
519 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
522 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
523 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
524 return AMD64_INTEGER
;
526 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
527 MEMORY is used as class. */
528 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
529 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
530 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
533 /* Rule (f): Otherwise class SSE is used. */
537 static void amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2]);
539 /* Return non-zero if TYPE is a non-POD structure or union type. */
542 amd64_non_pod_p (struct type
*type
)
544 /* ??? A class with a base class certainly isn't POD, but does this
545 catch all non-POD structure types? */
546 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
552 /* Classify TYPE according to the rules for aggregate (structures and
553 arrays) and union types, and store the result in CLASS. */
556 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class theclass
[2])
558 /* 1. If the size of an object is larger than two eightbytes, or in
559 C++, is a non-POD structure or union type, or contains
560 unaligned fields, it has class memory. */
561 if (TYPE_LENGTH (type
) > 16 || amd64_non_pod_p (type
))
563 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
567 /* 2. Both eightbytes get initialized to class NO_CLASS. */
568 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
570 /* 3. Each field of an object is classified recursively so that
571 always two fields are considered. The resulting class is
572 calculated according to the classes of the fields in the
575 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
577 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
579 /* All fields in an array have the same type. */
580 amd64_classify (subtype
, theclass
);
581 if (TYPE_LENGTH (type
) > 8 && theclass
[1] == AMD64_NO_CLASS
)
582 theclass
[1] = theclass
[0];
588 /* Structure or union. */
589 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
590 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
592 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
594 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
595 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
596 enum amd64_reg_class subclass
[2];
597 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
601 bitsize
= TYPE_LENGTH (subtype
) * 8;
602 endpos
= (TYPE_FIELD_BITPOS (type
, i
) + bitsize
- 1) / 64;
604 /* Ignore static fields. */
605 if (field_is_static (&TYPE_FIELD (type
, i
)))
608 gdb_assert (pos
== 0 || pos
== 1);
610 amd64_classify (subtype
, subclass
);
611 theclass
[pos
] = amd64_merge_classes (theclass
[pos
], subclass
[0]);
612 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
613 /* This is a bit of an odd case: We have a field that would
614 normally fit in one of the two eightbytes, except that
615 it is placed in a way that this field straddles them.
616 This has been seen with a structure containing an array.
618 The ABI is a bit unclear in this case, but we assume that
619 this field's class (stored in subclass[0]) must also be merged
620 into class[1]. In other words, our field has a piece stored
621 in the second eight-byte, and thus its class applies to
622 the second eight-byte as well.
624 In the case where the field length exceeds 8 bytes,
625 it should not be necessary to merge the field class
626 into class[1]. As LEN > 8, subclass[1] is necessarily
627 different from AMD64_NO_CLASS. If subclass[1] is equal
628 to subclass[0], then the normal class[1]/subclass[1]
629 merging will take care of everything. For subclass[1]
630 to be different from subclass[0], I can only see the case
631 where we have a SSE/SSEUP or X87/X87UP pair, which both
632 use up all 16 bytes of the aggregate, and are already
633 handled just fine (because each portion sits on its own
635 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[0]);
637 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[1]);
641 /* 4. Then a post merger cleanup is done: */
643 /* Rule (a): If one of the classes is MEMORY, the whole argument is
645 if (theclass
[0] == AMD64_MEMORY
|| theclass
[1] == AMD64_MEMORY
)
646 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
648 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
650 if (theclass
[0] == AMD64_SSEUP
)
651 theclass
[0] = AMD64_SSE
;
652 if (theclass
[1] == AMD64_SSEUP
&& theclass
[0] != AMD64_SSE
)
653 theclass
[1] = AMD64_SSE
;
656 /* Classify TYPE, and store the result in CLASS. */
659 amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2])
661 enum type_code code
= TYPE_CODE (type
);
662 int len
= TYPE_LENGTH (type
);
664 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
666 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
667 long, long long, and pointers are in the INTEGER class. Similarly,
668 range types, used by languages such as Ada, are also in the INTEGER
670 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
671 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
672 || code
== TYPE_CODE_CHAR
673 || code
== TYPE_CODE_PTR
|| TYPE_IS_REFERENCE (type
))
674 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
675 theclass
[0] = AMD64_INTEGER
;
677 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
679 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
680 && (len
== 4 || len
== 8))
682 theclass
[0] = AMD64_SSE
;
684 /* Arguments of types __float128, _Decimal128 and __m128 are split into
685 two halves. The least significant ones belong to class SSE, the most
686 significant one to class SSEUP. */
687 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
688 /* FIXME: __float128, __m128. */
689 theclass
[0] = AMD64_SSE
, theclass
[1] = AMD64_SSEUP
;
691 /* The 64-bit mantissa of arguments of type long double belongs to
692 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
694 else if (code
== TYPE_CODE_FLT
&& len
== 16)
695 /* Class X87 and X87UP. */
696 theclass
[0] = AMD64_X87
, theclass
[1] = AMD64_X87UP
;
698 /* Arguments of complex T where T is one of the types float or
699 double get treated as if they are implemented as:
707 else if (code
== TYPE_CODE_COMPLEX
&& len
== 8)
708 theclass
[0] = AMD64_SSE
;
709 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
710 theclass
[0] = theclass
[1] = AMD64_SSE
;
712 /* A variable of type complex long double is classified as type
714 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
715 theclass
[0] = AMD64_COMPLEX_X87
;
718 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
719 || code
== TYPE_CODE_UNION
)
720 amd64_classify_aggregate (type
, theclass
);
723 static enum return_value_convention
724 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
725 struct type
*type
, struct regcache
*regcache
,
726 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
728 enum amd64_reg_class theclass
[2];
729 int len
= TYPE_LENGTH (type
);
730 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
731 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
736 gdb_assert (!(readbuf
&& writebuf
));
738 /* 1. Classify the return type with the classification algorithm. */
739 amd64_classify (type
, theclass
);
741 /* 2. If the type has class MEMORY, then the caller provides space
742 for the return value and passes the address of this storage in
743 %rdi as if it were the first argument to the function. In effect,
744 this address becomes a hidden first argument.
746 On return %rax will contain the address that has been passed in
747 by the caller in %rdi. */
748 if (theclass
[0] == AMD64_MEMORY
)
750 /* As indicated by the comment above, the ABI guarantees that we
751 can always find the return value just after the function has
758 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
759 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
762 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
765 /* 8. If the class is COMPLEX_X87, the real part of the value is
766 returned in %st0 and the imaginary part in %st1. */
767 if (theclass
[0] == AMD64_COMPLEX_X87
)
771 regcache_raw_read (regcache
, AMD64_ST0_REGNUM
, readbuf
);
772 regcache_raw_read (regcache
, AMD64_ST1_REGNUM
, readbuf
+ 16);
777 i387_return_value (gdbarch
, regcache
);
778 regcache_raw_write (regcache
, AMD64_ST0_REGNUM
, writebuf
);
779 regcache_raw_write (regcache
, AMD64_ST1_REGNUM
, writebuf
+ 16);
781 /* Fix up the tag word such that both %st(0) and %st(1) are
783 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
786 return RETURN_VALUE_REGISTER_CONVENTION
;
789 gdb_assert (theclass
[1] != AMD64_MEMORY
);
790 gdb_assert (len
<= 16);
792 for (i
= 0; len
> 0; i
++, len
-= 8)
800 /* 3. If the class is INTEGER, the next available register
801 of the sequence %rax, %rdx is used. */
802 regnum
= integer_regnum
[integer_reg
++];
806 /* 4. If the class is SSE, the next available SSE register
807 of the sequence %xmm0, %xmm1 is used. */
808 regnum
= sse_regnum
[sse_reg
++];
812 /* 5. If the class is SSEUP, the eightbyte is passed in the
813 upper half of the last used SSE register. */
814 gdb_assert (sse_reg
> 0);
815 regnum
= sse_regnum
[sse_reg
- 1];
820 /* 6. If the class is X87, the value is returned on the X87
821 stack in %st0 as 80-bit x87 number. */
822 regnum
= AMD64_ST0_REGNUM
;
824 i387_return_value (gdbarch
, regcache
);
828 /* 7. If the class is X87UP, the value is returned together
829 with the previous X87 value in %st0. */
830 gdb_assert (i
> 0 && theclass
[0] == AMD64_X87
);
831 regnum
= AMD64_ST0_REGNUM
;
840 gdb_assert (!"Unexpected register class.");
843 gdb_assert (regnum
!= -1);
846 regcache_raw_read_part (regcache
, regnum
, offset
, std::min (len
, 8),
849 regcache_raw_write_part (regcache
, regnum
, offset
, std::min (len
, 8),
853 return RETURN_VALUE_REGISTER_CONVENTION
;
858 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
859 struct value
**args
, CORE_ADDR sp
, int struct_return
)
861 static int integer_regnum
[] =
863 AMD64_RDI_REGNUM
, /* %rdi */
864 AMD64_RSI_REGNUM
, /* %rsi */
865 AMD64_RDX_REGNUM
, /* %rdx */
866 AMD64_RCX_REGNUM
, /* %rcx */
867 AMD64_R8_REGNUM
, /* %r8 */
868 AMD64_R9_REGNUM
/* %r9 */
870 static int sse_regnum
[] =
872 /* %xmm0 ... %xmm7 */
873 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
874 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
875 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
876 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
878 struct value
**stack_args
= XALLOCAVEC (struct value
*, nargs
);
879 int num_stack_args
= 0;
880 int num_elements
= 0;
886 /* Reserve a register for the "hidden" argument. */
890 for (i
= 0; i
< nargs
; i
++)
892 struct type
*type
= value_type (args
[i
]);
893 int len
= TYPE_LENGTH (type
);
894 enum amd64_reg_class theclass
[2];
895 int needed_integer_regs
= 0;
896 int needed_sse_regs
= 0;
899 /* Classify argument. */
900 amd64_classify (type
, theclass
);
902 /* Calculate the number of integer and SSE registers needed for
904 for (j
= 0; j
< 2; j
++)
906 if (theclass
[j
] == AMD64_INTEGER
)
907 needed_integer_regs
++;
908 else if (theclass
[j
] == AMD64_SSE
)
912 /* Check whether enough registers are available, and if the
913 argument should be passed in registers at all. */
914 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
915 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
916 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
918 /* The argument will be passed on the stack. */
919 num_elements
+= ((len
+ 7) / 8);
920 stack_args
[num_stack_args
++] = args
[i
];
924 /* The argument will be passed in registers. */
925 const gdb_byte
*valbuf
= value_contents (args
[i
]);
928 gdb_assert (len
<= 16);
930 for (j
= 0; len
> 0; j
++, len
-= 8)
938 regnum
= integer_regnum
[integer_reg
++];
942 regnum
= sse_regnum
[sse_reg
++];
946 gdb_assert (sse_reg
> 0);
947 regnum
= sse_regnum
[sse_reg
- 1];
952 gdb_assert (!"Unexpected register class.");
955 gdb_assert (regnum
!= -1);
956 memset (buf
, 0, sizeof buf
);
957 memcpy (buf
, valbuf
+ j
* 8, std::min (len
, 8));
958 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
963 /* Allocate space for the arguments on the stack. */
964 sp
-= num_elements
* 8;
966 /* The psABI says that "The end of the input argument area shall be
967 aligned on a 16 byte boundary." */
970 /* Write out the arguments to the stack. */
971 for (i
= 0; i
< num_stack_args
; i
++)
973 struct type
*type
= value_type (stack_args
[i
]);
974 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
975 int len
= TYPE_LENGTH (type
);
977 write_memory (sp
+ element
* 8, valbuf
, len
);
978 element
+= ((len
+ 7) / 8);
981 /* The psABI says that "For calls that may call functions that use
982 varargs or stdargs (prototype-less calls or calls to functions
983 containing ellipsis (...) in the declaration) %al is used as
984 hidden argument to specify the number of SSE registers used. */
985 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
990 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
991 struct regcache
*regcache
, CORE_ADDR bp_addr
,
992 int nargs
, struct value
**args
, CORE_ADDR sp
,
993 int struct_return
, CORE_ADDR struct_addr
)
995 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
998 /* BND registers can be in arbitrary values at the moment of the
999 inferior call. This can cause boundary violations that are not
1000 due to a real bug or even desired by the user. The best to be done
1001 is set the BND registers to allow access to the whole memory, INIT
1002 state, before pushing the inferior call. */
1003 i387_reset_bnd_regs (gdbarch
, regcache
);
1005 /* Pass arguments. */
1006 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, struct_return
);
1008 /* Pass "hidden" argument". */
1011 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
1012 regcache_cooked_write (regcache
, AMD64_RDI_REGNUM
, buf
);
1015 /* Store return address. */
1017 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
1018 write_memory (sp
, buf
, 8);
1020 /* Finally, update the stack pointer... */
1021 store_unsigned_integer (buf
, 8, byte_order
, sp
);
1022 regcache_cooked_write (regcache
, AMD64_RSP_REGNUM
, buf
);
1024 /* ...and fake a frame pointer. */
1025 regcache_cooked_write (regcache
, AMD64_RBP_REGNUM
, buf
);
1030 /* Displaced instruction handling. */
1032 /* A partially decoded instruction.
1033 This contains enough details for displaced stepping purposes. */
1037 /* The number of opcode bytes. */
1039 /* The offset of the rex prefix or -1 if not present. */
1041 /* The offset to the first opcode byte. */
1043 /* The offset to the modrm byte or -1 if not present. */
1046 /* The raw instruction. */
1050 struct displaced_step_closure
1052 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1057 /* Details of the instruction. */
1058 struct amd64_insn insn_details
;
1060 /* Amount of space allocated to insn_buf. */
1063 /* The possibly modified insn.
1064 This is a variable-length field. */
1065 gdb_byte insn_buf
[1];
1068 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1069 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1070 at which point delete these in favor of libopcodes' versions). */
1072 static const unsigned char onebyte_has_modrm
[256] = {
1073 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1074 /* ------------------------------- */
1075 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1076 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1077 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1078 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1079 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1080 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1081 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1082 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1083 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1084 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1085 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1086 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1087 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1088 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1089 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1090 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1091 /* ------------------------------- */
1092 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1095 static const unsigned char twobyte_has_modrm
[256] = {
1096 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1097 /* ------------------------------- */
1098 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1099 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1100 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1101 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1102 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1103 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1104 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1105 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1106 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1107 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1108 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1109 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1110 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1111 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1112 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1113 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1114 /* ------------------------------- */
1115 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1118 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1121 rex_prefix_p (gdb_byte pfx
)
1123 return REX_PREFIX_P (pfx
);
1126 /* Skip the legacy instruction prefixes in INSN.
1127 We assume INSN is properly sentineled so we don't have to worry
1128 about falling off the end of the buffer. */
1131 amd64_skip_prefixes (gdb_byte
*insn
)
1137 case DATA_PREFIX_OPCODE
:
1138 case ADDR_PREFIX_OPCODE
:
1139 case CS_PREFIX_OPCODE
:
1140 case DS_PREFIX_OPCODE
:
1141 case ES_PREFIX_OPCODE
:
1142 case FS_PREFIX_OPCODE
:
1143 case GS_PREFIX_OPCODE
:
1144 case SS_PREFIX_OPCODE
:
1145 case LOCK_PREFIX_OPCODE
:
1146 case REPE_PREFIX_OPCODE
:
1147 case REPNE_PREFIX_OPCODE
:
1159 /* Return an integer register (other than RSP) that is unused as an input
1161 In order to not require adding a rex prefix if the insn doesn't already
1162 have one, the result is restricted to RAX ... RDI, sans RSP.
1163 The register numbering of the result follows architecture ordering,
1167 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1169 /* 1 bit for each reg */
1170 int used_regs_mask
= 0;
1172 /* There can be at most 3 int regs used as inputs in an insn, and we have
1173 7 to choose from (RAX ... RDI, sans RSP).
1174 This allows us to take a conservative approach and keep things simple.
1175 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1176 that implicitly specify RAX. */
1179 used_regs_mask
|= 1 << EAX_REG_NUM
;
1180 /* Similarily avoid RDX, implicit operand in divides. */
1181 used_regs_mask
|= 1 << EDX_REG_NUM
;
1183 used_regs_mask
|= 1 << ESP_REG_NUM
;
1185 /* If the opcode is one byte long and there's no ModRM byte,
1186 assume the opcode specifies a register. */
1187 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1188 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1190 /* Mark used regs in the modrm/sib bytes. */
1191 if (details
->modrm_offset
!= -1)
1193 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1194 int mod
= MODRM_MOD_FIELD (modrm
);
1195 int reg
= MODRM_REG_FIELD (modrm
);
1196 int rm
= MODRM_RM_FIELD (modrm
);
1197 int have_sib
= mod
!= 3 && rm
== 4;
1199 /* Assume the reg field of the modrm byte specifies a register. */
1200 used_regs_mask
|= 1 << reg
;
1204 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1205 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1206 used_regs_mask
|= 1 << base
;
1207 used_regs_mask
|= 1 << idx
;
1211 used_regs_mask
|= 1 << rm
;
1215 gdb_assert (used_regs_mask
< 256);
1216 gdb_assert (used_regs_mask
!= 255);
1218 /* Finally, find a free reg. */
1222 for (i
= 0; i
< 8; ++i
)
1224 if (! (used_regs_mask
& (1 << i
)))
1228 /* We shouldn't get here. */
1229 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1233 /* Extract the details of INSN that we need. */
1236 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1238 gdb_byte
*start
= insn
;
1241 details
->raw_insn
= insn
;
1243 details
->opcode_len
= -1;
1244 details
->rex_offset
= -1;
1245 details
->opcode_offset
= -1;
1246 details
->modrm_offset
= -1;
1248 /* Skip legacy instruction prefixes. */
1249 insn
= amd64_skip_prefixes (insn
);
1251 /* Skip REX instruction prefix. */
1252 if (rex_prefix_p (*insn
))
1254 details
->rex_offset
= insn
- start
;
1258 details
->opcode_offset
= insn
- start
;
1260 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1262 /* Two or three-byte opcode. */
1264 need_modrm
= twobyte_has_modrm
[*insn
];
1266 /* Check for three-byte opcode. */
1276 details
->opcode_len
= 3;
1279 details
->opcode_len
= 2;
1285 /* One-byte opcode. */
1286 need_modrm
= onebyte_has_modrm
[*insn
];
1287 details
->opcode_len
= 1;
1293 details
->modrm_offset
= insn
- start
;
1297 /* Update %rip-relative addressing in INSN.
1299 %rip-relative addressing only uses a 32-bit displacement.
1300 32 bits is not enough to be guaranteed to cover the distance between where
1301 the real instruction is and where its copy is.
1302 Convert the insn to use base+disp addressing.
1303 We set base = pc + insn_length so we can leave disp unchanged. */
1306 fixup_riprel (struct gdbarch
*gdbarch
, struct displaced_step_closure
*dsc
,
1307 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1309 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1310 int modrm_offset
= insn_details
->modrm_offset
;
1311 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1314 int arch_tmp_regno
, tmp_regno
;
1315 ULONGEST orig_value
;
1317 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1320 /* Compute the rip-relative address. */
1321 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
,
1322 dsc
->max_len
, from
);
1323 rip_base
= from
+ insn_length
;
1325 /* We need a register to hold the address.
1326 Pick one not used in the insn.
1327 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1328 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1329 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1331 /* REX.B should be unset as we were using rip-relative addressing,
1332 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1333 if (insn_details
->rex_offset
!= -1)
1334 dsc
->insn_buf
[insn_details
->rex_offset
] &= ~REX_B
;
1336 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1337 dsc
->tmp_regno
= tmp_regno
;
1338 dsc
->tmp_save
= orig_value
;
1341 /* Convert the ModRM field to be base+disp. */
1342 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1343 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1345 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1347 if (debug_displaced
)
1348 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1349 "displaced: using temp reg %d, old value %s, new value %s\n",
1350 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1351 paddress (gdbarch
, rip_base
));
1355 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1356 struct displaced_step_closure
*dsc
,
1357 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1359 const struct amd64_insn
*details
= &dsc
->insn_details
;
1361 if (details
->modrm_offset
!= -1)
1363 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1365 if ((modrm
& 0xc7) == 0x05)
1367 /* The insn uses rip-relative addressing.
1369 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1374 struct displaced_step_closure
*
1375 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1376 CORE_ADDR from
, CORE_ADDR to
,
1377 struct regcache
*regs
)
1379 int len
= gdbarch_max_insn_length (gdbarch
);
1380 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1381 continually watch for running off the end of the buffer. */
1382 int fixup_sentinel_space
= len
;
1383 struct displaced_step_closure
*dsc
1384 = ((struct displaced_step_closure
*)
1385 xmalloc (sizeof (*dsc
) + len
+ fixup_sentinel_space
));
1386 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1387 struct amd64_insn
*details
= &dsc
->insn_details
;
1390 dsc
->max_len
= len
+ fixup_sentinel_space
;
1392 read_memory (from
, buf
, len
);
1394 /* Set up the sentinel space so we don't have to worry about running
1395 off the end of the buffer. An excessive number of leading prefixes
1396 could otherwise cause this. */
1397 memset (buf
+ len
, 0, fixup_sentinel_space
);
1399 amd64_get_insn_details (buf
, details
);
1401 /* GDB may get control back after the insn after the syscall.
1402 Presumably this is a kernel bug.
1403 If this is a syscall, make sure there's a nop afterwards. */
1407 if (amd64_syscall_p (details
, &syscall_length
))
1408 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1411 /* Modify the insn to cope with the address where it will be executed from.
1412 In particular, handle any rip-relative addressing. */
1413 fixup_displaced_copy (gdbarch
, dsc
, from
, to
, regs
);
1415 write_memory (to
, buf
, len
);
1417 if (debug_displaced
)
1419 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1420 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1421 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1428 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1430 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1432 if (insn
[0] == 0xff)
1434 /* jump near, absolute indirect (/4) */
1435 if ((insn
[1] & 0x38) == 0x20)
1438 /* jump far, absolute indirect (/5) */
1439 if ((insn
[1] & 0x38) == 0x28)
1446 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1449 amd64_jmp_p (const struct amd64_insn
*details
)
1451 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1453 /* jump short, relative. */
1454 if (insn
[0] == 0xeb)
1457 /* jump near, relative. */
1458 if (insn
[0] == 0xe9)
1461 return amd64_absolute_jmp_p (details
);
1465 amd64_absolute_call_p (const struct amd64_insn
*details
)
1467 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1469 if (insn
[0] == 0xff)
1471 /* Call near, absolute indirect (/2) */
1472 if ((insn
[1] & 0x38) == 0x10)
1475 /* Call far, absolute indirect (/3) */
1476 if ((insn
[1] & 0x38) == 0x18)
1484 amd64_ret_p (const struct amd64_insn
*details
)
1486 /* NOTE: gcc can emit "repz ; ret". */
1487 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1491 case 0xc2: /* ret near, pop N bytes */
1492 case 0xc3: /* ret near */
1493 case 0xca: /* ret far, pop N bytes */
1494 case 0xcb: /* ret far */
1495 case 0xcf: /* iret */
1504 amd64_call_p (const struct amd64_insn
*details
)
1506 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1508 if (amd64_absolute_call_p (details
))
1511 /* call near, relative */
1512 if (insn
[0] == 0xe8)
1518 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1519 length in bytes. Otherwise, return zero. */
1522 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1524 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1526 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1535 /* Classify the instruction at ADDR using PRED.
1536 Throw an error if the memory can't be read. */
1539 amd64_classify_insn_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1540 int (*pred
) (const struct amd64_insn
*))
1542 struct amd64_insn details
;
1544 int len
, classification
;
1546 len
= gdbarch_max_insn_length (gdbarch
);
1547 buf
= (gdb_byte
*) alloca (len
);
1549 read_code (addr
, buf
, len
);
1550 amd64_get_insn_details (buf
, &details
);
1552 classification
= pred (&details
);
1554 return classification
;
1557 /* The gdbarch insn_is_call method. */
1560 amd64_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1562 return amd64_classify_insn_at (gdbarch
, addr
, amd64_call_p
);
1565 /* The gdbarch insn_is_ret method. */
1568 amd64_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1570 return amd64_classify_insn_at (gdbarch
, addr
, amd64_ret_p
);
1573 /* The gdbarch insn_is_jump method. */
1576 amd64_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1578 return amd64_classify_insn_at (gdbarch
, addr
, amd64_jmp_p
);
1581 /* Fix up the state of registers and memory after having single-stepped
1582 a displaced instruction. */
1585 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1586 struct displaced_step_closure
*dsc
,
1587 CORE_ADDR from
, CORE_ADDR to
,
1588 struct regcache
*regs
)
1590 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1591 /* The offset we applied to the instruction's address. */
1592 ULONGEST insn_offset
= to
- from
;
1593 gdb_byte
*insn
= dsc
->insn_buf
;
1594 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1596 if (debug_displaced
)
1597 fprintf_unfiltered (gdb_stdlog
,
1598 "displaced: fixup (%s, %s), "
1599 "insn = 0x%02x 0x%02x ...\n",
1600 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1603 /* If we used a tmp reg, restore it. */
1607 if (debug_displaced
)
1608 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1609 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1610 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1613 /* The list of issues to contend with here is taken from
1614 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1615 Yay for Free Software! */
1617 /* Relocate the %rip back to the program's instruction stream,
1620 /* Except in the case of absolute or indirect jump or call
1621 instructions, or a return instruction, the new rip is relative to
1622 the displaced instruction; make it relative to the original insn.
1623 Well, signal handler returns don't need relocation either, but we use the
1624 value of %rip to recognize those; see below. */
1625 if (! amd64_absolute_jmp_p (insn_details
)
1626 && ! amd64_absolute_call_p (insn_details
)
1627 && ! amd64_ret_p (insn_details
))
1632 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1634 /* A signal trampoline system call changes the %rip, resuming
1635 execution of the main program after the signal handler has
1636 returned. That makes them like 'return' instructions; we
1637 shouldn't relocate %rip.
1639 But most system calls don't, and we do need to relocate %rip.
1641 Our heuristic for distinguishing these cases: if stepping
1642 over the system call instruction left control directly after
1643 the instruction, the we relocate --- control almost certainly
1644 doesn't belong in the displaced copy. Otherwise, we assume
1645 the instruction has put control where it belongs, and leave
1646 it unrelocated. Goodness help us if there are PC-relative
1648 if (amd64_syscall_p (insn_details
, &insn_len
)
1649 && orig_rip
!= to
+ insn_len
1650 /* GDB can get control back after the insn after the syscall.
1651 Presumably this is a kernel bug.
1652 Fixup ensures its a nop, we add one to the length for it. */
1653 && orig_rip
!= to
+ insn_len
+ 1)
1655 if (debug_displaced
)
1656 fprintf_unfiltered (gdb_stdlog
,
1657 "displaced: syscall changed %%rip; "
1658 "not relocating\n");
1662 ULONGEST rip
= orig_rip
- insn_offset
;
1664 /* If we just stepped over a breakpoint insn, we don't backup
1665 the pc on purpose; this is to match behaviour without
1668 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1670 if (debug_displaced
)
1671 fprintf_unfiltered (gdb_stdlog
,
1673 "relocated %%rip from %s to %s\n",
1674 paddress (gdbarch
, orig_rip
),
1675 paddress (gdbarch
, rip
));
1679 /* If the instruction was PUSHFL, then the TF bit will be set in the
1680 pushed value, and should be cleared. We'll leave this for later,
1681 since GDB already messes up the TF flag when stepping over a
1684 /* If the instruction was a call, the return address now atop the
1685 stack is the address following the copied instruction. We need
1686 to make it the address following the original instruction. */
1687 if (amd64_call_p (insn_details
))
1691 const ULONGEST retaddr_len
= 8;
1693 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1694 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1695 retaddr
= (retaddr
- insn_offset
) & 0xffffffffffffffffULL
;
1696 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1698 if (debug_displaced
)
1699 fprintf_unfiltered (gdb_stdlog
,
1700 "displaced: relocated return addr at %s "
1702 paddress (gdbarch
, rsp
),
1703 paddress (gdbarch
, retaddr
));
1707 /* If the instruction INSN uses RIP-relative addressing, return the
1708 offset into the raw INSN where the displacement to be adjusted is
1709 found. Returns 0 if the instruction doesn't use RIP-relative
1713 rip_relative_offset (struct amd64_insn
*insn
)
1715 if (insn
->modrm_offset
!= -1)
1717 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1719 if ((modrm
& 0xc7) == 0x05)
1721 /* The displacement is found right after the ModRM byte. */
1722 return insn
->modrm_offset
+ 1;
1730 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1732 target_write_memory (*to
, buf
, len
);
1737 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1738 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1740 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1741 int len
= gdbarch_max_insn_length (gdbarch
);
1742 /* Extra space for sentinels. */
1743 int fixup_sentinel_space
= len
;
1744 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
+ fixup_sentinel_space
);
1745 struct amd64_insn insn_details
;
1747 LONGEST rel32
, newrel
;
1751 read_memory (oldloc
, buf
, len
);
1753 /* Set up the sentinel space so we don't have to worry about running
1754 off the end of the buffer. An excessive number of leading prefixes
1755 could otherwise cause this. */
1756 memset (buf
+ len
, 0, fixup_sentinel_space
);
1759 amd64_get_insn_details (insn
, &insn_details
);
1761 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1763 /* Skip legacy instruction prefixes. */
1764 insn
= amd64_skip_prefixes (insn
);
1766 /* Adjust calls with 32-bit relative addresses as push/jump, with
1767 the address pushed being the location where the original call in
1768 the user program would return to. */
1769 if (insn
[0] == 0xe8)
1771 gdb_byte push_buf
[32];
1775 /* Where "ret" in the original code will return to. */
1776 ret_addr
= oldloc
+ insn_length
;
1778 /* If pushing an address higher than or equal to 0x80000000,
1779 avoid 'pushq', as that sign extends its 32-bit operand, which
1780 would be incorrect. */
1781 if (ret_addr
<= 0x7fffffff)
1783 push_buf
[0] = 0x68; /* pushq $... */
1784 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1789 push_buf
[i
++] = 0x48; /* sub $0x8,%rsp */
1790 push_buf
[i
++] = 0x83;
1791 push_buf
[i
++] = 0xec;
1792 push_buf
[i
++] = 0x08;
1794 push_buf
[i
++] = 0xc7; /* movl $imm,(%rsp) */
1795 push_buf
[i
++] = 0x04;
1796 push_buf
[i
++] = 0x24;
1797 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1798 ret_addr
& 0xffffffff);
1801 push_buf
[i
++] = 0xc7; /* movl $imm,4(%rsp) */
1802 push_buf
[i
++] = 0x44;
1803 push_buf
[i
++] = 0x24;
1804 push_buf
[i
++] = 0x04;
1805 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1809 gdb_assert (i
<= sizeof (push_buf
));
1810 /* Push the push. */
1811 append_insns (to
, i
, push_buf
);
1813 /* Convert the relative call to a relative jump. */
1816 /* Adjust the destination offset. */
1817 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1818 newrel
= (oldloc
- *to
) + rel32
;
1819 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1821 if (debug_displaced
)
1822 fprintf_unfiltered (gdb_stdlog
,
1823 "Adjusted insn rel32=%s at %s to"
1824 " rel32=%s at %s\n",
1825 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1826 hex_string (newrel
), paddress (gdbarch
, *to
));
1828 /* Write the adjusted jump into its displaced location. */
1829 append_insns (to
, 5, insn
);
1833 offset
= rip_relative_offset (&insn_details
);
1836 /* Adjust jumps with 32-bit relative addresses. Calls are
1837 already handled above. */
1838 if (insn
[0] == 0xe9)
1840 /* Adjust conditional jumps. */
1841 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1847 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1848 newrel
= (oldloc
- *to
) + rel32
;
1849 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1850 if (debug_displaced
)
1851 fprintf_unfiltered (gdb_stdlog
,
1852 "Adjusted insn rel32=%s at %s to"
1853 " rel32=%s at %s\n",
1854 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1855 hex_string (newrel
), paddress (gdbarch
, *to
));
1858 /* Write the adjusted instruction into its displaced location. */
1859 append_insns (to
, insn_length
, buf
);
1863 /* The maximum number of saved registers. This should include %rip. */
1864 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1866 struct amd64_frame_cache
1871 CORE_ADDR sp_offset
;
1874 /* Saved registers. */
1875 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1879 /* Do we have a frame? */
1883 /* Initialize a frame cache. */
1886 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1893 cache
->sp_offset
= -8;
1896 /* Saved registers. We initialize these to -1 since zero is a valid
1897 offset (that's where %rbp is supposed to be stored).
1898 The values start out as being offsets, and are later converted to
1899 addresses (at which point -1 is interpreted as an address, still meaning
1901 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1902 cache
->saved_regs
[i
] = -1;
1903 cache
->saved_sp
= 0;
1904 cache
->saved_sp_reg
= -1;
1906 /* Frameless until proven otherwise. */
1907 cache
->frameless_p
= 1;
1910 /* Allocate and initialize a frame cache. */
1912 static struct amd64_frame_cache
*
1913 amd64_alloc_frame_cache (void)
1915 struct amd64_frame_cache
*cache
;
1917 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1918 amd64_init_frame_cache (cache
);
1922 /* GCC 4.4 and later, can put code in the prologue to realign the
1923 stack pointer. Check whether PC points to such code, and update
1924 CACHE accordingly. Return the first instruction after the code
1925 sequence or CURRENT_PC, whichever is smaller. If we don't
1926 recognize the code, return PC. */
1929 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1930 struct amd64_frame_cache
*cache
)
1932 /* There are 2 code sequences to re-align stack before the frame
1935 1. Use a caller-saved saved register:
1941 2. Use a callee-saved saved register:
1948 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1950 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1951 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1956 int offset
, offset_and
;
1958 if (target_read_code (pc
, buf
, sizeof buf
))
1961 /* Check caller-saved saved register. The first instruction has
1962 to be "leaq 8(%rsp), %reg". */
1963 if ((buf
[0] & 0xfb) == 0x48
1968 /* MOD must be binary 10 and R/M must be binary 100. */
1969 if ((buf
[2] & 0xc7) != 0x44)
1972 /* REG has register number. */
1973 reg
= (buf
[2] >> 3) & 7;
1975 /* Check the REX.R bit. */
1983 /* Check callee-saved saved register. The first instruction
1984 has to be "pushq %reg". */
1986 if ((buf
[0] & 0xf8) == 0x50)
1988 else if ((buf
[0] & 0xf6) == 0x40
1989 && (buf
[1] & 0xf8) == 0x50)
1991 /* Check the REX.B bit. */
1992 if ((buf
[0] & 1) != 0)
2001 reg
+= buf
[offset
] & 0x7;
2005 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2006 if ((buf
[offset
] & 0xfb) != 0x48
2007 || buf
[offset
+ 1] != 0x8d
2008 || buf
[offset
+ 3] != 0x24
2009 || buf
[offset
+ 4] != 0x10)
2012 /* MOD must be binary 10 and R/M must be binary 100. */
2013 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2016 /* REG has register number. */
2017 r
= (buf
[offset
+ 2] >> 3) & 7;
2019 /* Check the REX.R bit. */
2020 if (buf
[offset
] == 0x4c)
2023 /* Registers in pushq and leaq have to be the same. */
2030 /* Rigister can't be %rsp nor %rbp. */
2031 if (reg
== 4 || reg
== 5)
2034 /* The next instruction has to be "andq $-XXX, %rsp". */
2035 if (buf
[offset
] != 0x48
2036 || buf
[offset
+ 2] != 0xe4
2037 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2040 offset_and
= offset
;
2041 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2043 /* The next instruction has to be "pushq -8(%reg)". */
2045 if (buf
[offset
] == 0xff)
2047 else if ((buf
[offset
] & 0xf6) == 0x40
2048 && buf
[offset
+ 1] == 0xff)
2050 /* Check the REX.B bit. */
2051 if ((buf
[offset
] & 0x1) != 0)
2058 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2060 if (buf
[offset
+ 1] != 0xf8
2061 || (buf
[offset
] & 0xf8) != 0x70)
2064 /* R/M has register. */
2065 r
+= buf
[offset
] & 7;
2067 /* Registers in leaq and pushq have to be the same. */
2071 if (current_pc
> pc
+ offset_and
)
2072 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2074 return std::min (pc
+ offset
+ 2, current_pc
);
2077 /* Similar to amd64_analyze_stack_align for x32. */
2080 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2081 struct amd64_frame_cache
*cache
)
2083 /* There are 2 code sequences to re-align stack before the frame
2086 1. Use a caller-saved saved register:
2094 [addr32] leal 8(%rsp), %reg
2096 [addr32] pushq -8(%reg)
2098 2. Use a callee-saved saved register:
2108 [addr32] leal 16(%rsp), %reg
2110 [addr32] pushq -8(%reg)
2112 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2114 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2115 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2117 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2119 0x83 0xe4 0xf0 andl $-16, %esp
2120 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2125 int offset
, offset_and
;
2127 if (target_read_memory (pc
, buf
, sizeof buf
))
2130 /* Skip optional addr32 prefix. */
2131 offset
= buf
[0] == 0x67 ? 1 : 0;
2133 /* Check caller-saved saved register. The first instruction has
2134 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2135 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
2136 && buf
[offset
+ 1] == 0x8d
2137 && buf
[offset
+ 3] == 0x24
2138 && buf
[offset
+ 4] == 0x8)
2140 /* MOD must be binary 10 and R/M must be binary 100. */
2141 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2144 /* REG has register number. */
2145 reg
= (buf
[offset
+ 2] >> 3) & 7;
2147 /* Check the REX.R bit. */
2148 if ((buf
[offset
] & 0x4) != 0)
2155 /* Check callee-saved saved register. The first instruction
2156 has to be "pushq %reg". */
2158 if ((buf
[offset
] & 0xf6) == 0x40
2159 && (buf
[offset
+ 1] & 0xf8) == 0x50)
2161 /* Check the REX.B bit. */
2162 if ((buf
[offset
] & 1) != 0)
2167 else if ((buf
[offset
] & 0xf8) != 0x50)
2171 reg
+= buf
[offset
] & 0x7;
2175 /* Skip optional addr32 prefix. */
2176 if (buf
[offset
] == 0x67)
2179 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2180 "leal 16(%rsp), %reg". */
2181 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
2182 || buf
[offset
+ 1] != 0x8d
2183 || buf
[offset
+ 3] != 0x24
2184 || buf
[offset
+ 4] != 0x10)
2187 /* MOD must be binary 10 and R/M must be binary 100. */
2188 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2191 /* REG has register number. */
2192 r
= (buf
[offset
+ 2] >> 3) & 7;
2194 /* Check the REX.R bit. */
2195 if ((buf
[offset
] & 0x4) != 0)
2198 /* Registers in pushq and leaq have to be the same. */
2205 /* Rigister can't be %rsp nor %rbp. */
2206 if (reg
== 4 || reg
== 5)
2209 /* The next instruction may be "andq $-XXX, %rsp" or
2210 "andl $-XXX, %esp". */
2211 if (buf
[offset
] != 0x48)
2214 if (buf
[offset
+ 2] != 0xe4
2215 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2218 offset_and
= offset
;
2219 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2221 /* Skip optional addr32 prefix. */
2222 if (buf
[offset
] == 0x67)
2225 /* The next instruction has to be "pushq -8(%reg)". */
2227 if (buf
[offset
] == 0xff)
2229 else if ((buf
[offset
] & 0xf6) == 0x40
2230 && buf
[offset
+ 1] == 0xff)
2232 /* Check the REX.B bit. */
2233 if ((buf
[offset
] & 0x1) != 0)
2240 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2242 if (buf
[offset
+ 1] != 0xf8
2243 || (buf
[offset
] & 0xf8) != 0x70)
2246 /* R/M has register. */
2247 r
+= buf
[offset
] & 7;
2249 /* Registers in leaq and pushq have to be the same. */
2253 if (current_pc
> pc
+ offset_and
)
2254 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2256 return std::min (pc
+ offset
+ 2, current_pc
);
2259 /* Do a limited analysis of the prologue at PC and update CACHE
2260 accordingly. Bail out early if CURRENT_PC is reached. Return the
2261 address where the analysis stopped.
2263 We will handle only functions beginning with:
2266 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2268 or (for the X32 ABI):
2271 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2273 Any function that doesn't start with one of these sequences will be
2274 assumed to have no prologue and thus no valid frame pointer in
2278 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2279 CORE_ADDR pc
, CORE_ADDR current_pc
,
2280 struct amd64_frame_cache
*cache
)
2282 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2283 /* There are two variations of movq %rsp, %rbp. */
2284 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2285 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2286 /* Ditto for movl %esp, %ebp. */
2287 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2288 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2293 if (current_pc
<= pc
)
2296 if (gdbarch_ptr_bit (gdbarch
) == 32)
2297 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2299 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2301 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2303 if (op
== 0x55) /* pushq %rbp */
2305 /* Take into account that we've executed the `pushq %rbp' that
2306 starts this instruction sequence. */
2307 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2308 cache
->sp_offset
+= 8;
2310 /* If that's all, return now. */
2311 if (current_pc
<= pc
+ 1)
2314 read_code (pc
+ 1, buf
, 3);
2316 /* Check for `movq %rsp, %rbp'. */
2317 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2318 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2320 /* OK, we actually have a frame. */
2321 cache
->frameless_p
= 0;
2325 /* For X32, also check for `movq %esp, %ebp'. */
2326 if (gdbarch_ptr_bit (gdbarch
) == 32)
2328 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2329 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2331 /* OK, we actually have a frame. */
2332 cache
->frameless_p
= 0;
2343 /* Work around false termination of prologue - GCC PR debug/48827.
2345 START_PC is the first instruction of a function, PC is its minimal already
2346 determined advanced address. Function returns PC if it has nothing to do.
2350 <-- here is 0 lines advance - the false prologue end marker.
2351 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2352 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2353 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2354 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2355 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2356 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2357 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2358 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2362 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2364 struct symtab_and_line start_pc_sal
, next_sal
;
2365 gdb_byte buf
[4 + 8 * 7];
2371 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2372 if (start_pc_sal
.symtab
== NULL
2373 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2374 (SYMTAB_COMPUNIT (start_pc_sal
.symtab
))) < 6
2375 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2378 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2379 if (next_sal
.line
!= start_pc_sal
.line
)
2382 /* START_PC can be from overlayed memory, ignored here. */
2383 if (target_read_code (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2387 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2394 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2396 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2397 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2398 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2402 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2404 /* 8-bit displacement. */
2408 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2410 /* 32-bit displacement. */
2418 if (offset
- 4 != buf
[3])
2421 return next_sal
.end
;
2424 /* Return PC of first real instruction. */
2427 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2429 struct amd64_frame_cache cache
;
2431 CORE_ADDR func_addr
;
2433 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2435 CORE_ADDR post_prologue_pc
2436 = skip_prologue_using_sal (gdbarch
, func_addr
);
2437 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
2439 /* Clang always emits a line note before the prologue and another
2440 one after. We trust clang to emit usable line notes. */
2441 if (post_prologue_pc
2443 && COMPUNIT_PRODUCER (cust
) != NULL
2444 && startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
2445 return std::max (start_pc
, post_prologue_pc
);
2448 amd64_init_frame_cache (&cache
);
2449 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2451 if (cache
.frameless_p
)
2454 return amd64_skip_xmm_prologue (pc
, start_pc
);
2458 /* Normal frames. */
2461 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2462 struct amd64_frame_cache
*cache
)
2464 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2465 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2469 cache
->pc
= get_frame_func (this_frame
);
2471 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2474 if (cache
->frameless_p
)
2476 /* We didn't find a valid frame. If we're at the start of a
2477 function, or somewhere half-way its prologue, the function's
2478 frame probably hasn't been fully setup yet. Try to
2479 reconstruct the base address for the stack frame by looking
2480 at the stack pointer. For truly "frameless" functions this
2483 if (cache
->saved_sp_reg
!= -1)
2485 /* Stack pointer has been saved. */
2486 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2487 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2489 /* We're halfway aligning the stack. */
2490 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2491 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2493 /* This will be added back below. */
2494 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2498 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2499 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2505 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2506 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2509 /* Now that we have the base address for the stack frame we can
2510 calculate the value of %rsp in the calling frame. */
2511 cache
->saved_sp
= cache
->base
+ 16;
2513 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2514 frame we find it at the same offset from the reconstructed base
2515 address. If we're halfway aligning the stack, %rip is handled
2516 differently (see above). */
2517 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2518 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2520 /* Adjust all the saved registers such that they contain addresses
2521 instead of offsets. */
2522 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2523 if (cache
->saved_regs
[i
] != -1)
2524 cache
->saved_regs
[i
] += cache
->base
;
2529 static struct amd64_frame_cache
*
2530 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2532 struct amd64_frame_cache
*cache
;
2535 return (struct amd64_frame_cache
*) *this_cache
;
2537 cache
= amd64_alloc_frame_cache ();
2538 *this_cache
= cache
;
2542 amd64_frame_cache_1 (this_frame
, cache
);
2544 CATCH (ex
, RETURN_MASK_ERROR
)
2546 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2547 throw_exception (ex
);
2554 static enum unwind_stop_reason
2555 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2558 struct amd64_frame_cache
*cache
=
2559 amd64_frame_cache (this_frame
, this_cache
);
2562 return UNWIND_UNAVAILABLE
;
2564 /* This marks the outermost frame. */
2565 if (cache
->base
== 0)
2566 return UNWIND_OUTERMOST
;
2568 return UNWIND_NO_REASON
;
2572 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2573 struct frame_id
*this_id
)
2575 struct amd64_frame_cache
*cache
=
2576 amd64_frame_cache (this_frame
, this_cache
);
2579 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2580 else if (cache
->base
== 0)
2582 /* This marks the outermost frame. */
2586 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2589 static struct value
*
2590 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2593 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2594 struct amd64_frame_cache
*cache
=
2595 amd64_frame_cache (this_frame
, this_cache
);
2597 gdb_assert (regnum
>= 0);
2599 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2600 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2602 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2603 return frame_unwind_got_memory (this_frame
, regnum
,
2604 cache
->saved_regs
[regnum
]);
2606 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2609 static const struct frame_unwind amd64_frame_unwind
=
2612 amd64_frame_unwind_stop_reason
,
2613 amd64_frame_this_id
,
2614 amd64_frame_prev_register
,
2616 default_frame_sniffer
2619 /* Generate a bytecode expression to get the value of the saved PC. */
2622 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2623 struct agent_expr
*ax
, struct axs_value
*value
,
2626 /* The following sequence assumes the traditional use of the base
2628 ax_reg (ax
, AMD64_RBP_REGNUM
);
2630 ax_simple (ax
, aop_add
);
2631 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2632 value
->kind
= axs_lvalue_memory
;
2636 /* Signal trampolines. */
2638 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2639 64-bit variants. This would require using identical frame caches
2640 on both platforms. */
2642 static struct amd64_frame_cache
*
2643 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2645 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2646 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2647 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2648 struct amd64_frame_cache
*cache
;
2654 return (struct amd64_frame_cache
*) *this_cache
;
2656 cache
= amd64_alloc_frame_cache ();
2660 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2661 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2663 addr
= tdep
->sigcontext_addr (this_frame
);
2664 gdb_assert (tdep
->sc_reg_offset
);
2665 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2666 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2667 if (tdep
->sc_reg_offset
[i
] != -1)
2668 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2672 CATCH (ex
, RETURN_MASK_ERROR
)
2674 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2675 throw_exception (ex
);
2679 *this_cache
= cache
;
2683 static enum unwind_stop_reason
2684 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2687 struct amd64_frame_cache
*cache
=
2688 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2691 return UNWIND_UNAVAILABLE
;
2693 return UNWIND_NO_REASON
;
2697 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2698 void **this_cache
, struct frame_id
*this_id
)
2700 struct amd64_frame_cache
*cache
=
2701 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2704 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2705 else if (cache
->base
== 0)
2707 /* This marks the outermost frame. */
2711 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2714 static struct value
*
2715 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2716 void **this_cache
, int regnum
)
2718 /* Make sure we've initialized the cache. */
2719 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2721 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2725 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2726 struct frame_info
*this_frame
,
2729 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2731 /* We shouldn't even bother if we don't have a sigcontext_addr
2733 if (tdep
->sigcontext_addr
== NULL
)
2736 if (tdep
->sigtramp_p
!= NULL
)
2738 if (tdep
->sigtramp_p (this_frame
))
2742 if (tdep
->sigtramp_start
!= 0)
2744 CORE_ADDR pc
= get_frame_pc (this_frame
);
2746 gdb_assert (tdep
->sigtramp_end
!= 0);
2747 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2754 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2757 amd64_sigtramp_frame_unwind_stop_reason
,
2758 amd64_sigtramp_frame_this_id
,
2759 amd64_sigtramp_frame_prev_register
,
2761 amd64_sigtramp_frame_sniffer
2766 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2768 struct amd64_frame_cache
*cache
=
2769 amd64_frame_cache (this_frame
, this_cache
);
2774 static const struct frame_base amd64_frame_base
=
2776 &amd64_frame_unwind
,
2777 amd64_frame_base_address
,
2778 amd64_frame_base_address
,
2779 amd64_frame_base_address
2782 /* Normal frames, but in a function epilogue. */
2784 /* Implement the stack_frame_destroyed_p gdbarch method.
2786 The epilogue is defined here as the 'ret' instruction, which will
2787 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2788 the function's stack frame. */
2791 amd64_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2794 struct compunit_symtab
*cust
;
2796 cust
= find_pc_compunit_symtab (pc
);
2797 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2800 if (target_read_memory (pc
, &insn
, 1))
2801 return 0; /* Can't read memory at pc. */
2803 if (insn
!= 0xc3) /* 'ret' instruction. */
2810 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2811 struct frame_info
*this_frame
,
2812 void **this_prologue_cache
)
2814 if (frame_relative_level (this_frame
) == 0)
2815 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2816 get_frame_pc (this_frame
));
2821 static struct amd64_frame_cache
*
2822 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2824 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2825 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2826 struct amd64_frame_cache
*cache
;
2830 return (struct amd64_frame_cache
*) *this_cache
;
2832 cache
= amd64_alloc_frame_cache ();
2833 *this_cache
= cache
;
2837 /* Cache base will be %esp plus cache->sp_offset (-8). */
2838 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2839 cache
->base
= extract_unsigned_integer (buf
, 8,
2840 byte_order
) + cache
->sp_offset
;
2842 /* Cache pc will be the frame func. */
2843 cache
->pc
= get_frame_pc (this_frame
);
2845 /* The saved %esp will be at cache->base plus 16. */
2846 cache
->saved_sp
= cache
->base
+ 16;
2848 /* The saved %eip will be at cache->base plus 8. */
2849 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2853 CATCH (ex
, RETURN_MASK_ERROR
)
2855 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2856 throw_exception (ex
);
2863 static enum unwind_stop_reason
2864 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2867 struct amd64_frame_cache
*cache
2868 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2871 return UNWIND_UNAVAILABLE
;
2873 return UNWIND_NO_REASON
;
2877 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2879 struct frame_id
*this_id
)
2881 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2885 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2887 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2890 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2893 amd64_epilogue_frame_unwind_stop_reason
,
2894 amd64_epilogue_frame_this_id
,
2895 amd64_frame_prev_register
,
2897 amd64_epilogue_frame_sniffer
2900 static struct frame_id
2901 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2905 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2907 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2910 /* 16 byte align the SP per frame requirements. */
2913 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2915 return sp
& -(CORE_ADDR
)16;
2919 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2920 in the floating-point register set REGSET to register cache
2921 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2924 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2925 int regnum
, const void *fpregs
, size_t len
)
2927 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2928 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2930 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2931 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
2934 /* Collect register REGNUM from the register cache REGCACHE and store
2935 it in the buffer specified by FPREGS and LEN as described by the
2936 floating-point register set REGSET. If REGNUM is -1, do this for
2937 all registers in REGSET. */
2940 amd64_collect_fpregset (const struct regset
*regset
,
2941 const struct regcache
*regcache
,
2942 int regnum
, void *fpregs
, size_t len
)
2944 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2945 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2947 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2948 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
2951 const struct regset amd64_fpregset
=
2953 NULL
, amd64_supply_fpregset
, amd64_collect_fpregset
2957 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2958 %rdi. We expect its value to be a pointer to the jmp_buf structure
2959 from which we extract the address that we will land at. This
2960 address is copied into PC. This routine returns non-zero on
2964 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2968 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2969 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2970 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
2972 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2973 longjmp will land. */
2974 if (jb_pc_offset
== -1)
2977 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
2978 jb_addr
= extract_typed_address
2979 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
2980 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
2983 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
2988 static const int amd64_record_regmap
[] =
2990 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
2991 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
2992 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
2993 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
2994 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
2995 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
2999 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3000 const target_desc
*default_tdesc
)
3002 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3003 const struct target_desc
*tdesc
= info
.target_desc
;
3004 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
3005 static const char *const stap_register_prefixes
[] = { "%", NULL
};
3006 static const char *const stap_register_indirection_prefixes
[] = { "(",
3008 static const char *const stap_register_indirection_suffixes
[] = { ")",
3011 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3012 floating-point registers. */
3013 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
3014 tdep
->fpregset
= &amd64_fpregset
;
3016 if (! tdesc_has_registers (tdesc
))
3017 tdesc
= default_tdesc
;
3018 tdep
->tdesc
= tdesc
;
3020 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
3021 tdep
->register_names
= amd64_register_names
;
3023 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512") != NULL
)
3025 tdep
->zmmh_register_names
= amd64_zmmh_names
;
3026 tdep
->k_register_names
= amd64_k_names
;
3027 tdep
->xmm_avx512_register_names
= amd64_xmm_avx512_names
;
3028 tdep
->ymm16h_register_names
= amd64_ymmh_avx512_names
;
3030 tdep
->num_zmm_regs
= 32;
3031 tdep
->num_xmm_avx512_regs
= 16;
3032 tdep
->num_ymm_avx512_regs
= 16;
3034 tdep
->zmm0h_regnum
= AMD64_ZMM0H_REGNUM
;
3035 tdep
->k0_regnum
= AMD64_K0_REGNUM
;
3036 tdep
->xmm16_regnum
= AMD64_XMM16_REGNUM
;
3037 tdep
->ymm16h_regnum
= AMD64_YMM16H_REGNUM
;
3040 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
3042 tdep
->ymmh_register_names
= amd64_ymmh_names
;
3043 tdep
->num_ymm_regs
= 16;
3044 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
3047 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
)
3049 tdep
->mpx_register_names
= amd64_mpx_names
;
3050 tdep
->bndcfgu_regnum
= AMD64_BNDCFGU_REGNUM
;
3051 tdep
->bnd0r_regnum
= AMD64_BND0R_REGNUM
;
3054 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments") != NULL
)
3056 const struct tdesc_feature
*feature
=
3057 tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments");
3058 struct tdesc_arch_data
*tdesc_data_segments
=
3059 (struct tdesc_arch_data
*) info
.tdep_info
;
3061 tdesc_numbered_register (feature
, tdesc_data_segments
,
3062 AMD64_FSBASE_REGNUM
, "fs_base");
3063 tdesc_numbered_register (feature
, tdesc_data_segments
,
3064 AMD64_GSBASE_REGNUM
, "gs_base");
3067 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys") != NULL
)
3069 tdep
->pkeys_register_names
= amd64_pkeys_names
;
3070 tdep
->pkru_regnum
= AMD64_PKRU_REGNUM
;
3071 tdep
->num_pkeys_regs
= 1;
3074 tdep
->num_byte_regs
= 20;
3075 tdep
->num_word_regs
= 16;
3076 tdep
->num_dword_regs
= 16;
3077 /* Avoid wiring in the MMX registers for now. */
3078 tdep
->num_mmx_regs
= 0;
3080 set_gdbarch_pseudo_register_read_value (gdbarch
,
3081 amd64_pseudo_register_read_value
);
3082 set_gdbarch_pseudo_register_write (gdbarch
,
3083 amd64_pseudo_register_write
);
3084 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
3085 amd64_ax_pseudo_register_collect
);
3087 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
3089 /* AMD64 has an FPU and 16 SSE registers. */
3090 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
3091 tdep
->num_xmm_regs
= 16;
3093 /* This is what all the fuss is about. */
3094 set_gdbarch_long_bit (gdbarch
, 64);
3095 set_gdbarch_long_long_bit (gdbarch
, 64);
3096 set_gdbarch_ptr_bit (gdbarch
, 64);
3098 /* In contrast to the i386, on AMD64 a `long double' actually takes
3099 up 128 bits, even though it's still based on the i387 extended
3100 floating-point format which has only 80 significant bits. */
3101 set_gdbarch_long_double_bit (gdbarch
, 128);
3103 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
3105 /* Register numbers of various important registers. */
3106 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
3107 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
3108 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
3109 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
3111 /* The "default" register numbering scheme for AMD64 is referred to
3112 as the "DWARF Register Number Mapping" in the System V psABI.
3113 The preferred debugging format for all known AMD64 targets is
3114 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3115 DWARF-1), but we provide the same mapping just in case. This
3116 mapping is also used for stabs, which GCC does support. */
3117 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3118 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3120 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3121 be in use on any of the supported AMD64 targets. */
3123 /* Call dummy code. */
3124 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
3125 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
3126 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
3128 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
3129 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
3130 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
3132 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
3134 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
3136 tdep
->record_regmap
= amd64_record_regmap
;
3138 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
3140 /* Hook the function epilogue frame unwinder. This unwinder is
3141 appended to the list first, so that it supercedes the other
3142 unwinders in function epilogues. */
3143 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
3145 /* Hook the prologue-based frame unwinders. */
3146 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
3147 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
3148 frame_base_set_default (gdbarch
, &amd64_frame_base
);
3150 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
3152 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
3154 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
3156 /* SystemTap variables and functions. */
3157 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
3158 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
3159 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
3160 stap_register_indirection_prefixes
);
3161 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
3162 stap_register_indirection_suffixes
);
3163 set_gdbarch_stap_is_single_operand (gdbarch
,
3164 i386_stap_is_single_operand
);
3165 set_gdbarch_stap_parse_special_token (gdbarch
,
3166 i386_stap_parse_special_token
);
3167 set_gdbarch_insn_is_call (gdbarch
, amd64_insn_is_call
);
3168 set_gdbarch_insn_is_ret (gdbarch
, amd64_insn_is_ret
);
3169 set_gdbarch_insn_is_jump (gdbarch
, amd64_insn_is_jump
);
3173 static struct type
*
3174 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3178 switch (regnum
- tdep
->eax_regnum
)
3180 case AMD64_RBP_REGNUM
: /* %ebp */
3181 case AMD64_RSP_REGNUM
: /* %esp */
3182 return builtin_type (gdbarch
)->builtin_data_ptr
;
3183 case AMD64_RIP_REGNUM
: /* %eip */
3184 return builtin_type (gdbarch
)->builtin_func_ptr
;
3187 return i386_pseudo_register_type (gdbarch
, regnum
);
3191 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3192 const target_desc
*default_tdesc
)
3194 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3196 amd64_init_abi (info
, gdbarch
, default_tdesc
);
3198 tdep
->num_dword_regs
= 17;
3199 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
3201 set_gdbarch_long_bit (gdbarch
, 32);
3202 set_gdbarch_ptr_bit (gdbarch
, 32);
3205 /* Return the target description for a specified XSAVE feature mask. */
3207 const struct target_desc
*
3208 amd64_target_description (uint64_t xcr0
)
3210 static target_desc
*amd64_tdescs \
3211 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/] = {};
3212 target_desc
**tdesc
;
3214 tdesc
= &amd64_tdescs
[(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
3215 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
3216 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
3217 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0];
3220 *tdesc
= amd64_create_target_description (xcr0
, false, false);
3226 _initialize_amd64_tdep (void)
3234 { "i386/amd64.xml", X86_XSTATE_SSE_MASK
},
3235 { "i386/amd64-avx.xml", X86_XSTATE_AVX_MASK
},
3236 { "i386/amd64-mpx.xml", X86_XSTATE_MPX_MASK
},
3237 { "i386/amd64-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK
},
3238 { "i386/amd64-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK
},
3239 { "i386/amd64-avx-mpx-avx512-pku.xml",
3240 X86_XSTATE_AVX_MPX_AVX512_PKU_MASK
},
3243 for (auto &a
: xml_masks
)
3245 auto tdesc
= amd64_target_description (a
.mask
);
3247 selftests::record_xml_tdesc (a
.xml
, tdesc
);
3249 #endif /* GDB_SELF_TEST */
3253 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3254 sense that the instruction pointer and data pointer are simply
3255 64-bit offsets into the code segment and the data segment instead
3256 of a selector offset pair. The functions below store the upper 32
3257 bits of these pointers (instead of just the 16-bits of the segment
3260 /* Fill register REGNUM in REGCACHE with the appropriate
3261 floating-point or SSE register value from *FXSAVE. If REGNUM is
3262 -1, do this for all registers. This function masks off any of the
3263 reserved bits in *FXSAVE. */
3266 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3269 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3270 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3272 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3275 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3277 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
3279 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3280 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3281 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3282 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3286 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3289 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3292 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3293 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3295 i387_supply_xsave (regcache
, regnum
, xsave
);
3298 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3300 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
3302 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3303 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
),
3305 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3306 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
),
3311 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3312 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3313 all registers. This function doesn't touch any of the reserved
3317 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3320 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3321 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3322 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
3324 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3326 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3328 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3329 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3330 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3331 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3335 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3338 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3339 void *xsave
, int gcore
)
3341 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3342 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3343 gdb_byte
*regs
= (gdb_byte
*) xsave
;
3345 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3347 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3349 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3350 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
),
3352 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3353 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
),