1 /* ARC target-dependent stuff.
2 Copyright (C) 1995, 1997 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "floatformat.h"
32 static int arc_set_cpu_type (char *str
);
34 /* Current CPU, set with the "set cpu" command. */
35 static int arc_bfd_mach_type
;
37 char *tmp_arc_cpu_type
;
39 /* Table of cpu names. */
45 arc_cpu_type_table
[] =
47 { "arc5", bfd_mach_arc_5
},
48 { "arc6", bfd_mach_arc_6
},
49 { "arc7", bfd_mach_arc_7
},
50 { "arc8", bfd_mach_arc_8
},
54 /* Used by simulator. */
55 int display_pipeline_p
;
57 /* This one must have the same type as used in the emulator.
58 It's currently an enum so this should be ok for now. */
61 #define ARC_CALL_SAVED_REG(r) ((r) >= 16 && (r) < 24)
63 #define OPMASK 0xf8000000
65 /* Instruction field accessor macros.
66 See the Programmer's Reference Manual. */
67 #define X_OP(i) (((i) >> 27) & 0x1f)
68 #define X_A(i) (((i) >> 21) & 0x3f)
69 #define X_B(i) (((i) >> 15) & 0x3f)
70 #define X_C(i) (((i) >> 9) & 0x3f)
71 #define X_D(i) ((((i) & 0x1ff) ^ 0x100) - 0x100)
72 #define X_L(i) (((((i) >> 5) & 0x3ffffc) ^ 0x200000) - 0x200000)
73 #define X_N(i) (((i) >> 5) & 3)
74 #define X_Q(i) ((i) & 0x1f)
76 /* Return non-zero if X is a short immediate data indicator. */
77 #define SHIMM_P(x) ((x) == 61 || (x) == 63)
79 /* Return non-zero if X is a "long" (32 bit) immediate data indicator. */
80 #define LIMM_P(x) ((x) == 62)
82 /* Build a simple instruction. */
83 #define BUILD_INSN(op, a, b, c, d) \
84 ((((op) & 31) << 27) \
85 | (((a) & 63) << 21) \
86 | (((b) & 63) << 15) \
90 /* Codestream stuff. */
91 static void codestream_read (unsigned int *, int);
92 static void codestream_seek (CORE_ADDR
);
93 static unsigned int codestream_fill (int);
95 #define CODESTREAM_BUFSIZ 16
96 static CORE_ADDR codestream_next_addr
;
97 static CORE_ADDR codestream_addr
;
98 /* FIXME assumes sizeof (int) == 32? */
99 static unsigned int codestream_buf
[CODESTREAM_BUFSIZ
];
100 static int codestream_off
;
101 static int codestream_cnt
;
103 #define codestream_tell() \
104 (codestream_addr + codestream_off * sizeof (codestream_buf[0]))
105 #define codestream_peek() \
106 (codestream_cnt == 0 \
107 ? codestream_fill (1) \
108 : codestream_buf[codestream_off])
109 #define codestream_get() \
110 (codestream_cnt-- == 0 \
111 ? codestream_fill (0) \
112 : codestream_buf[codestream_off++])
115 codestream_fill (int peek_flag
)
117 codestream_addr
= codestream_next_addr
;
118 codestream_next_addr
+= CODESTREAM_BUFSIZ
* sizeof (codestream_buf
[0]);
120 codestream_cnt
= CODESTREAM_BUFSIZ
;
121 read_memory (codestream_addr
, (char *) codestream_buf
,
122 CODESTREAM_BUFSIZ
* sizeof (codestream_buf
[0]));
123 /* FIXME: check return code? */
126 /* Handle byte order differences -> convert to host byte ordering. */
129 for (i
= 0; i
< CODESTREAM_BUFSIZ
; i
++)
131 extract_unsigned_integer (&codestream_buf
[i
],
132 sizeof (codestream_buf
[i
]));
136 return codestream_peek ();
138 return codestream_get ();
142 codestream_seek (CORE_ADDR place
)
144 codestream_next_addr
= place
/ CODESTREAM_BUFSIZ
;
145 codestream_next_addr
*= CODESTREAM_BUFSIZ
;
148 while (codestream_tell () != place
)
152 /* This function is currently unused but leave in for now. */
155 codestream_read (unsigned int *buf
, int count
)
160 for (i
= 0; i
< count
; i
++)
161 *p
++ = codestream_get ();
164 /* Set up prologue scanning and return the first insn. */
167 setup_prologue_scan (CORE_ADDR pc
)
171 codestream_seek (pc
);
172 insn
= codestream_get ();
178 * Find & return amount a local space allocated, and advance codestream to
179 * first register push (if any).
180 * If entry sequence doesn't make sense, return -1, and leave
181 * codestream pointer random.
185 arc_get_frame_setup (CORE_ADDR pc
)
188 /* Size of frame or -1 if unrecognizable prologue. */
190 /* An initial "sub sp,sp,N" may or may not be for a stdarg fn. */
191 int maybe_stdarg_decr
= -1;
193 insn
= setup_prologue_scan (pc
);
195 /* The authority for what appears here is the home-grown ABI.
196 The most recent version is 1.2. */
198 /* First insn may be "sub sp,sp,N" if stdarg fn. */
199 if ((insn
& BUILD_INSN (-1, -1, -1, -1, 0))
200 == BUILD_INSN (10, SP_REGNUM
, SP_REGNUM
, SHIMM_REGNUM
, 0))
202 maybe_stdarg_decr
= X_D (insn
);
203 insn
= codestream_get ();
206 if ((insn
& BUILD_INSN (-1, 0, -1, -1, -1)) /* st blink,[sp,4] */
207 == BUILD_INSN (2, 0, SP_REGNUM
, BLINK_REGNUM
, 4))
209 insn
= codestream_get ();
210 /* Frame may not be necessary, even though blink is saved.
211 At least this is something we recognize. */
215 if ((insn
& BUILD_INSN (-1, 0, -1, -1, -1)) /* st fp,[sp] */
216 == BUILD_INSN (2, 0, SP_REGNUM
, FP_REGNUM
, 0))
218 insn
= codestream_get ();
219 if ((insn
& BUILD_INSN (-1, -1, -1, -1, 0))
220 != BUILD_INSN (12, FP_REGNUM
, SP_REGNUM
, SP_REGNUM
, 0))
223 /* Check for stack adjustment sub sp,sp,N. */
224 insn
= codestream_peek ();
225 if ((insn
& BUILD_INSN (-1, -1, -1, 0, 0))
226 == BUILD_INSN (10, SP_REGNUM
, SP_REGNUM
, 0, 0))
228 if (LIMM_P (X_C (insn
)))
229 frame_size
= codestream_get ();
230 else if (SHIMM_P (X_C (insn
)))
231 frame_size
= X_D (insn
);
239 /* This sequence is used to get the address of the return
240 buffer for a function that returns a structure. */
241 insn
= codestream_peek ();
242 if ((insn
& OPMASK
) == 0x60000000)
252 /* If we found a "sub sp,sp,N" and nothing else, it may or may not be a
253 stdarg fn. The stdarg decrement is not treated as part of the frame size,
254 so we have a dilemma: what do we return? For now, if we get a
255 "sub sp,sp,N" and nothing else assume this isn't a stdarg fn. One way
256 to fix this completely would be to add a bit to the function descriptor
257 that says the function is a stdarg function. */
259 if (frame_size
< 0 && maybe_stdarg_decr
> 0)
260 return maybe_stdarg_decr
;
264 /* Given a pc value, skip it forward past the function prologue by
265 disassembling instructions that appear to be a prologue.
267 If FRAMELESS_P is set, we are only testing to see if the function
268 is frameless. If it is a frameless function, return PC unchanged.
269 This allows a quicker answer. */
272 arc_skip_prologue (CORE_ADDR pc
, int frameless_p
)
277 if ((frame_size
= arc_get_frame_setup (pc
)) < 0)
281 return frame_size
== 0 ? pc
: codestream_tell ();
283 /* Skip over register saves. */
284 for (i
= 0; i
< 8; i
++)
286 insn
= codestream_peek ();
287 if ((insn
& BUILD_INSN (-1, 0, -1, 0, 0))
288 != BUILD_INSN (2, 0, SP_REGNUM
, 0, 0))
289 break; /* not st insn */
290 if (!ARC_CALL_SAVED_REG (X_C (insn
)))
295 return codestream_tell ();
298 /* Return the return address for a frame.
299 This is used to implement FRAME_SAVED_PC.
300 This is taken from frameless_look_for_prologue. */
303 arc_frame_saved_pc (struct frame_info
*frame
)
305 CORE_ADDR func_start
;
308 func_start
= get_pc_function_start (frame
->pc
) + FUNCTION_START_OFFSET
;
312 return ARC_PC_TO_REAL_ADDRESS (read_memory_integer (FRAME_FP (frame
) + 4, 4));
315 /* The authority for what appears here is the home-grown ABI.
316 The most recent version is 1.2. */
318 insn
= setup_prologue_scan (func_start
);
320 /* First insn may be "sub sp,sp,N" if stdarg fn. */
321 if ((insn
& BUILD_INSN (-1, -1, -1, -1, 0))
322 == BUILD_INSN (10, SP_REGNUM
, SP_REGNUM
, SHIMM_REGNUM
, 0))
323 insn
= codestream_get ();
325 /* If the next insn is "st blink,[sp,4]" we can get blink from there.
326 Otherwise this is a leaf function and we can use blink. Note that
327 this still allows for the case where a leaf function saves/clobbers/
330 if ((insn
& BUILD_INSN (-1, 0, -1, -1, -1)) /* st blink,[sp,4] */
331 != BUILD_INSN (2, 0, SP_REGNUM
, BLINK_REGNUM
, 4))
332 return ARC_PC_TO_REAL_ADDRESS (read_register (BLINK_REGNUM
));
334 return ARC_PC_TO_REAL_ADDRESS (read_memory_integer (FRAME_FP (frame
) + 4, 4));
338 * Parse the first few instructions of the function to see
339 * what registers were stored.
341 * The startup sequence can be at the start of the function.
342 * 'st blink,[sp+4], st fp,[sp], mov fp,sp'
344 * Local space is allocated just below by sub sp,sp,nnn.
345 * Next, the registers used by this function are stored (as offsets from sp).
349 frame_find_saved_regs (struct frame_info
*fip
, struct frame_saved_regs
*fsrp
)
353 CORE_ADDR dummy_bottom
;
355 int i
, regnum
, offset
;
357 memset (fsrp
, 0, sizeof *fsrp
);
359 /* If frame is the end of a dummy, compute where the beginning would be. */
360 dummy_bottom
= fip
->frame
- 4 - REGISTER_BYTES
- CALL_DUMMY_LENGTH
;
362 /* Check if the PC is in the stack, in a dummy frame. */
363 if (dummy_bottom
<= fip
->pc
&& fip
->pc
<= fip
->frame
)
365 /* all regs were saved by push_call_dummy () */
367 for (i
= 0; i
< NUM_REGS
; i
++)
369 adr
-= REGISTER_RAW_SIZE (i
);
375 locals
= arc_get_frame_setup (get_pc_function_start (fip
->pc
));
379 /* Set `adr' to the value of `sp'. */
380 adr
= fip
->frame
- locals
;
381 for (i
= 0; i
< 8; i
++)
383 insn
= codestream_get ();
384 if ((insn
& BUILD_INSN (-1, 0, -1, 0, 0))
385 != BUILD_INSN (2, 0, SP_REGNUM
, 0, 0))
389 fsrp
->regs
[regnum
] = adr
+ offset
;
393 fsrp
->regs
[PC_REGNUM
] = fip
->frame
+ 4;
394 fsrp
->regs
[FP_REGNUM
] = fip
->frame
;
398 arc_push_dummy_frame (void)
400 CORE_ADDR sp
= read_register (SP_REGNUM
);
402 char regbuf
[MAX_REGISTER_RAW_SIZE
];
404 read_register_gen (PC_REGNUM
, regbuf
);
405 write_memory (sp
+ 4, regbuf
, REGISTER_SIZE
);
406 read_register_gen (FP_REGNUM
, regbuf
);
407 write_memory (sp
, regbuf
, REGISTER_SIZE
);
408 write_register (FP_REGNUM
, sp
);
409 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
411 read_register_gen (regnum
, regbuf
);
412 sp
= push_bytes (sp
, regbuf
, REGISTER_RAW_SIZE (regnum
));
414 sp
+= (2 * REGISTER_SIZE
);
415 write_register (SP_REGNUM
, sp
);
421 struct frame_info
*frame
= get_current_frame ();
424 struct frame_saved_regs fsr
;
425 char regbuf
[MAX_REGISTER_RAW_SIZE
];
427 fp
= FRAME_FP (frame
);
428 get_frame_saved_regs (frame
, &fsr
);
429 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
432 adr
= fsr
.regs
[regnum
];
435 read_memory (adr
, regbuf
, REGISTER_RAW_SIZE (regnum
));
436 write_register_bytes (REGISTER_BYTE (regnum
), regbuf
,
437 REGISTER_RAW_SIZE (regnum
));
440 write_register (FP_REGNUM
, read_memory_integer (fp
, 4));
441 write_register (PC_REGNUM
, read_memory_integer (fp
+ 4, 4));
442 write_register (SP_REGNUM
, fp
+ 8);
443 flush_cached_frames ();
446 /* Simulate single-step. */
450 NORMAL4
, /* a normal 4 byte insn */
451 NORMAL8
, /* a normal 8 byte insn */
452 BRANCH4
, /* a 4 byte branch insn, including ones without delay slots */
453 BRANCH8
, /* an 8 byte branch insn, including ones with delay slots */
457 /* Return the type of INSN and store in TARGET the destination address of a
458 branch if this is one. */
459 /* ??? Need to verify all cases are properly handled. */
462 get_insn_type (unsigned long insn
, CORE_ADDR pc
, CORE_ADDR
*target
)
470 case 2: /* load/store insns */
471 if (LIMM_P (X_A (insn
))
472 || LIMM_P (X_B (insn
))
473 || LIMM_P (X_C (insn
)))
478 case 6: /* branch insns */
479 *target
= pc
+ 4 + X_L (insn
);
480 /* ??? It isn't clear that this is always the right answer.
481 The problem occurs when the next insn is an 8 byte insn. If the
482 branch is conditional there's no worry as there shouldn't be an 8
483 byte insn following. The programmer may be cheating if s/he knows
484 the branch will never be taken, but we don't deal with that.
485 Note that the programmer is also allowed to play games by putting
486 an insn with long immediate data in the delay slot and then duplicate
487 the long immediate data at the branch target. Ugh! */
491 case 7: /* jump insns */
492 if (LIMM_P (X_B (insn
)))
494 limm
= read_memory_integer (pc
+ 4, 4);
495 *target
= ARC_PC_TO_REAL_ADDRESS (limm
);
498 if (SHIMM_P (X_B (insn
)))
499 *target
= ARC_PC_TO_REAL_ADDRESS (X_D (insn
));
501 *target
= ARC_PC_TO_REAL_ADDRESS (read_register (X_B (insn
)));
502 if (X_Q (insn
) == 0 && X_N (insn
) == 0)
505 default: /* arithmetic insns, etc. */
506 if (LIMM_P (X_A (insn
))
507 || LIMM_P (X_B (insn
))
508 || LIMM_P (X_C (insn
)))
514 /* single_step() is called just before we want to resume the inferior, if we
515 want to single-step it but there is no hardware or kernel single-step
516 support. We find all the possible targets of the coming instruction and
519 single_step is also called just after the inferior stops. If we had
520 set up a simulated single-step, we undo our damage. */
523 arc_software_single_step (enum target_signal ignore
, /* sig but we don't need it */
524 int insert_breakpoints_p
)
526 static CORE_ADDR next_pc
, target
;
528 typedef char binsn_quantum
[BREAKPOINT_MAX
];
529 static binsn_quantum break_mem
[2];
531 if (insert_breakpoints_p
)
537 pc
= read_register (PC_REGNUM
);
538 insn
= read_memory_integer (pc
, 4);
539 type
= get_insn_type (insn
, pc
, &target
);
541 /* Always set a breakpoint for the insn after the branch. */
542 next_pc
= pc
+ ((type
== NORMAL8
|| type
== BRANCH8
) ? 8 : 4);
543 target_insert_breakpoint (next_pc
, break_mem
[0]);
547 if ((type
== BRANCH4
|| type
== BRANCH8
)
548 /* Watch out for branches to the following location.
549 We just stored a breakpoint there and another call to
550 target_insert_breakpoint will think the real insn is the
551 breakpoint we just stored there. */
552 && target
!= next_pc
)
555 target_insert_breakpoint (target
, break_mem
[1]);
561 /* Remove breakpoints. */
562 target_remove_breakpoint (next_pc
, break_mem
[0]);
565 target_remove_breakpoint (target
, break_mem
[1]);
568 stop_pc
-= DECR_PC_AFTER_BREAK
;
573 #ifdef GET_LONGJMP_TARGET
574 /* Figure out where the longjmp will land. Slurp the args out of the stack.
575 We expect the first arg to be a pointer to the jmp_buf structure from which
576 we extract the pc (JB_PC) that we will land at. The pc is copied into PC.
577 This routine returns true on success. */
580 get_longjmp_target (CORE_ADDR
*pc
)
582 char buf
[TARGET_PTR_BIT
/ TARGET_CHAR_BIT
];
583 CORE_ADDR sp
, jb_addr
;
585 sp
= read_register (SP_REGNUM
);
587 if (target_read_memory (sp
+ SP_ARG0
, /* Offset of first arg on stack */
589 TARGET_PTR_BIT
/ TARGET_CHAR_BIT
))
592 jb_addr
= extract_address (buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
594 if (target_read_memory (jb_addr
+ JB_PC
* JB_ELEMENT_SIZE
, buf
,
595 TARGET_PTR_BIT
/ TARGET_CHAR_BIT
))
598 *pc
= extract_address (buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
602 #endif /* GET_LONGJMP_TARGET */
604 /* Disassemble one instruction. */
607 arc_print_insn (bfd_vma vma
, disassemble_info
*info
)
609 static int current_mach
;
610 static int current_endian
;
611 static disassembler_ftype current_disasm
;
613 if (current_disasm
== NULL
614 || arc_bfd_mach_type
!= current_mach
615 || TARGET_BYTE_ORDER
!= current_endian
)
617 current_mach
= arc_bfd_mach_type
;
618 current_endian
= TARGET_BYTE_ORDER
;
619 current_disasm
= arc_get_disassembler (NULL
);
622 return (*current_disasm
) (vma
, info
);
625 /* Command to set cpu type. */
628 arc_set_cpu_type_command (char *args
, int from_tty
)
632 if (tmp_arc_cpu_type
== NULL
|| *tmp_arc_cpu_type
== '\0')
634 printf_unfiltered ("The known ARC cpu types are as follows:\n");
635 for (i
= 0; arc_cpu_type_table
[i
].name
!= NULL
; ++i
)
636 printf_unfiltered ("%s\n", arc_cpu_type_table
[i
].name
);
638 /* Restore the value. */
639 tmp_arc_cpu_type
= strsave (arc_cpu_type
);
644 if (!arc_set_cpu_type (tmp_arc_cpu_type
))
646 error ("Unknown cpu type `%s'.", tmp_arc_cpu_type
);
647 /* Restore its value. */
648 tmp_arc_cpu_type
= strsave (arc_cpu_type
);
653 arc_show_cpu_type_command (char *args
, int from_tty
)
657 /* Modify the actual cpu type.
658 Result is a boolean indicating success. */
661 arc_set_cpu_type (char *str
)
668 for (i
= 0; arc_cpu_type_table
[i
].name
!= NULL
; ++i
)
670 if (strcasecmp (str
, arc_cpu_type_table
[i
].name
) == 0)
673 arc_bfd_mach_type
= arc_cpu_type_table
[i
].value
;
682 _initialize_arc_tdep (void)
684 struct cmd_list_element
*c
;
686 c
= add_set_cmd ("cpu", class_support
, var_string_noescape
,
687 (char *) &tmp_arc_cpu_type
,
688 "Set the type of ARC cpu in use.\n\
689 This command has two purposes. In a multi-cpu system it lets one\n\
690 change the cpu being debugged. It also gives one access to\n\
691 cpu-type-specific registers and recognize cpu-type-specific instructions.\
694 c
->function
.cfunc
= arc_set_cpu_type_command
;
695 c
= add_show_from_set (c
, &showlist
);
696 c
->function
.cfunc
= arc_show_cpu_type_command
;
698 /* We have to use strsave here because the `set' command frees it before
699 setting a new value. */
700 tmp_arc_cpu_type
= strsave (DEFAULT_ARC_CPU_TYPE
);
701 arc_set_cpu_type (tmp_arc_cpu_type
);
703 c
= add_set_cmd ("displaypipeline", class_support
, var_zinteger
,
704 (char *) &display_pipeline_p
,
705 "Set pipeline display (simulator only).\n\
706 When enabled, the state of the pipeline after each cycle is displayed.",
708 c
= add_show_from_set (c
, &showlist
);
710 c
= add_set_cmd ("debugpipeline", class_support
, var_zinteger
,
711 (char *) &debug_pipeline_p
,
712 "Set pipeline debug display (simulator only).\n\
713 When enabled, debugging information about the pipeline is displayed.",
715 c
= add_show_from_set (c
, &showlist
);
717 c
= add_set_cmd ("cputimer", class_support
, var_zinteger
,
719 "Set maximum cycle count (simulator only).\n\
720 Control will return to gdb if the timer expires.\n\
721 A negative value disables the timer.",
723 c
= add_show_from_set (c
, &showlist
);
725 tm_print_insn
= arc_print_insn
;