1 /* Target dependent code for ARC arhitecture, for GDB.
3 Copyright 2005-2017 Free Software Foundation, Inc.
4 Contributed by Synopsys Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 /* GDB header files. */
23 #include "arch-utils.h"
25 #include "dwarf2-frame.h"
26 #include "frame-base.h"
27 #include "frame-unwind.h"
31 #include "trad-frame.h"
33 /* ARC header files. */
34 #include "opcode/arc.h"
35 #include "opcodes/arc-dis.h"
38 /* Standard headers. */
41 /* Default target descriptions. */
42 #include "features/arc-v2.c"
43 #include "features/arc-arcompact.c"
45 /* The frame unwind cache for the ARC. Current structure is a stub, because
46 it should be filled in during the prologue analysis. */
48 struct arc_frame_cache
50 /* The stack pointer at the time this frame was created; i.e. the caller's
51 stack pointer when this function was called. It is used to identify this
55 /* Store addresses for registers saved in prologue. */
56 struct trad_frame_saved_reg
*saved_regs
;
59 /* Global debug flag. */
63 /* List of "maintenance print arc" commands. */
65 static struct cmd_list_element
*maintenance_print_arc_list
= NULL
;
67 /* XML target description features. */
69 static const char core_v2_feature_name
[] = "org.gnu.gdb.arc.core.v2";
71 core_reduced_v2_feature_name
[] = "org.gnu.gdb.arc.core-reduced.v2";
73 core_arcompact_feature_name
[] = "org.gnu.gdb.arc.core.arcompact";
74 static const char aux_minimal_feature_name
[] = "org.gnu.gdb.arc.aux-minimal";
76 /* XML target description known registers. */
78 static const char *const core_v2_register_names
[] = {
79 "r0", "r1", "r2", "r3",
80 "r4", "r5", "r6", "r7",
81 "r8", "r9", "r10", "r11",
82 "r12", "r13", "r14", "r15",
83 "r16", "r17", "r18", "r19",
84 "r20", "r21", "r22", "r23",
85 "r24", "r25", "gp", "fp",
86 "sp", "ilink", "r30", "blink",
87 "r32", "r33", "r34", "r35",
88 "r36", "r37", "r38", "r39",
89 "r40", "r41", "r42", "r43",
90 "r44", "r45", "r46", "r47",
91 "r48", "r49", "r50", "r51",
92 "r52", "r53", "r54", "r55",
93 "r56", "r57", "accl", "acch",
94 "lp_count", "reserved", "limm", "pcl",
97 static const char *const aux_minimal_register_names
[] = {
101 static const char *const core_arcompact_register_names
[] = {
102 "r0", "r1", "r2", "r3",
103 "r4", "r5", "r6", "r7",
104 "r8", "r9", "r10", "r11",
105 "r12", "r13", "r14", "r15",
106 "r16", "r17", "r18", "r19",
107 "r20", "r21", "r22", "r23",
108 "r24", "r25", "gp", "fp",
109 "sp", "ilink1", "ilink2", "blink",
110 "r32", "r33", "r34", "r35",
111 "r36", "r37", "r38", "r39",
112 "r40", "r41", "r42", "r43",
113 "r44", "r45", "r46", "r47",
114 "r48", "r49", "r50", "r51",
115 "r52", "r53", "r54", "r55",
116 "r56", "r57", "r58", "r59",
117 "lp_count", "reserved", "limm", "pcl",
120 /* Returns an unsigned value of OPERAND_NUM in instruction INSN.
121 For relative branch instructions returned value is an offset, not an actual
125 arc_insn_get_operand_value (const struct arc_instruction
&insn
,
126 unsigned int operand_num
)
128 switch (insn
.operands
[operand_num
].kind
)
130 case ARC_OPERAND_KIND_LIMM
:
131 gdb_assert (insn
.limm_p
);
132 return insn
.limm_value
;
133 case ARC_OPERAND_KIND_SHIMM
:
134 return insn
.operands
[operand_num
].value
;
136 /* Value in instruction is a register number. */
137 struct regcache
*regcache
= get_current_regcache ();
139 regcache_cooked_read_unsigned (regcache
,
140 insn
.operands
[operand_num
].value
,
146 /* Like arc_insn_get_operand_value, but returns a signed value. */
149 arc_insn_get_operand_value_signed (const struct arc_instruction
&insn
,
150 unsigned int operand_num
)
152 switch (insn
.operands
[operand_num
].kind
)
154 case ARC_OPERAND_KIND_LIMM
:
155 gdb_assert (insn
.limm_p
);
156 /* Convert unsigned raw value to signed one. This assumes 2's
157 complement arithmetic, but so is the LONG_MIN value from generic
158 defs.h and that assumption is true for ARC. */
159 gdb_static_assert (sizeof (insn
.limm_value
) == sizeof (int));
160 return (((LONGEST
) insn
.limm_value
) ^ INT_MIN
) - INT_MIN
;
161 case ARC_OPERAND_KIND_SHIMM
:
162 /* Sign conversion has been done by binutils. */
163 return insn
.operands
[operand_num
].value
;
165 /* Value in instruction is a register number. */
166 struct regcache
*regcache
= get_current_regcache ();
168 regcache_cooked_read_signed (regcache
,
169 insn
.operands
[operand_num
].value
,
175 /* Get register with base address of memory operation. */
178 arc_insn_get_memory_base_reg (const struct arc_instruction
&insn
)
180 /* POP_S and PUSH_S have SP as an implicit argument in a disassembler. */
181 if (insn
.insn_class
== PUSH
|| insn
.insn_class
== POP
)
182 return ARC_SP_REGNUM
;
184 gdb_assert (insn
.insn_class
== LOAD
|| insn
.insn_class
== STORE
);
186 /* Other instructions all have at least two operands: operand 0 is data,
187 operand 1 is address. Operand 2 is offset from address. However, see
188 comment to arc_instruction.operands - in some cases, third operand may be
189 missing, namely if it is 0. */
190 gdb_assert (insn
.operands_count
>= 2);
191 return insn
.operands
[1].value
;
194 /* Get offset of a memory operation INSN. */
197 arc_insn_get_memory_offset (const struct arc_instruction
&insn
)
199 /* POP_S and PUSH_S have offset as an implicit argument in a
201 if (insn
.insn_class
== POP
)
203 else if (insn
.insn_class
== PUSH
)
206 gdb_assert (insn
.insn_class
== LOAD
|| insn
.insn_class
== STORE
);
208 /* Other instructions all have at least two operands: operand 0 is data,
209 operand 1 is address. Operand 2 is offset from address. However, see
210 comment to arc_instruction.operands - in some cases, third operand may be
211 missing, namely if it is 0. */
212 if (insn
.operands_count
< 3)
215 CORE_ADDR value
= arc_insn_get_operand_value (insn
, 2);
216 /* Handle scaling. */
217 if (insn
.writeback_mode
== ARC_WRITEBACK_AS
)
219 /* Byte data size is not valid for AS. Halfword means shift by 1 bit.
220 Word and double word means shift by 2 bits. */
221 gdb_assert (insn
.data_size_mode
!= ARC_SCALING_B
);
222 if (insn
.data_size_mode
== ARC_SCALING_H
)
230 /* Functions are sorted in the order as they are used in the
231 _initialize_arc_tdep (), which uses the same order as gdbarch.h. Static
232 functions are defined before the first invocation. */
235 arc_insn_get_branch_target (const struct arc_instruction
&insn
)
237 gdb_assert (insn
.is_control_flow
);
239 /* BI [c]: PC = nextPC + (c << 2). */
240 if (insn
.insn_class
== BI
)
242 ULONGEST reg_value
= arc_insn_get_operand_value (insn
, 0);
243 return arc_insn_get_linear_next_pc (insn
) + (reg_value
<< 2);
245 /* BIH [c]: PC = nextPC + (c << 1). */
246 else if (insn
.insn_class
== BIH
)
248 ULONGEST reg_value
= arc_insn_get_operand_value (insn
, 0);
249 return arc_insn_get_linear_next_pc (insn
) + (reg_value
<< 1);
252 /* JLI and EI depend on optional AUX registers. Not supported right now. */
253 else if (insn
.insn_class
== JLI
)
255 fprintf_unfiltered (gdb_stderr
,
256 "JLI_S instruction is not supported by the GDB.");
259 else if (insn
.insn_class
== EI
)
261 fprintf_unfiltered (gdb_stderr
,
262 "EI_S instruction is not supported by the GDB.");
265 /* LEAVE_S: PC = BLINK. */
266 else if (insn
.insn_class
== LEAVE
)
268 struct regcache
*regcache
= get_current_regcache ();
270 regcache_cooked_read_unsigned (regcache
, ARC_BLINK_REGNUM
, &value
);
273 /* BBIT0/1, BRcc: PC = currentPC + operand. */
274 else if (insn
.insn_class
== BBIT0
|| insn
.insn_class
== BBIT1
275 || insn
.insn_class
== BRCC
)
277 /* Most instructions has branch target as their sole argument. However
278 conditional brcc/bbit has it as a third operand. */
279 CORE_ADDR pcrel_addr
= arc_insn_get_operand_value (insn
, 2);
281 /* Offset is relative to the 4-byte aligned address of the current
282 instruction, hence last two bits should be truncated. */
283 return pcrel_addr
+ align_down (insn
.address
, 4);
285 /* B, Bcc, BL, BLcc, LP, LPcc: PC = currentPC + operand. */
286 else if (insn
.insn_class
== BRANCH
|| insn
.insn_class
== LOOP
)
288 CORE_ADDR pcrel_addr
= arc_insn_get_operand_value (insn
, 0);
290 /* Offset is relative to the 4-byte aligned address of the current
291 instruction, hence last two bits should be truncated. */
292 return pcrel_addr
+ align_down (insn
.address
, 4);
294 /* J, Jcc, JL, JLcc: PC = operand. */
295 else if (insn
.insn_class
== JUMP
)
297 /* All jumps are single-operand. */
298 return arc_insn_get_operand_value (insn
, 0);
301 /* This is some new and unknown instruction. */
302 gdb_assert_not_reached ("Unknown branch instruction.");
305 /* Dump INSN into gdb_stdlog. */
308 arc_insn_dump (const struct arc_instruction
&insn
)
310 struct gdbarch
*gdbarch
= target_gdbarch ();
312 arc_print ("Dumping arc_instruction at %s\n",
313 paddress (gdbarch
, insn
.address
));
314 arc_print ("\tlength = %u\n", insn
.length
);
318 arc_print ("\tThis is not a valid ARC instruction.\n");
322 arc_print ("\tlength_with_limm = %u\n", insn
.length
+ (insn
.limm_p
? 4 : 0));
323 arc_print ("\tcc = 0x%x\n", insn
.condition_code
);
324 arc_print ("\tinsn_class = %u\n", insn
.insn_class
);
325 arc_print ("\tis_control_flow = %i\n", insn
.is_control_flow
);
326 arc_print ("\thas_delay_slot = %i\n", insn
.has_delay_slot
);
328 CORE_ADDR next_pc
= arc_insn_get_linear_next_pc (insn
);
329 arc_print ("\tlinear_next_pc = %s\n", paddress (gdbarch
, next_pc
));
331 if (insn
.is_control_flow
)
333 CORE_ADDR t
= arc_insn_get_branch_target (insn
);
334 arc_print ("\tbranch_target = %s\n", paddress (gdbarch
, t
));
337 arc_print ("\tlimm_p = %i\n", insn
.limm_p
);
339 arc_print ("\tlimm_value = 0x%08x\n", insn
.limm_value
);
341 if (insn
.insn_class
== STORE
|| insn
.insn_class
== LOAD
342 || insn
.insn_class
== PUSH
|| insn
.insn_class
== POP
)
344 arc_print ("\twriteback_mode = %u\n", insn
.writeback_mode
);
345 arc_print ("\tdata_size_mode = %u\n", insn
.data_size_mode
);
346 arc_print ("\tmemory_base_register = %s\n",
347 gdbarch_register_name (gdbarch
,
348 arc_insn_get_memory_base_reg (insn
)));
349 /* get_memory_offset returns an unsigned CORE_ADDR, but treat it as a
350 LONGEST for a nicer representation. */
351 arc_print ("\taddr_offset = %s\n",
352 plongest (arc_insn_get_memory_offset (insn
)));
355 arc_print ("\toperands_count = %u\n", insn
.operands_count
);
356 for (unsigned int i
= 0; i
< insn
.operands_count
; ++i
)
358 int is_reg
= (insn
.operands
[i
].kind
== ARC_OPERAND_KIND_REG
);
360 arc_print ("\toperand[%u] = {\n", i
);
361 arc_print ("\t\tis_reg = %i\n", is_reg
);
363 arc_print ("\t\tregister = %s\n",
364 gdbarch_register_name (gdbarch
, insn
.operands
[i
].value
));
365 /* Don't know if this value is signed or not, so print both
366 representations. This tends to look quite ugly, especially for big
368 arc_print ("\t\tunsigned value = %s\n",
369 pulongest (arc_insn_get_operand_value (insn
, i
)));
370 arc_print ("\t\tsigned value = %s\n",
371 plongest (arc_insn_get_operand_value_signed (insn
, i
)));
377 arc_insn_get_linear_next_pc (const struct arc_instruction
&insn
)
379 /* In ARC long immediate is always 4 bytes. */
380 return (insn
.address
+ insn
.length
+ (insn
.limm_p
? 4 : 0));
383 /* Implement the "write_pc" gdbarch method.
385 In ARC PC register is a normal register so in most cases setting PC value
386 is a straightforward process: debugger just writes PC value. However it
387 gets trickier in case when current instruction is an instruction in delay
388 slot. In this case CPU will execute instruction at current PC value, then
389 will set PC to the current value of BTA register; also current instruction
390 cannot be branch/jump and some of the other instruction types. Thus if
391 debugger would try to just change PC value in this case, this instruction
392 will get executed, but then core will "jump" to the original branch target.
394 Whether current instruction is a delay-slot instruction or not is indicated
395 by DE bit in STATUS32 register indicates if current instruction is a delay
396 slot instruction. This bit is writable by debug host, which allows debug
397 host to prevent core from jumping after the delay slot instruction. It
398 also works in another direction: setting this bit will make core to treat
399 any current instructions as a delay slot instruction and to set PC to the
400 current value of BTA register.
402 To workaround issues with changing PC register while in delay slot
403 instruction, debugger should check for the STATUS32.DE bit and reset it if
404 it is set. No other change is required in this function. Most common
405 case, where this function might be required is calling inferior functions
406 from debugger. Generic GDB logic handles this pretty well: current values
407 of registers are stored, value of PC is changed (that is the job of this
408 function), and after inferior function is executed, GDB restores all
409 registers, include BTA and STATUS32, which also means that core is returned
410 to its original state of being halted on delay slot instructions.
412 This method is useless for ARC 600, because it doesn't have externally
413 exposed BTA register. In the case of ARC 600 it is impossible to restore
414 core to its state in all occasions thus core should never be halted (from
415 the perspective of debugger host) in the delay slot. */
418 arc_write_pc (struct regcache
*regcache
, CORE_ADDR new_pc
)
420 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
423 debug_printf ("arc: Writing PC, new value=%s\n",
424 paddress (gdbarch
, new_pc
));
426 regcache_cooked_write_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
),
430 regcache_cooked_read_unsigned (regcache
, gdbarch_ps_regnum (gdbarch
),
433 /* Mask for DE bit is 0x40. */
438 debug_printf ("arc: Changing PC while in delay slot. Will "
439 "reset STATUS32.DE bit to zero. Value of STATUS32 "
440 "register is 0x%s\n",
441 phex (status32
, ARC_REGISTER_SIZE
));
444 /* Reset bit and write to the cache. */
446 regcache_cooked_write_unsigned (regcache
, gdbarch_ps_regnum (gdbarch
),
451 /* Implement the "virtual_frame_pointer" gdbarch method.
453 According to ABI the FP (r27) is used to point to the middle of the current
454 stack frame, just below the saved FP and before local variables, register
455 spill area and outgoing args. However for optimization levels above O2 and
456 in any case in leaf functions, the frame pointer is usually not set at all.
457 The exception being when handling nested functions.
459 We use this function to return a "virtual" frame pointer, marking the start
460 of the current stack frame as a register-offset pair. If the FP is not
461 being used, then it should return SP, with an offset of the frame size.
463 The current implementation doesn't actually know the frame size, nor
464 whether the FP is actually being used, so for now we just return SP and an
465 offset of zero. This is no worse than other architectures, but is needed
466 to avoid assertion failures.
468 TODO: Can we determine the frame size to get a correct offset?
470 PC is a program counter where we need the virtual FP. REG_PTR is the base
471 register used for the virtual FP. OFFSET_PTR is the offset used for the
475 arc_virtual_frame_pointer (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
476 int *reg_ptr
, LONGEST
*offset_ptr
)
478 *reg_ptr
= gdbarch_sp_regnum (gdbarch
);
482 /* Implement the "dummy_id" gdbarch method.
484 Tear down a dummy frame created by arc_push_dummy_call (). This data has
485 to be constructed manually from the data in our hand. The stack pointer
486 and program counter can be obtained from the frame info. */
488 static struct frame_id
489 arc_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
491 return frame_id_build (get_frame_sp (this_frame
),
492 get_frame_pc (this_frame
));
495 /* Implement the "push_dummy_call" gdbarch method.
499 This shows the layout of the stack frame for the general case of a
500 function call; a given function might not have a variable number of
501 arguments or local variables, or might not save any registers, so it would
502 not have the corresponding frame areas. Additionally, a leaf function
503 (i.e. one which calls no other functions) does not need to save the
504 contents of the BLINK register (which holds its return address), and a
505 function might not have a frame pointer.
507 The stack grows downward, so SP points below FP in memory; SP always
508 points to the last used word on the stack, not the first one.
511 | arg word N | | caller's
515 old SP ---> +-----------------------+ --+
519 | including fp, blink | |
521 new FP ---> +-----------------------+ | frame
531 new SP ---> +-----------------------+ --+
540 The list of arguments to be passed to a function is considered to be a
541 sequence of _N_ words (as though all the parameters were stored in order in
542 memory with each parameter occupying an integral number of words). Words
543 1..8 are passed in registers 0..7; if the function has more than 8 words of
544 arguments then words 9..@em N are passed on the stack in the caller's frame.
546 If the function has a variable number of arguments, e.g. it has a form such
547 as `function (p1, p2, ...);' and _P_ words are required to hold the values
548 of the named parameters (which are passed in registers 0..@em P -1), then
549 the remaining 8 - _P_ words passed in registers _P_..7 are spilled into the
550 top of the frame so that the anonymous parameter words occupy a continuous
553 Any arguments are already in target byte order. We just need to store
556 BP_ADDR is the return address where breakpoint must be placed. NARGS is
557 the number of arguments to the function. ARGS is the arguments values (in
558 target byte order). SP is the Current value of SP register. STRUCT_RETURN
559 is TRUE if structures are returned by the function. STRUCT_ADDR is the
560 hidden address for returning a struct. Returns SP of a new frame. */
563 arc_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
564 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
565 struct value
**args
, CORE_ADDR sp
, int struct_return
,
566 CORE_ADDR struct_addr
)
569 debug_printf ("arc: push_dummy_call (nargs = %d)\n", nargs
);
571 int arg_reg
= ARC_FIRST_ARG_REGNUM
;
573 /* Push the return address. */
574 regcache_cooked_write_unsigned (regcache
, ARC_BLINK_REGNUM
, bp_addr
);
576 /* Are we returning a value using a structure return instead of a normal
577 value return? If so, struct_addr is the address of the reserved space for
578 the return structure to be written on the stack, and that address is
579 passed to that function as a hidden first argument. */
582 /* Pass the return address in the first argument register. */
583 regcache_cooked_write_unsigned (regcache
, arg_reg
, struct_addr
);
586 debug_printf ("arc: struct return address %s passed in R%d",
587 print_core_address (gdbarch
, struct_addr
), arg_reg
);
594 unsigned int total_space
= 0;
596 /* How much space do the arguments occupy in total? Must round each
597 argument's size up to an integral number of words. */
598 for (int i
= 0; i
< nargs
; i
++)
600 unsigned int len
= TYPE_LENGTH (value_type (args
[i
]));
601 unsigned int space
= align_up (len
, 4);
603 total_space
+= space
;
606 debug_printf ("arc: arg %d: %u bytes -> %u\n", i
, len
, space
);
609 /* Allocate a buffer to hold a memory image of the arguments. */
610 gdb_byte
*memory_image
= XCNEWVEC (gdb_byte
, total_space
);
612 /* Now copy all of the arguments into the buffer, correctly aligned. */
613 gdb_byte
*data
= memory_image
;
614 for (int i
= 0; i
< nargs
; i
++)
616 unsigned int len
= TYPE_LENGTH (value_type (args
[i
]));
617 unsigned int space
= align_up (len
, 4);
619 memcpy (data
, value_contents (args
[i
]), (size_t) len
);
621 debug_printf ("arc: copying arg %d, val 0x%08x, len %d to mem\n",
622 i
, *((int *) value_contents (args
[i
])), len
);
627 /* Now load as much as possible of the memory image into registers. */
629 while (arg_reg
<= ARC_LAST_ARG_REGNUM
)
632 debug_printf ("arc: passing 0x%02x%02x%02x%02x in register R%d\n",
633 data
[0], data
[1], data
[2], data
[3], arg_reg
);
635 /* Note we don't use write_unsigned here, since that would convert
636 the byte order, but we are already in the correct byte order. */
637 regcache_cooked_write (regcache
, arg_reg
, data
);
639 data
+= ARC_REGISTER_SIZE
;
640 total_space
-= ARC_REGISTER_SIZE
;
642 /* All the data is now in registers. */
643 if (total_space
== 0)
649 /* If there is any data left, push it onto the stack (in a single write
654 debug_printf ("arc: passing %d bytes on stack\n", total_space
);
657 write_memory (sp
, data
, (int) total_space
);
660 xfree (memory_image
);
663 /* Finally, update the SP register. */
664 regcache_cooked_write_unsigned (regcache
, gdbarch_sp_regnum (gdbarch
), sp
);
669 /* Implement the "push_dummy_code" gdbarch method.
671 We don't actually push any code. We just identify where a breakpoint can
672 be inserted to which we are can return and the resume address where we
675 ARC does not necessarily have an executable stack, so we can't put the
676 return breakpoint there. Instead we put it at the entry point of the
677 function. This means the SP is unchanged.
679 SP is a current stack pointer FUNADDR is an address of the function to be
680 called. ARGS is arguments to pass. NARGS is a number of args to pass.
681 VALUE_TYPE is a type of value returned. REAL_PC is a resume address when
682 the function is called. BP_ADDR is an address where breakpoint should be
683 set. Returns the updated stack pointer. */
686 arc_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
687 struct value
**args
, int nargs
, struct type
*value_type
,
688 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
689 struct regcache
*regcache
)
692 *bp_addr
= entry_point_address ();
696 /* Implement the "cannot_fetch_register" gdbarch method. */
699 arc_cannot_fetch_register (struct gdbarch
*gdbarch
, int regnum
)
701 /* Assume that register is readable if it is unknown. LIMM and RESERVED are
702 not real registers, but specific register numbers. They are available as
703 regnums to align architectural register numbers with GDB internal regnums,
704 but they shouldn't appear in target descriptions generated by
708 case ARC_RESERVED_REGNUM
:
709 case ARC_LIMM_REGNUM
:
716 /* Implement the "cannot_store_register" gdbarch method. */
719 arc_cannot_store_register (struct gdbarch
*gdbarch
, int regnum
)
721 /* Assume that register is writable if it is unknown. See comment in
722 arc_cannot_fetch_register about LIMM and RESERVED. */
725 case ARC_RESERVED_REGNUM
:
726 case ARC_LIMM_REGNUM
:
734 /* Get the return value of a function from the registers/memory used to
735 return it, according to the convention used by the ABI - 4-bytes values are
736 in the R0, while 8-byte values are in the R0-R1.
738 TODO: This implementation ignores the case of "complex double", where
739 according to ABI, value is returned in the R0-R3 registers.
741 TYPE is a returned value's type. VALBUF is a buffer for the returned
745 arc_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
746 struct regcache
*regcache
, gdb_byte
*valbuf
)
748 unsigned int len
= TYPE_LENGTH (type
);
751 debug_printf ("arc: extract_return_value\n");
753 if (len
<= ARC_REGISTER_SIZE
)
757 /* Get the return value from one register. */
758 regcache_cooked_read_unsigned (regcache
, ARC_R0_REGNUM
, &val
);
759 store_unsigned_integer (valbuf
, (int) len
,
760 gdbarch_byte_order (gdbarch
), val
);
763 debug_printf ("arc: returning 0x%s\n", phex (val
, ARC_REGISTER_SIZE
));
765 else if (len
<= ARC_REGISTER_SIZE
* 2)
769 /* Get the return value from two registers. */
770 regcache_cooked_read_unsigned (regcache
, ARC_R0_REGNUM
, &low
);
771 regcache_cooked_read_unsigned (regcache
, ARC_R1_REGNUM
, &high
);
773 store_unsigned_integer (valbuf
, ARC_REGISTER_SIZE
,
774 gdbarch_byte_order (gdbarch
), low
);
775 store_unsigned_integer (valbuf
+ ARC_REGISTER_SIZE
,
776 (int) len
- ARC_REGISTER_SIZE
,
777 gdbarch_byte_order (gdbarch
), high
);
780 debug_printf ("arc: returning 0x%s%s\n",
781 phex (high
, ARC_REGISTER_SIZE
),
782 phex (low
, ARC_REGISTER_SIZE
));
785 error (_("arc: extract_return_value: type length %u too large"), len
);
789 /* Store the return value of a function into the registers/memory used to
790 return it, according to the convention used by the ABI.
792 TODO: This implementation ignores the case of "complex double", where
793 according to ABI, value is returned in the R0-R3 registers.
795 TYPE is a returned value's type. VALBUF is a buffer with the value to
799 arc_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
800 struct regcache
*regcache
, const gdb_byte
*valbuf
)
802 unsigned int len
= TYPE_LENGTH (type
);
805 debug_printf ("arc: store_return_value\n");
807 if (len
<= ARC_REGISTER_SIZE
)
811 /* Put the return value into one register. */
812 val
= extract_unsigned_integer (valbuf
, (int) len
,
813 gdbarch_byte_order (gdbarch
));
814 regcache_cooked_write_unsigned (regcache
, ARC_R0_REGNUM
, val
);
817 debug_printf ("arc: storing 0x%s\n", phex (val
, ARC_REGISTER_SIZE
));
819 else if (len
<= ARC_REGISTER_SIZE
* 2)
823 /* Put the return value into two registers. */
824 low
= extract_unsigned_integer (valbuf
, ARC_REGISTER_SIZE
,
825 gdbarch_byte_order (gdbarch
));
826 high
= extract_unsigned_integer (valbuf
+ ARC_REGISTER_SIZE
,
827 (int) len
- ARC_REGISTER_SIZE
,
828 gdbarch_byte_order (gdbarch
));
830 regcache_cooked_write_unsigned (regcache
, ARC_R0_REGNUM
, low
);
831 regcache_cooked_write_unsigned (regcache
, ARC_R1_REGNUM
, high
);
834 debug_printf ("arc: storing 0x%s%s\n",
835 phex (high
, ARC_REGISTER_SIZE
),
836 phex (low
, ARC_REGISTER_SIZE
));
839 error (_("arc_store_return_value: type length too large."));
842 /* Implement the "get_longjmp_target" gdbarch method. */
845 arc_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
848 debug_printf ("arc: get_longjmp_target\n");
850 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
851 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
852 int pc_offset
= tdep
->jb_pc
* ARC_REGISTER_SIZE
;
853 gdb_byte buf
[ARC_REGISTER_SIZE
];
854 CORE_ADDR jb_addr
= get_frame_register_unsigned (frame
, ARC_FIRST_ARG_REGNUM
);
856 if (target_read_memory (jb_addr
+ pc_offset
, buf
, ARC_REGISTER_SIZE
))
857 return 0; /* Failed to read from memory. */
859 *pc
= extract_unsigned_integer (buf
, ARC_REGISTER_SIZE
,
860 gdbarch_byte_order (gdbarch
));
864 /* Implement the "return_value" gdbarch method. */
866 static enum return_value_convention
867 arc_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
868 struct type
*valtype
, struct regcache
*regcache
,
869 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
871 /* If the return type is a struct, or a union, or would occupy more than two
872 registers, the ABI uses the "struct return convention": the calling
873 function passes a hidden first parameter to the callee (in R0). That
874 parameter is the address at which the value being returned should be
875 stored. Otherwise, the result is returned in registers. */
876 int is_struct_return
= (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
877 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
878 || TYPE_LENGTH (valtype
) > 2 * ARC_REGISTER_SIZE
);
881 debug_printf ("arc: return_value (readbuf = %s, writebuf = %s)\n",
882 host_address_to_string (readbuf
),
883 host_address_to_string (writebuf
));
885 if (writebuf
!= NULL
)
887 /* Case 1. GDB should not ask us to set a struct return value: it
888 should know the struct return location and write the value there
890 gdb_assert (!is_struct_return
);
891 arc_store_return_value (gdbarch
, valtype
, regcache
, writebuf
);
893 else if (readbuf
!= NULL
)
895 /* Case 2. GDB should not ask us to get a struct return value: it
896 should know the struct return location and read the value from there
898 gdb_assert (!is_struct_return
);
899 arc_extract_return_value (gdbarch
, valtype
, regcache
, readbuf
);
902 return (is_struct_return
903 ? RETURN_VALUE_STRUCT_CONVENTION
904 : RETURN_VALUE_REGISTER_CONVENTION
);
907 /* Return the base address of the frame. For ARC, the base address is the
911 arc_frame_base_address (struct frame_info
*this_frame
, void **prologue_cache
)
913 return (CORE_ADDR
) get_frame_register_unsigned (this_frame
, ARC_FP_REGNUM
);
916 /* Copy of gdb_buffered_insn_length_fprintf from disasm.c. */
918 static int ATTRIBUTE_PRINTF (2, 3)
919 arc_fprintf_disasm (void *stream
, const char *format
, ...)
924 struct disassemble_info
925 arc_disassemble_info (struct gdbarch
*gdbarch
)
927 struct disassemble_info di
;
928 init_disassemble_info (&di
, &null_stream
, arc_fprintf_disasm
);
929 di
.arch
= gdbarch_bfd_arch_info (gdbarch
)->arch
;
930 di
.mach
= gdbarch_bfd_arch_info (gdbarch
)->mach
;
931 di
.endian
= gdbarch_byte_order (gdbarch
);
932 di
.read_memory_func
= [](bfd_vma memaddr
, gdb_byte
*myaddr
,
933 unsigned int len
, struct disassemble_info
*info
)
935 return target_read_code (memaddr
, myaddr
, len
);
940 /* Implement the "skip_prologue" gdbarch method.
942 Skip the prologue for the function at PC. This is done by checking from
943 the line information read from the DWARF, if possible; otherwise, we scan
944 the function prologue to find its end. */
947 arc_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
950 debug_printf ("arc: skip_prologue\n");
953 const char *func_name
;
955 /* See what the symbol table says. */
956 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, NULL
))
958 /* Found a function. */
959 CORE_ADDR postprologue_pc
960 = skip_prologue_using_sal (gdbarch
, func_addr
);
962 if (postprologue_pc
!= 0)
963 return std::max (pc
, postprologue_pc
);
966 /* No prologue info in symbol table, have to analyze prologue. */
968 /* Find an upper limit on the function prologue using the debug
969 information. If the debug information could not be used to provide that
970 bound, then pass 0 and arc_scan_prologue will estimate value itself. */
971 CORE_ADDR limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
972 /* We don't have a proper analyze_prologue function yet, but its result
973 should be returned here. Currently GDB will just stop at the first
974 instruction of function if debug information doesn't have prologue info;
975 and if there is a debug info about prologue - this code path will not be
977 return (limit_pc
== 0 ? pc
: limit_pc
);
980 /* Implement the "print_insn" gdbarch method.
982 arc_get_disassembler () may return different functions depending on bfd
983 type, so it is not possible to pass print_insn directly to
984 set_gdbarch_print_insn (). Instead this wrapper function is used. It also
985 may be used by other functions to get disassemble_info for address. It is
986 important to note, that those print_insn from opcodes always print
987 instruction to the stream specified in the INFO. If this is not desired,
988 then either `print_insn` function in INFO should be set to some function
989 that will not print, or `stream` should be different from standard
993 arc_delayed_print_insn (bfd_vma addr
, struct disassemble_info
*info
)
995 int (*print_insn
) (bfd_vma
, struct disassemble_info
*);
996 /* exec_bfd may be null, if GDB is run without a target BFD file. Opcodes
997 will handle NULL value gracefully. */
998 print_insn
= arc_get_disassembler (exec_bfd
);
999 gdb_assert (print_insn
!= NULL
);
1000 return print_insn (addr
, info
);
1003 /* Baremetal breakpoint instructions.
1005 ARC supports both big- and little-endian. However, instructions for
1006 little-endian processors are encoded in the middle-endian: half-words are
1007 in big-endian, while bytes inside the half-words are in little-endian; data
1008 is represented in the "normal" little-endian. Big-endian processors treat
1009 data and code identically.
1011 Assuming the number 0x01020304, it will be presented this way:
1013 Address : N N+1 N+2 N+3
1014 little-endian : 0x04 0x03 0x02 0x01
1015 big-endian : 0x01 0x02 0x03 0x04
1016 ARC middle-endian : 0x02 0x01 0x04 0x03
1019 static const gdb_byte arc_brk_s_be
[] = { 0x7f, 0xff };
1020 static const gdb_byte arc_brk_s_le
[] = { 0xff, 0x7f };
1021 static const gdb_byte arc_brk_be
[] = { 0x25, 0x6f, 0x00, 0x3f };
1022 static const gdb_byte arc_brk_le
[] = { 0x6f, 0x25, 0x3f, 0x00 };
1024 /* For ARC ELF, breakpoint uses the 16-bit BRK_S instruction, which is 0x7fff
1025 (little endian) or 0xff7f (big endian). We used to insert BRK_S even
1026 instead of 32-bit instructions, which works mostly ok, unless breakpoint is
1027 inserted into delay slot instruction. In this case if branch is taken
1028 BLINK value will be set to address of instruction after delay slot, however
1029 if we replaced 32-bit instruction in delay slot with 16-bit long BRK_S,
1030 then BLINK value will have an invalid value - it will point to the address
1031 after the BRK_S (which was there at the moment of branch execution) while
1032 it should point to the address after the 32-bit long instruction. To avoid
1033 such issues this function disassembles instruction at target location and
1036 ARC 600 supports only 16-bit BRK_S.
1038 NB: Baremetal GDB uses BRK[_S], while user-space GDB uses TRAP_S. BRK[_S]
1039 is much better because it doesn't commit unlike TRAP_S, so it can be set in
1040 delay slots; however it cannot be used in user-mode, hence usage of TRAP_S
1041 in GDB for user-space. */
1043 /* Implement the "breakpoint_kind_from_pc" gdbarch method. */
1046 arc_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
1048 size_t length_with_limm
= gdb_insn_length (gdbarch
, *pcptr
);
1050 /* Replace 16-bit instruction with BRK_S, replace 32-bit instructions with
1051 BRK. LIMM is part of instruction length, so it can be either 4 or 8
1052 bytes for 32-bit instructions. */
1053 if ((length_with_limm
== 4 || length_with_limm
== 8)
1054 && !arc_mach_is_arc600 (gdbarch
))
1055 return sizeof (arc_brk_le
);
1057 return sizeof (arc_brk_s_le
);
1060 /* Implement the "sw_breakpoint_from_kind" gdbarch method. */
1062 static const gdb_byte
*
1063 arc_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
1067 if (kind
== sizeof (arc_brk_le
))
1069 return ((gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1075 return ((gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1081 /* Implement the "unwind_pc" gdbarch method. */
1084 arc_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1086 int pc_regnum
= gdbarch_pc_regnum (gdbarch
);
1087 CORE_ADDR pc
= frame_unwind_register_unsigned (next_frame
, pc_regnum
);
1090 debug_printf ("arc: unwind PC: %s\n", paddress (gdbarch
, pc
));
1095 /* Implement the "unwind_sp" gdbarch method. */
1098 arc_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1100 int sp_regnum
= gdbarch_sp_regnum (gdbarch
);
1101 CORE_ADDR sp
= frame_unwind_register_unsigned (next_frame
, sp_regnum
);
1104 debug_printf ("arc: unwind SP: %s\n", paddress (gdbarch
, sp
));
1109 /* Implement the "frame_align" gdbarch method. */
1112 arc_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1114 return align_down (sp
, 4);
1117 /* Frame unwinder for normal frames. */
1119 static struct arc_frame_cache
*
1120 arc_make_frame_cache (struct frame_info
*this_frame
)
1123 debug_printf ("arc: frame_cache\n");
1125 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1127 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1128 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1130 CORE_ADDR entrypoint
, prologue_end
;
1131 if (find_pc_partial_function (block_addr
, NULL
, &entrypoint
, &prologue_end
))
1133 struct symtab_and_line sal
= find_pc_line (entrypoint
, 0);
1135 /* No line info so use current PC. */
1136 prologue_end
= prev_pc
;
1137 else if (sal
.end
< prologue_end
)
1138 /* The next line begins after the function end. */
1139 prologue_end
= sal
.end
;
1141 prologue_end
= std::min (prologue_end
, prev_pc
);
1145 entrypoint
= get_frame_register_unsigned (this_frame
,
1146 gdbarch_pc_regnum (gdbarch
));
1150 /* Allocate new frame cache instance and space for saved register info.
1151 * FRAME_OBSTACK_ZALLOC will initialize fields to zeroes. */
1152 struct arc_frame_cache
*cache
1153 = FRAME_OBSTACK_ZALLOC (struct arc_frame_cache
);
1154 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1156 /* Should call analyze_prologue here, when it will be implemented. */
1161 /* Implement the "this_id" frame_unwind method. */
1164 arc_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1165 struct frame_id
*this_id
)
1168 debug_printf ("arc: frame_this_id\n");
1170 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1172 if (*this_cache
== NULL
)
1173 *this_cache
= arc_make_frame_cache (this_frame
);
1174 struct arc_frame_cache
*cache
= (struct arc_frame_cache
*) (*this_cache
);
1176 CORE_ADDR stack_addr
= cache
->prev_sp
;
1178 /* There are 4 possible situation which decide how frame_id->code_addr is
1181 1) Function is compiled with option -g. Then frame_id will be created
1182 in dwarf_* function and not in this function. NB: even if target
1183 binary is compiled with -g, some std functions like __start and _init
1184 are not, so they still will follow one of the following choices.
1186 2) Function is compiled without -g and binary hasn't been stripped in
1187 any way. In this case GDB still has enough information to evaluate
1188 frame code_addr properly. This case is covered by call to
1191 3) Binary has been striped with option -g (strip debug symbols). In
1192 this case there is still enough symbols for get_frame_func () to work
1193 properly, so this case is also covered by it.
1195 4) Binary has been striped with option -s (strip all symbols). In this
1196 case GDB cannot get function start address properly, so we return current
1199 CORE_ADDR code_addr
= get_frame_func (this_frame
);
1201 code_addr
= get_frame_register_unsigned (this_frame
,
1202 gdbarch_pc_regnum (gdbarch
));
1204 *this_id
= frame_id_build (stack_addr
, code_addr
);
1207 /* Implement the "prev_register" frame_unwind method. */
1209 static struct value
*
1210 arc_frame_prev_register (struct frame_info
*this_frame
,
1211 void **this_cache
, int regnum
)
1213 if (*this_cache
== NULL
)
1214 *this_cache
= arc_make_frame_cache (this_frame
);
1215 struct arc_frame_cache
*cache
= (struct arc_frame_cache
*) (*this_cache
);
1217 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1219 /* If we are asked to unwind the PC, then we need to return BLINK instead:
1220 the saved value of PC points into this frame's function's prologue, not
1221 the next frame's function's resume location. */
1222 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1223 regnum
= ARC_BLINK_REGNUM
;
1225 /* SP is a special case - we should return prev_sp, because
1226 trad_frame_get_prev_register will return _current_ SP value.
1227 Alternatively we could have stored cache->prev_sp in the cache->saved
1228 regs, but here we follow the lead of AArch64, ARM and Xtensa and will
1229 leave that logic in this function, instead of prologue analyzers. That I
1230 think is a bit more clear as `saved_regs` should contain saved regs, not
1233 Because value has been computed, "got_constant" should be used, so that
1234 returned value will be a "not_lval" - immutable. */
1236 if (regnum
== gdbarch_sp_regnum (gdbarch
))
1237 return frame_unwind_got_constant (this_frame
, regnum
, cache
->prev_sp
);
1239 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
, regnum
);
1242 /* Implement the "init_reg" dwarf2_frame method. */
1245 arc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1246 struct dwarf2_frame_state_reg
*reg
,
1247 struct frame_info
*info
)
1249 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1250 /* The return address column. */
1251 reg
->how
= DWARF2_FRAME_REG_RA
;
1252 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
1253 /* The call frame address. */
1254 reg
->how
= DWARF2_FRAME_REG_CFA
;
1257 /* Structure defining the ARC ordinary frame unwind functions. Since we are
1258 the fallback unwinder, we use the default frame sniffer, which always
1259 accepts the frame. */
1261 static const struct frame_unwind arc_frame_unwind
= {
1263 default_frame_unwind_stop_reason
,
1265 arc_frame_prev_register
,
1267 default_frame_sniffer
,
1273 static const struct frame_base arc_normal_base
= {
1275 arc_frame_base_address
,
1276 arc_frame_base_address
,
1277 arc_frame_base_address
1280 /* Initialize target description for the ARC.
1282 Returns TRUE if input tdesc was valid and in this case it will assign TDESC
1283 and TDESC_DATA output parameters. */
1286 arc_tdesc_init (struct gdbarch_info info
, const struct target_desc
**tdesc
,
1287 struct tdesc_arch_data
**tdesc_data
)
1290 debug_printf ("arc: Target description initialization.\n");
1292 const struct target_desc
*tdesc_loc
= info
.target_desc
;
1294 /* Depending on whether this is ARCompact or ARCv2 we will assign
1295 different default registers sets (which will differ in exactly two core
1296 registers). GDB will also refuse to accept register feature from invalid
1297 ISA - v2 features can be used only with v2 ARChitecture. We read
1298 bfd_arch_info, which looks like to be a safe bet here, as it looks like it
1299 is always initialized even when we don't pass any elf file to GDB at all
1300 (it uses default arch in this case). Also GDB will call this function
1301 multiple times, and if XML target description file contains architecture
1302 specifications, then GDB will set this architecture to info.bfd_arch_info,
1303 overriding value from ELF file if they are different. That means that,
1304 where matters, this value is always our best guess on what CPU we are
1305 debugging. It has been noted that architecture specified in tdesc file
1306 has higher precedence over ELF and even "set architecture" - that is,
1307 using "set architecture" command will have no effect when tdesc has "arch"
1309 /* Cannot use arc_mach_is_arcv2 (), because gdbarch is not created yet. */
1310 const int is_arcv2
= (info
.bfd_arch_info
->mach
== bfd_mach_arc_arcv2
);
1312 const char *const *core_regs
;
1313 const char *core_feature_name
;
1315 /* If target doesn't provide a description - use default one. */
1316 if (!tdesc_has_registers (tdesc_loc
))
1320 tdesc_loc
= tdesc_arc_v2
;
1322 debug_printf ("arc: Using default register set for ARC v2.\n");
1326 tdesc_loc
= tdesc_arc_arcompact
;
1328 debug_printf ("arc: Using default register set for ARCompact.\n");
1334 debug_printf ("arc: Using provided register set.\n");
1336 gdb_assert (tdesc_loc
!= NULL
);
1338 /* Now we can search for base registers. Core registers can be either full
1339 or reduced. Summary:
1341 - core.v2 + aux-minimal
1342 - core-reduced.v2 + aux-minimal
1343 - core.arcompact + aux-minimal
1345 NB: It is entirely feasible to have ARCompact with reduced core regs, but
1346 we ignore that because GCC doesn't support that and at the same time
1347 ARCompact is considered obsolete, so there is not much reason to support
1349 const struct tdesc_feature
*feature
1350 = tdesc_find_feature (tdesc_loc
, core_v2_feature_name
);
1351 if (feature
!= NULL
)
1353 /* Confirm that register and architecture match, to prevent accidents in
1354 some situations. This code will trigger an error if:
1356 1. XML tdesc doesn't specify arch explicitly, registers are for arch
1357 X, but ELF specifies arch Y.
1359 2. XML tdesc specifies arch X, but contains registers for arch Y.
1361 It will not protect from case where XML or ELF specify arch X,
1362 registers are for the same arch X, but the real target is arch Y. To
1363 detect this case we need to check IDENTITY register. */
1366 arc_print (_("Error: ARC v2 target description supplied for "
1367 "non-ARCv2 target.\n"));
1371 is_reduced_rf
= FALSE
;
1372 core_feature_name
= core_v2_feature_name
;
1373 core_regs
= core_v2_register_names
;
1377 feature
= tdesc_find_feature (tdesc_loc
, core_reduced_v2_feature_name
);
1378 if (feature
!= NULL
)
1382 arc_print (_("Error: ARC v2 target description supplied for "
1383 "non-ARCv2 target.\n"));
1387 is_reduced_rf
= TRUE
;
1388 core_feature_name
= core_reduced_v2_feature_name
;
1389 core_regs
= core_v2_register_names
;
1393 feature
= tdesc_find_feature (tdesc_loc
,
1394 core_arcompact_feature_name
);
1395 if (feature
!= NULL
)
1399 arc_print (_("Error: ARCompact target description supplied "
1400 "for non-ARCompact target.\n"));
1404 is_reduced_rf
= FALSE
;
1405 core_feature_name
= core_arcompact_feature_name
;
1406 core_regs
= core_arcompact_register_names
;
1410 arc_print (_("Error: Couldn't find core register feature in "
1411 "supplied target description."));
1417 struct tdesc_arch_data
*tdesc_data_loc
= tdesc_data_alloc ();
1419 gdb_assert (feature
!= NULL
);
1422 for (int i
= 0; i
<= ARC_LAST_CORE_REGNUM
; i
++)
1424 /* If rf16, then skip extra registers. */
1425 if (is_reduced_rf
&& ((i
>= ARC_R4_REGNUM
&& i
<= ARC_R9_REGNUM
)
1426 || (i
>= ARC_R16_REGNUM
&& i
<= ARC_R25_REGNUM
)))
1429 valid_p
= tdesc_numbered_register (feature
, tdesc_data_loc
, i
,
1432 /* - Ignore errors in extension registers - they are optional.
1433 - Ignore missing ILINK because it doesn't make sense for Linux.
1434 - Ignore missing ILINK2 when architecture is ARCompact, because it
1435 doesn't make sense for Linux targets.
1437 In theory those optional registers should be in separate features, but
1438 that would create numerous but tiny features, which looks like an
1439 overengineering of a rather simple task. */
1440 if (!valid_p
&& (i
<= ARC_SP_REGNUM
|| i
== ARC_BLINK_REGNUM
1441 || i
== ARC_LP_COUNT_REGNUM
|| i
== ARC_PCL_REGNUM
1442 || (i
== ARC_R30_REGNUM
&& is_arcv2
)))
1444 arc_print (_("Error: Cannot find required register `%s' in "
1445 "feature `%s'.\n"), core_regs
[i
], core_feature_name
);
1446 tdesc_data_cleanup (tdesc_data_loc
);
1451 /* Mandatory AUX registeres are intentionally few and are common between
1452 ARCompact and ARC v2, so same code can be used for both. */
1453 feature
= tdesc_find_feature (tdesc_loc
, aux_minimal_feature_name
);
1454 if (feature
== NULL
)
1456 arc_print (_("Error: Cannot find required feature `%s' in supplied "
1457 "target description.\n"), aux_minimal_feature_name
);
1458 tdesc_data_cleanup (tdesc_data_loc
);
1462 for (int i
= ARC_FIRST_AUX_REGNUM
; i
<= ARC_LAST_AUX_REGNUM
; i
++)
1464 const char *name
= aux_minimal_register_names
[i
- ARC_FIRST_AUX_REGNUM
];
1465 valid_p
= tdesc_numbered_register (feature
, tdesc_data_loc
, i
, name
);
1468 arc_print (_("Error: Cannot find required register `%s' "
1469 "in feature `%s'.\n"),
1470 name
, tdesc_feature_name (feature
));
1471 tdesc_data_cleanup (tdesc_data_loc
);
1477 *tdesc_data
= tdesc_data_loc
;
1482 /* Implement the "init" gdbarch method. */
1484 static struct gdbarch
*
1485 arc_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1487 const struct target_desc
*tdesc
;
1488 struct tdesc_arch_data
*tdesc_data
;
1491 debug_printf ("arc: Architecture initialization.\n");
1493 if (!arc_tdesc_init (info
, &tdesc
, &tdesc_data
))
1496 /* Allocate the ARC-private target-dependent information structure, and the
1497 GDB target-independent information structure. */
1498 struct gdbarch_tdep
*tdep
= XCNEW (struct gdbarch_tdep
);
1499 tdep
->jb_pc
= -1; /* No longjmp support by default. */
1500 struct gdbarch
*gdbarch
= gdbarch_alloc (&info
, tdep
);
1503 set_gdbarch_short_bit (gdbarch
, 16);
1504 set_gdbarch_int_bit (gdbarch
, 32);
1505 set_gdbarch_long_bit (gdbarch
, 32);
1506 set_gdbarch_long_long_bit (gdbarch
, 64);
1507 set_gdbarch_long_long_align_bit (gdbarch
, 32);
1508 set_gdbarch_float_bit (gdbarch
, 32);
1509 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
1510 set_gdbarch_double_bit (gdbarch
, 64);
1511 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
1512 set_gdbarch_ptr_bit (gdbarch
, 32);
1513 set_gdbarch_addr_bit (gdbarch
, 32);
1514 set_gdbarch_char_signed (gdbarch
, 0);
1516 set_gdbarch_write_pc (gdbarch
, arc_write_pc
);
1518 set_gdbarch_virtual_frame_pointer (gdbarch
, arc_virtual_frame_pointer
);
1520 /* tdesc_use_registers expects gdbarch_num_regs to return number of registers
1521 parsed by gdbarch_init, and then it will add all of the remaining
1522 registers and will increase number of registers. */
1523 set_gdbarch_num_regs (gdbarch
, ARC_LAST_REGNUM
+ 1);
1524 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
1525 set_gdbarch_sp_regnum (gdbarch
, ARC_SP_REGNUM
);
1526 set_gdbarch_pc_regnum (gdbarch
, ARC_PC_REGNUM
);
1527 set_gdbarch_ps_regnum (gdbarch
, ARC_STATUS32_REGNUM
);
1528 set_gdbarch_fp0_regnum (gdbarch
, -1); /* No FPU registers. */
1530 set_gdbarch_dummy_id (gdbarch
, arc_dummy_id
);
1531 set_gdbarch_push_dummy_call (gdbarch
, arc_push_dummy_call
);
1532 set_gdbarch_push_dummy_code (gdbarch
, arc_push_dummy_code
);
1534 set_gdbarch_cannot_fetch_register (gdbarch
, arc_cannot_fetch_register
);
1535 set_gdbarch_cannot_store_register (gdbarch
, arc_cannot_store_register
);
1537 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
1539 set_gdbarch_return_value (gdbarch
, arc_return_value
);
1541 set_gdbarch_skip_prologue (gdbarch
, arc_skip_prologue
);
1542 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1544 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, arc_breakpoint_kind_from_pc
);
1545 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, arc_sw_breakpoint_from_kind
);
1547 /* On ARC 600 BRK_S instruction advances PC, unlike other ARC cores. */
1548 if (!arc_mach_is_arc600 (gdbarch
))
1549 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
1551 set_gdbarch_decr_pc_after_break (gdbarch
, 2);
1553 set_gdbarch_unwind_pc (gdbarch
, arc_unwind_pc
);
1554 set_gdbarch_unwind_sp (gdbarch
, arc_unwind_sp
);
1556 set_gdbarch_frame_align (gdbarch
, arc_frame_align
);
1558 set_gdbarch_print_insn (gdbarch
, arc_delayed_print_insn
);
1560 set_gdbarch_cannot_step_breakpoint (gdbarch
, 1);
1562 /* "nonsteppable" watchpoint means that watchpoint triggers before
1563 instruction is committed, therefore it is required to remove watchpoint
1564 to step though instruction that triggers it. ARC watchpoints trigger
1565 only after instruction is committed, thus there is no need to remove
1566 them. In fact on ARC watchpoint for memory writes may trigger with more
1567 significant delay, like one or two instructions, depending on type of
1568 memory where write is performed (CCM or external) and next instruction
1569 after the memory write. */
1570 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 0);
1572 /* This doesn't include possible long-immediate value. */
1573 set_gdbarch_max_insn_length (gdbarch
, 4);
1575 /* Frame unwinders and sniffers. */
1576 dwarf2_frame_set_init_reg (gdbarch
, arc_dwarf2_frame_init_reg
);
1577 dwarf2_append_unwinders (gdbarch
);
1578 frame_unwind_append_unwinder (gdbarch
, &arc_frame_unwind
);
1579 frame_base_set_default (gdbarch
, &arc_normal_base
);
1581 /* Setup stuff specific to a particular environment (baremetal or Linux).
1582 It can override functions set earlier. */
1583 gdbarch_init_osabi (info
, gdbarch
);
1585 if (tdep
->jb_pc
>= 0)
1586 set_gdbarch_get_longjmp_target (gdbarch
, arc_get_longjmp_target
);
1588 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
1593 /* Implement the "dump_tdep" gdbarch method. */
1596 arc_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
1598 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1600 fprintf_unfiltered (file
, "arc_dump_tdep: jb_pc = %i\n", tdep
->jb_pc
);
1603 /* Wrapper for "maintenance print arc" list of commands. */
1606 maintenance_print_arc_command (char *args
, int from_tty
)
1608 cmd_show_list (maintenance_print_arc_list
, from_tty
, "");
1611 /* This command accepts single argument - address of instruction to
1615 dump_arc_instruction_command (char *args
, int from_tty
)
1618 if (args
!= NULL
&& strlen (args
) > 0)
1619 val
= evaluate_expression (parse_expression (args
).get ());
1621 val
= access_value_history (0);
1622 record_latest_value (val
);
1624 CORE_ADDR address
= value_as_address (val
);
1625 struct arc_instruction insn
;
1626 struct disassemble_info di
= arc_disassemble_info (target_gdbarch ());
1627 arc_insn_decode (address
, &di
, arc_delayed_print_insn
, &insn
);
1628 arc_insn_dump (insn
);
1631 /* Suppress warning from -Wmissing-prototypes. */
1632 extern initialize_file_ftype _initialize_arc_tdep
;
1635 _initialize_arc_tdep (void)
1637 gdbarch_register (bfd_arch_arc
, arc_gdbarch_init
, arc_dump_tdep
);
1639 initialize_tdesc_arc_v2 ();
1640 initialize_tdesc_arc_arcompact ();
1642 /* Register ARC-specific commands with gdb. */
1644 /* Add root prefix command for "maintenance print arc" commands. */
1645 add_prefix_cmd ("arc", class_maintenance
, maintenance_print_arc_command
,
1646 _("ARC-specific maintenance commands for printing GDB "
1648 &maintenance_print_arc_list
, "maintenance print arc ", 0,
1649 &maintenanceprintlist
);
1651 add_cmd ("arc-instruction", class_maintenance
,
1652 dump_arc_instruction_command
,
1653 _("Dump arc_instruction structure for specified address."),
1654 &maintenance_print_arc_list
);
1656 /* Debug internals for ARC GDB. */
1657 add_setshow_zinteger_cmd ("arc", class_maintenance
,
1659 _("Set ARC specific debugging."),
1660 _("Show ARC specific debugging."),
1661 _("Non-zero enables ARC specific debugging."),
1662 NULL
, NULL
, &setdebuglist
, &showdebuglist
);